JP2531440B2 - Al electrode wiring structure of semiconductor device - Google Patents
Al electrode wiring structure of semiconductor deviceInfo
- Publication number
- JP2531440B2 JP2531440B2 JP5151626A JP15162693A JP2531440B2 JP 2531440 B2 JP2531440 B2 JP 2531440B2 JP 5151626 A JP5151626 A JP 5151626A JP 15162693 A JP15162693 A JP 15162693A JP 2531440 B2 JP2531440 B2 JP 2531440B2
- Authority
- JP
- Japan
- Prior art keywords
- sio
- electrode wiring
- layer
- wiring
- wiring structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体デバイスのAl
電極配線の構造に関するものである。BACKGROUND OF THE INVENTION The present invention relates to an Al semiconductor device.
The present invention relates to the structure of electrode wiring.
【0002】[0002]
【従来の技術】従来、半導体デバイスの同一基板上の素
子間は、SiO2 系絶縁膜2で覆われたAl膜3によっ
て配線されていた(図2)。Al配線には、抵抗が低
く、加工も容易であるという利点があるものの、ストレ
スマイグレーションと呼ばれる断線現象が起こり、配線
の信頼性を考える上で大きな問題があった。2. Description of the Related Art Conventionally, wirings between elements on the same substrate of a semiconductor device have been formed by an Al film 3 covered with a SiO 2 insulating film 2 (FIG. 2). Although the Al wiring has the advantages of low resistance and easy processing, a disconnection phenomenon called stress migration occurs, which is a serious problem in considering the reliability of the wiring.
【0003】[0003]
【発明が解決しようとする課題】近年のデバイスの高集
積化にともなって配線長が増加し、さらに配線を流れる
電流密度が増大しており、配線の信頼性を高めることが
非常に重要である。特に産業上利用価値の高い、Siを
用いたデバイスにおいては、配線の信頼性向上は緊急の
課題である。これまでの信頼性向上の方法として、例え
ば特開平1−207952号公報にあるように、電極配
線材料とそれを被覆する絶縁体材料の間に、バリアメタ
ルを挿入する方法が用いられてきたが、バリアメタルの
膜質の制御、例えば組成制御が困難であるという問題が
あった。With the recent trend toward higher device integration, the wiring length has increased, and the current density flowing through the wiring has increased, so it is very important to improve the reliability of the wiring. . Particularly in a device using Si, which has a high industrial utility value, improvement of wiring reliability is an urgent issue. As a conventional method of improving reliability, a method of inserting a barrier metal between an electrode wiring material and an insulating material covering the electrode wiring material has been used as disclosed in, for example, Japanese Patent Application Laid-Open No. 1-207952. However, there is a problem that it is difficult to control the film quality of the barrier metal, for example, composition control.
【0004】本発明の目的は、SiO2 系絶縁材料で覆
われたAl電極配線構造の信頼性を、比較的容易な方法
で確保することにある。An object of the present invention is to secure the reliability of an Al electrode wiring structure covered with a SiO 2 insulating material by a relatively easy method.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明によるAl電極配線構造においては、Siと
Al2 O3 の極薄層を、SiO2 /Si/Al2 O3 /
Alの順に挿入する。In order to achieve the above object, in the Al electrode wiring structure according to the present invention, an extremely thin layer of Si and Al 2 O 3 is formed as SiO 2 / Si / Al 2 O 3 /
Insert in the order of Al.
【0006】電極配線構造では通常、下面側のAl/S
iO2 界面では自動的に安定化構造が実現されることか
ら、処理の必要な界面、電極配線の上面および側面(少
なくとも上面)である。電極配線構造の全面にSi層を
形成するのが最もよいが、上面にだけ形成してもある程
度の効果がある。Al2 O3 極薄層は、Al表面を室温
大気保管などによって得られる自然酸化膜で十分であ
る。ついで、熱応力をできるだけ小さくするため基板温
度を400℃以下に保ったまま、電極配線構造の上面と
側面に同時にSi層を形成する方法としては、CVD法
が適当である。SiH4 ガスを原料に用いる場合には、
堆積速度が小さくなりすぎるが、この問題はプラズマや
光照射で原料ガスを分解する方法により解決できる。ま
た後に述べるように電極配線構造の上面にだけSi層を
形成してもある程度の効果が得られるが、この場合はス
パッタ蒸着などの方法で良い。In the electrode wiring structure, Al / S on the lower surface side is usually used.
Since the stabilizing structure is automatically realized at the iO 2 interface, it is the interface that needs to be processed, and the upper surface and the side surface (at least the upper surface) of the electrode wiring. Although it is best to form the Si layer on the entire surface of the electrode wiring structure, there is some effect if it is formed only on the upper surface. As the Al 2 O 3 ultrathin layer, a natural oxide film obtained by storing the Al surface at room temperature in the air is sufficient. Then, the CVD method is suitable as a method for simultaneously forming the Si layer on the upper surface and the side surface of the electrode wiring structure while keeping the substrate temperature at 400 ° C. or lower in order to minimize the thermal stress. When SiH 4 gas is used as a raw material,
Although the deposition rate becomes too low, this problem can be solved by the method of decomposing the source gas by plasma or light irradiation. Further, as will be described later, a certain effect can be obtained by forming a Si layer only on the upper surface of the electrode wiring structure, but in this case, a method such as sputter deposition may be used.
【0007】Si膜はその形成方法に依存して、アモル
ファス、多結晶など様々な構造をとるが、いずれでも良
い。The Si film has various structures such as amorphous and polycrystalline depending on the forming method, but any of them may be used.
【0008】[0008]
【作用】ストレスマイグレーションと呼ばれる配線にお
ける断線現象は、四方をSiO2 絶縁カバー膜に覆われ
たAl配線に大きな引っ張り応力が生じ、これを緩和す
るようにAl原子が移動することによって起きるものと
考えられている。この配線に働く引っ張り応力の原因と
しては、従来熱応力或いはカバー膜の内部応力が挙げら
れていたが、最近その他にも、Al/SiO2 の界面反
応により配線体積が減少し、応力発生に寄与する可能性
があると報告された(アプライド・フィジックス・レッ
ターズ(Applied Physics Lette
rs)19991年,59巻680頁)。[Function] It is considered that the disconnection phenomenon in the wiring called stress migration is caused by a large tensile stress generated in the Al wiring covered with the SiO 2 insulating cover film on all sides and the Al atoms move so as to alleviate the tensile stress. Has been. Conventionally, thermal stress or internal stress in the cover film has been cited as the cause of the tensile stress acting on the wiring. Recently, however, the volume of the wiring is reduced by the Al / SiO 2 interface reaction, which contributes to the stress generation. (Applied Physics Letters (Applied Physics Letters)
rs) 1999, 59, 680).
【0009】本発明者は、配線金属Alと、絶縁膜Si
O2 との間の界面反応を抑えて、発生応力を低減すれ
ば、ストレスマイグレーションによって断線が起きるま
での時間を長くできるものと考えた。The present inventor has found that the wiring metal Al and the insulating film Si
It was considered that the time until disconnection occurs due to stress migration can be lengthened by suppressing the interfacial reaction with O 2 and reducing the generated stress.
【0010】そこで、AlとSiO2 の界面反応の様子
を、高分解能電子顕微鏡及びX線光電子光法を用いて調
べたところ、次の注目すべき事実を見いだした。すなわ
ちAl上にSiO2 を堆積したSiO2 /Al界面で
は、 3SiO2 +4Al → 3Si+2Al2 O3 (1) という界面反応が、アニールをすればする程進行するの
に対し、SiO2 上にAlを堆積したAl/SiO2 界
面ではこの反応が3nm以下で停止する。さらに詳細な
分析の結果、後者の界面では、(1)の反応が均一に2
−3nmの厚さまで進行してSiO2 /Si/Al2 O
3 /Alの積層構造が形成されていることを明らかにし
た。この構造における各界面の組み合わせが全て熱力学
的に安定であることが、全体として界面反応の進行が停
止する原因である。Then, the state of the interfacial reaction between Al and SiO 2 was examined by using a high resolution electron microscope and an X-ray photoelectron spectroscopy, and the following remarkable facts were found. That is, in the SiO 2 / Al interface by depositing a SiO 2 on Al, 3SiO 2 + 4Al → 3Si + 2Al 2 O 3 (1) of the interface reaction, while proceeds enough to be annealed, the Al on SiO 2 At the deposited Al / SiO 2 interface, this reaction stops below 3 nm. As a result of a more detailed analysis, the reaction of (1) is uniformly distributed at the latter interface.
-3 nm thick SiO 2 / Si / Al 2 O
It was clarified that a 3 / Al laminated structure was formed. The thermodynamically stable combination of each interface in this structure is the cause of the progress of the interface reaction as a whole.
【0011】次に本発明者は、Al上にSiO2 を堆積
した場合でも、何らかの方法で人工的にAl2 O3 層と
Si層を挿入すれば、(1)の反応の進行をくい止める
ことができると考えた。この考えにもとづき、洗浄なA
l表面を室温大気中で12時間放置して、厚さ1.5n
mの自然酸化膜を形成した後、スパッタ法により厚さ2
nmのアモルファスSi層を堆積し、続いてCVD法で
SiO2 膜を堆積したところ、500℃の熱処理に対す
る耐熱性が飛躍的に増大することが確認された。Next, the inventors of the present invention can prevent the reaction of (1) from proceeding even if SiO 2 is deposited on Al by artificially inserting the Al 2 O 3 layer and the Si layer by some method. I thought I could do it. Based on this idea, clean A
l The surface is left in a room temperature atmosphere for 12 hours to obtain a thickness of 1.5n.
After forming a natural oxide film of m
It was confirmed that the heat resistance to the heat treatment at 500 ° C. was dramatically increased by depositing the amorphous Si layer of nm and then depositing the SiO 2 film by the CVD method.
【0012】ここでAl電極配線とは、Si,Cu,P
dなどの微量不純物が含んでいても良く、またAl−S
i−Cuのように二種類以上含んでいてもよい。またS
iO2 系材料中にP,B,Asなどの他の元素が含まれ
ていてもよく、BPSGのように複数種類含まれていて
もよい。Here, the Al electrode wiring means Si, Cu, P
Trace impurities such as d may be included, and Al-S
It may contain two or more kinds such as i-Cu. Also S
Other elements such as P, B and As may be contained in the iO 2 -based material, or a plurality of kinds such as BPSG may be contained.
【0013】またSiOx Ny のようにNが含まれてい
る絶縁材料でもよい。Also, an insulating material containing N such as SiO x N y may be used.
【0014】[0014]
【実施例】次に本発明を実施例に基づいて説明する。Next, the present invention will be described based on embodiments.
【0015】(実施例1)図1に示すように、(10
0)面方位の基板1の表面に、熱酸化により厚さ500
nmのSiO2 膜2を形成した。この上にスパッタ法を
用いてSi1%を含むAl膜3を500nm堆積し、通
常のリソグラフィー技術を用いて、線幅0.5μmおよ
び1.0μmの配線パターンとした後、乾燥空気中に2
4時間保管してAl表面に自然酸化膜4を形成した。次
に、プラズマ−CVD法により、基板温度250℃で原
料ガス(SiH4 )を供給して厚さ2nmのアモルファ
スSi層5を形成し、配線表面以外のSiをリソグラフ
ィ技術で除去した。引き続いてCVD法でSiO2 層6
を200nm形成して配線構造をカバーした。(Embodiment 1) As shown in FIG.
The surface of the substrate 1 having the (0) plane orientation has a thickness of 500 due to thermal oxidation.
A SiO 2 film 2 having a thickness of 2 nm was formed. An Al film 3 containing 1% of Si is deposited thereon to a thickness of 500 nm by using a sputtering method, and a wiring pattern having line widths of 0.5 μm and 1.0 μm is formed by using an ordinary lithography technique.
After being stored for 4 hours, a natural oxide film 4 was formed on the Al surface. Next, a source gas (SiH 4 ) was supplied at a substrate temperature of 250 ° C. by a plasma-CVD method to form an amorphous Si layer 5 having a thickness of 2 nm, and Si other than the wiring surface was removed by a lithography technique. Subsequently, the SiO 2 layer 6 is formed by the CVD method.
Of 200 nm to cover the wiring structure.
【0016】200℃で断線に至るまでの時間を測定し
たところ、Si層を形成しなかった場合に比べて、Si
層を形成した場合の方が10倍長くなり信頼性が大幅に
向上した。また、500℃での加速試験をしたところ、
Si層を形成しなかった場合にはアニール30分で界面
反応が起こって配線構造が変形するのに対し、Si層を
形成した場合には5時間のアニールでも変化が見られ
ず、高温耐熱性は飛躍的に増大した。When the time until the disconnection was measured at 200 ° C., it was found that Si was compared with the case where the Si layer was not formed.
When the layer was formed, it was 10 times longer, and the reliability was significantly improved. Moreover, when an accelerated test at 500 ° C was performed,
When the Si layer is not formed, an interface reaction occurs in the annealing for 30 minutes and the wiring structure is deformed, whereas when the Si layer is formed, no change is observed even after annealing for 5 hours, and the high temperature heat resistance Has increased dramatically.
【0017】(実施例2)Si(100)基板表面に、
熱酸化により厚さ500nmのSiO2 膜を形成した。
この上にスパッタ法を用いてSi1%を含むAl膜を5
00nm堆積し、乾燥空気中に24時間保管してAl表
面に自然酸化膜を形成した。次にバイアススパッタ法に
より、Ar雰囲気中、基板温度200℃で、厚さ2nm
のアモルファスSi層を配線上面に堆積した。ここで通
常のリソグラフィー技術を用いて、線幅0.5μmおよ
び1.0μmの配線パターンを形成した後、テトラエキ
シシラン(TEOS)とオゾン(O3 )を原料とするC
VD法を用いて基板温度400℃で、SiO2 層300
nmのカバー膜を堆積した。Example 2 On the surface of a Si (100) substrate,
A 500 nm thick SiO 2 film was formed by thermal oxidation.
An Al film containing 1% of Si is formed on top of this by sputtering.
Then, a natural oxide film was formed on the Al surface by depositing it to a thickness of 00 nm and storing it in dry air for 24 hours. Next, by a bias sputtering method, in an Ar atmosphere, at a substrate temperature of 200 ° C. and a thickness of 2 nm.
Was deposited on the upper surface of the wiring. Here, a wiring pattern having line widths of 0.5 μm and 1.0 μm is formed by using an ordinary lithography technique, and then C using tetraexisilane (TEOS) and ozone (O 3 ) as raw materials is formed.
The SiO 2 layer 300 is formed at a substrate temperature of 400 ° C. using the VD method.
nm cover film was deposited.
【0018】200℃で断線に至るまでの時間を測定し
たところ、Si層を形成しなかった場合に比べて、Si
層を形成した場合の方が4倍長くなり信頼性が大幅に向
上した。When the time until breaking of the wire was measured at 200 ° C., it was found that Si was compared with the case where the Si layer was not formed.
When the layer was formed, it was four times longer and the reliability was significantly improved.
【0019】実施例1、2ではアモルファスSi層の厚
さを2nmとしたが1nmでもよい。Although the thickness of the amorphous Si layer is set to 2 nm in Examples 1 and 2, it may be set to 1 nm.
【0020】[0020]
【発明の効果】以上に説明したように、本発明によれ
ば、SiO2 系絶縁膜で四方を覆われたAl電極配線構
造の信頼性を大幅に向上させることができる。また製造
工程が容易なため、コストが安いという工業的な利点を
有する。As described above, according to the present invention, the reliability of the Al electrode wiring structure covered on all sides with the SiO 2 insulating film can be greatly improved. Further, since the manufacturing process is easy, there is an industrial advantage that the cost is low.
【図1】本発明のAl電極配線構造の一実施例を説明す
るための断面図である。FIG. 1 is a sectional view for explaining an embodiment of an Al electrode wiring structure of the present invention.
【図2】従来のAl電極配線構造の一例を説明する断面
図である。FIG. 2 is a sectional view illustrating an example of a conventional Al electrode wiring structure.
1 Si基板 2 SiO2 膜 3 Al膜 4 Al2 O3 5 Si 6 SiO2 層1 Si substrate 2 SiO 2 film 3 Al film 4 Al 2 O 3 5 Si 6 SiO 2 layer
Claims (2)
配線を被覆するSiO2 系絶縁材料との界面のうち少な
くとも上面に、SiとAl2 O3 の極薄層が、SiO2
/Si/Al2 O3 /Alの順に挿入されていることを
特徴とするAl電極配線構造。The method according to claim 1] Al at least on the upper surface of the interface between the main constituent element electrode wiring and the SiO 2 based insulating material covering the wiring, ultrathin layer of Si and Al 2 O 3 is, SiO 2
/ Si / Al 2 O 3 / Al is inserted in this order.
を用いる請求項1に記載のAl電極配線構造。 2. SiO x N y as a SiO 2 -based insulating material
The Al electrode wiring structure according to claim 1, wherein
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5151626A JP2531440B2 (en) | 1993-06-23 | 1993-06-23 | Al electrode wiring structure of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5151626A JP2531440B2 (en) | 1993-06-23 | 1993-06-23 | Al electrode wiring structure of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0722412A JPH0722412A (en) | 1995-01-24 |
JP2531440B2 true JP2531440B2 (en) | 1996-09-04 |
Family
ID=15522658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5151626A Expired - Fee Related JP2531440B2 (en) | 1993-06-23 | 1993-06-23 | Al electrode wiring structure of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2531440B2 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02121329A (en) * | 1988-10-31 | 1990-05-09 | Kawasaki Steel Corp | Manufacture of semiconductor device |
-
1993
- 1993-06-23 JP JP5151626A patent/JP2531440B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0722412A (en) | 1995-01-24 |
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