JP2531440B2 - Al electrode wiring structure of semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an Al semiconductor device.
The present invention relates to the structure of electrode wiring.

[0002]

2. Description of the Related Art Conventionally, wirings between elements on the same substrate of a semiconductor device have been formed by an Al film 3 covered with a SiO ₂ insulating film 2 (FIG. 2). Although the Al wiring has the advantages of low resistance and easy processing, a disconnection phenomenon called stress migration occurs, which is a serious problem in considering the reliability of the wiring.

[0003]

With the recent trend toward higher device integration, the wiring length has increased, and the current density flowing through the wiring has increased, so it is very important to improve the reliability of the wiring. . Particularly in a device using Si, which has a high industrial utility value, improvement of wiring reliability is an urgent issue. As a conventional method of improving reliability, a method of inserting a barrier metal between an electrode wiring material and an insulating material covering the electrode wiring material has been used as disclosed in, for example, Japanese Patent Application Laid-Open No. 1-207952. However, there is a problem that it is difficult to control the film quality of the barrier metal, for example, composition control.

An object of the present invention is to secure the reliability of an Al electrode wiring structure covered with a SiO ₂ insulating material by a relatively easy method.

[0005]

In order to achieve the above object, in the Al electrode wiring structure according to the present invention, an extremely thin layer of Si and Al ₂ O ₃ is formed as SiO ₂ / Si / Al ₂ O ₃ /
Insert in the order of Al.

In the electrode wiring structure, Al / S on the lower surface side is usually used.
Since the stabilizing structure is automatically realized at the iO ₂ interface, it is the interface that needs to be processed, and the upper surface and the side surface (at least the upper surface) of the electrode wiring. Although it is best to form the Si layer on the entire surface of the electrode wiring structure, there is some effect if it is formed only on the upper surface. As the Al ₂ O ₃ ultrathin layer, a natural oxide film obtained by storing the Al surface at room temperature in the air is sufficient. Then, the CVD method is suitable as a method for simultaneously forming the Si layer on the upper surface and the side surface of the electrode wiring structure while keeping the substrate temperature at 400 ° C. or lower in order to minimize the thermal stress. When SiH ₄ gas is used as a raw material,
Although the deposition rate becomes too low, this problem can be solved by the method of decomposing the source gas by plasma or light irradiation. Further, as will be described later, a certain effect can be obtained by forming a Si layer only on the upper surface of the electrode wiring structure, but in this case, a method such as sputter deposition may be used.

The Si film has various structures such as amorphous and polycrystalline depending on the forming method, but any of them may be used.

[0008]

[Function] It is considered that the disconnection phenomenon in the wiring called stress migration is caused by a large tensile stress generated in the Al wiring covered with the SiO ₂ insulating cover film on all sides and the Al atoms move so as to alleviate the tensile stress. Has been. Conventionally, thermal stress or internal stress in the cover film has been cited as the cause of the tensile stress acting on the wiring. Recently, however, the volume of the wiring is reduced by the Al / SiO ₂ interface reaction, which contributes to the stress generation. (Applied Physics Letters (Applied Physics Letters)
rs) 1999, 59, 680).

The present inventor has found that the wiring metal Al and the insulating film Si
It was considered that the time until disconnection occurs due to stress migration can be lengthened by suppressing the interfacial reaction with O ₂ and reducing the generated stress.

Then, the state of the interfacial reaction between Al and SiO ₂ was examined by using a high resolution electron microscope and an X-ray photoelectron spectroscopy, and the following remarkable facts were found. That is, in the SiO ₂ / Al interface by depositing a SiO ₂ on _{Al, 3SiO 2 + 4Al → 3Si} + 2Al 2 O 3 (1) of the interface reaction, while proceeds enough to be annealed, the Al on SiO ₂ At the deposited Al / SiO ₂ interface, this reaction stops below 3 nm. As a result of a more detailed analysis, the reaction of (1) is uniformly distributed at the latter interface.
-3 nm thick SiO ₂ / Si / Al ₂ O
It was clarified that a ₃ / Al laminated structure was formed. The thermodynamically stable combination of each interface in this structure is the cause of the progress of the interface reaction as a whole.

Next, the inventors of the present invention can prevent the reaction of (1) from proceeding even if SiO ₂ is deposited on Al by artificially inserting the Al ₂ O ₃ layer and the Si layer by some method. I thought I could do it. Based on this idea, clean A
l The surface is left in a room temperature atmosphere for 12 hours to obtain a thickness of 1.5n.
After forming a natural oxide film of m
It was confirmed that the heat resistance to the heat treatment at 500 ° C. was dramatically increased by depositing the amorphous Si layer of nm and then depositing the SiO ₂ film by the CVD method.

Here, the Al electrode wiring means Si, Cu, P
Trace impurities such as d may be included, and Al-S
It may contain two or more kinds such as i-Cu. Also S
Other elements such as P, B and As may be contained in the iO ₂ -based material, or a plurality of kinds such as BPSG may be contained.

Also, an insulating material containing N such as SiO _x N _y may be used.

[0014]

Next, the present invention will be described based on embodiments.

(Embodiment 1) As shown in FIG.
The surface of the substrate 1 having the (0) plane orientation has a thickness of 500 due to thermal oxidation.
A SiO ₂ film 2 having a thickness of 2 nm was formed. An Al film 3 containing 1% of Si is deposited thereon to a thickness of 500 nm by using a sputtering method, and a wiring pattern having line widths of 0.5 μm and 1.0 μm is formed by using an ordinary lithography technique.
After being stored for 4 hours, a natural oxide film 4 was formed on the Al surface. Next, a source gas (SiH ₄ ) was supplied at a substrate temperature of 250 ° C. by a plasma-CVD method to form an amorphous Si layer 5 having a thickness of 2 nm, and Si other than the wiring surface was removed by a lithography technique. Subsequently, the SiO ₂ layer 6 is formed by the CVD method.
Of 200 nm to cover the wiring structure.

When the time until the disconnection was measured at 200 ° C., it was found that Si was compared with the case where the Si layer was not formed.
When the layer was formed, it was 10 times longer, and the reliability was significantly improved. Moreover, when an accelerated test at 500 ° C was performed,
When the Si layer is not formed, an interface reaction occurs in the annealing for 30 minutes and the wiring structure is deformed, whereas when the Si layer is formed, no change is observed even after annealing for 5 hours, and the high temperature heat resistance Has increased dramatically.

Example 2 On the surface of a Si (100) substrate,
A 500 nm thick SiO ₂ film was formed by thermal oxidation.
An Al film containing 1% of Si is formed on top of this by sputtering.
Then, a natural oxide film was formed on the Al surface by depositing it to a thickness of 00 nm and storing it in dry air for 24 hours. Next, by a bias sputtering method, in an Ar atmosphere, at a substrate temperature of 200 ° C. and a thickness of 2 nm.
Was deposited on the upper surface of the wiring. Here, a wiring pattern having line widths of 0.5 μm and 1.0 μm is formed by using an ordinary lithography technique, and then C using tetraexisilane (TEOS) and ozone (O ₃ ) as raw materials is formed.
The SiO ₂ layer 300 is formed at a substrate temperature of 400 ° C. using the VD method.
nm cover film was deposited.

When the time until breaking of the wire was measured at 200 ° C., it was found that Si was compared with the case where the Si layer was not formed.
When the layer was formed, it was four times longer and the reliability was significantly improved.

Although the thickness of the amorphous Si layer is set to 2 nm in Examples 1 and 2, it may be set to 1 nm.

[0020]

As described above, according to the present invention, the reliability of the Al electrode wiring structure covered on all sides with the SiO ₂ insulating film can be greatly improved. Further, since the manufacturing process is easy, there is an industrial advantage that the cost is low.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining an embodiment of an Al electrode wiring structure of the present invention.

FIG. 2 is a sectional view illustrating an example of a conventional Al electrode wiring structure.

[Explanation of symbols]

1 Si substrate 2 SiO ₂ film 3 Al film 4 Al ₂ O ₃ 5 Si 6 SiO ₂ layer

Claims (2)

(57) [Claims] The method according to claim 1] Al at least on the upper surface of the interface between the main constituent element electrode wiring and the SiO ₂ based insulating material covering the wiring, ultrathin layer of Si and Al ₂ O ₃ is, SiO ₂
/ Si / Al ₂ O ₃ / Al is inserted in this order. _2. SiO _x N _y as a SiO ₂ -based insulating material
The Al electrode wiring structure according to claim 1, wherein