JP2530410B2 - Decoding circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a service using a product code as an error correction method, for example, a decoding circuit used in an FM multiplex broadcasting system for multiplexing stereo audio and other digital data for FM broadcasting and broadcasting. Regarding

SUMMARY OF THE INVENTION The present invention relates to decoding when a product code is used as an error correction method, and particularly when a CRC code is added to each horizontal code packet for error detection. In the decoding, the error correction is reduced by performing the decoding of the vertical code by using the information on whether the error is detected by the CRC code of the horizontal code.

[0003]

2. Description of the Related Art In a system that uses a product code as an error correction method, such as an FM multiplex broadcasting system that multiplexes stereo sound and other digital data into an FM broadcast and broadcasts, when decoding the product code, In many cases, a circuit sequentially decodes each packet in the horizontal direction (or the vertical direction), and then sequentially decodes each packet in the direction orthogonal thereto, that is, in the vertical direction (or the horizontal direction).

The Ready Robinson decoding method is known as a method capable of maximizing the correction capability of the product code.

[0005]

However, in the above-described conventional decoding circuit, when a normal decoding method is used, when there are many errors, the error increases unnecessarily due to erroneous correction, and the error is corrected by the horizontal code. There is a risk that the decrypted data may be destroyed by erroneous correction due to vertical decoding.

Further, in order to maximize the correction ability of the product code, when the Ready Robinson decoding method is used,
There is a problem that the amount of calculation increases and the time required for the decoding process increases.

In view of the above-mentioned circumstances, the present invention can decode a vertical code by using an error correction code (CRC code) added to each packet and prevent erroneous correction due to the vertical code. An object of the present invention is to provide a decoding circuit capable of preventing data obtained correctly by a horizontal code from being destroyed by decoding by a vertical code.

[0008]

In order to achieve the above object, the invention according to claim 1 is a decoding circuit for decoding a packet using a product code as an error correction method, wherein a horizontal code is applied to each packet. When performing decoding, the horizontal code decoding unit that performs error detection by CRC check and adds a flag indicating whether or not each packet is correctly decoded, and a vertical code for each packet processed by this horizontal code decoding unit. When decoding the code, a vertical code decoding unit for correcting only erroneous data by using the flag information of each packet provided by the horizontal code decoding unit is provided.

[0009]

In the above structure, when the horizontal code is decoded for each packet, an error is detected by CRC check and a flag is added to indicate whether each packet is correctly decoded. When decoding the vertical code for each packet, only the erroneous data is corrected by using the flag information of each packet added by the horizontal code.

[0010]

1 is a block diagram showing an example of a decoding circuit when demodulating a mobile reception FM multiplex broadcast by applying an embodiment of the decoding circuit according to the present invention.

The decoding circuit shown in this figure is a synchronous reproduction circuit 1.
, Changeover switch 2, and two frame buffer circuits 3
, CPU 5, and (272, 190) code decoding circuit 6
, CRC check circuit 7, and data buffer circuit 8
And a data display circuit 9 for sequentially fetching each packet 10 (see FIG. 2) by each frame buffer circuit 3 and checking whether each horizontal packet 10 has been correctly corrected by the horizontal decoding operation. After making the determination and adding the determination result to each packet 10, only the bits of the packet 10 that have a decoding error due to the decoding operation in the horizontal direction when performing the decoding operation for the vertical code of each packet 10 After that, the packet 10 having a decoding error in the first horizontal decoding operation is horizontally decoded to determine whether or not each horizontal packet 10 has been correctly corrected.

As shown in FIG. 2, each packet 10 constitutes one frame with 272 packets 10 which are long in the lateral direction. Of these 272 packets 10, 19 packets are assigned from the top.
The first 190 bits of the 0 packet 10 is composed of a data part and a CRC code part, and the subsequent 82 bits are a horizontal parity part corresponding to each packet 10 on a one-to-one basis.

Of the 272 packets 10, each of the 191st to 272nd packets 10 from the top is a vertical parity part for the 190 packets 10 from the top.

Further, the synchronous reproduction circuit 1 detects whether or not the flow of the input packet 10 includes a frame synchronous signal indicating a delimiter of each frame, and generates a synchronous detection signal each time it detects this. Then, this is supplied to the changeover switch 2 and the CPU 5.

The change-over switch 2 is a switch that switches each time a sync detection signal is output from the sync reproduction circuit 1, and takes in each input packet 10 and selects it as the currently selected frame buffer. Supply to the circuit 3.

Each frame buffer circuit 3 fetches and stores each packet 10 supplied via the changeover switch 2, and also reads each stored packet 10 in response to a read command from the CPU 5, This is supplied to the CPU 5, and when a write command is supplied from this CPU 5, the packet 10 supplied together with this write command is fetched and stored.

Also, the (272, 190) code decoding circuit 6
Every time a packet 10 is supplied from the CPU 5, the packet is fetched, the contents of the parity part thereof are decoded, and it is checked whether or not there is an error in the contents of the data part and the CRC code part forming the packet. If there is, the contents of the data part and the CRC code part are corrected within the range of the correction condition from the CPU 5, and the packet 10 that has been corrected or the packet 10 before correction is sent to the CPU 5 when it cannot be corrected. Supply.

The CRC check circuit 7 is the CPU
Every time the packet 10 is supplied from the packet 5, the packet 10 is fetched and the packet 10 is read based on the contents of the CRC code part.
It is checked whether or not the contents of the data part is correct, and the check result is supplied to the CPU 5.

The data buffer circuit 8 is the CPU
When 5 to 1 frame of data is supplied, this is taken in and stored, and the content is supplied to the data display circuit 9.

Each time data is supplied from the data buffer circuit 8, the data display circuit 9 fetches and displays the data.

The CPU 5 reads the packet from the frame buffer circuit 3 and the packet 10 on the basis of the programmed processing procedure, various timing signals output from each circuit section, various check results, and the like.
Various processings such as the transfer processing of, the determination processing of the check result, and the like are performed.

The operation of this embodiment will be described below with reference to the flow chart shown in FIG.

First, every time each packet 10 is input,
The synchronous reproduction circuit 1 checks the presence / absence of a synchronization signal in 1-frame units, and every time the synchronization signal is detected, the changeover switch 2 is switched so that the packets 10 are alternately stored in the frame buffer circuits 3 in frame units. .

Further, in parallel with this operation, if a sync detection signal indicating that the sync signal is detected is output from the sync reproduction circuit 1, the CPU 5 is in a memory full state by the previous packet fetch operation. With respect to each packet 10 stored in the frame buffer circuit 3 of the above, each horizontal packet 10 is sequentially taken out from the top of the frame, transferred to the (272, 190) code decoding circuit 6, and decoded. Data part and CRC of this packet 10
Check if there is an error in the contents of the code part.

If there is an error in the contents of the data part and the CRC code part of the packet 10, the CPU 5 controls the (272, 190) code decoding circuit 6 to change the data part and the CRC code part of the packet 10. After the correction, whether or not the syndrome is zero is checked, and if it is zero, it is determined that the error correction is successful (step ST1).

Thereafter, the CPU 5 causes the (272, 19)
0) The error-corrected packet 10 is taken out from the code decoding circuit 6 and transferred to the CRC check circuit 7 for CR.
It is checked whether or not the data check by the C code is OK (step ST2).

Then, the error correction by the (272, 190) code decoding circuit 6 is successful, and the CRC check circuit 7
If the CRC check by OK is OK, the CPU 5 determines that the content of the data portion of the packet 10 is correct, sets a data OK flag for the packet 10, and sets the packet 10 as the corrected packet 10. Return to the frame buffer circuit 3 (step ST
4).

If error correction by the (272, 190) code decoding circuit 6 fails or an error is detected by the CRC check by the CRC check circuit 7, CP
U5 determines that there is an error in the data of this packet 10, sets a flag of data FAULT for this packet 10, and returns the original packet 10 (packet 10 before correction) to the frame buffer circuit 3 (step ST3, ST4).

Hereinafter, the CPU 5 uses the frame buffer circuit 3
The horizontal error correction described above is sequentially executed for each of the remaining packets 10 stored in the packet, and either the data OK flag or the data FAULT flag is set for each packet 10 (step ST1). ~ ST
5). This series of processing is performed for all 272 packets.

Next, when this process is completed, the CPU 5
For each packet 10 stored in the frame buffer circuit 3, for example, each packet 10 in the vertical direction is sequentially taken out from the left side of the frame, and this is taken out (272, 190)
The data is transferred to the code decoding circuit 6 to be decoded, and it is checked whether there is an error. If there is an error, the data O
After correcting the bits excluding the data in which the flag of K is set, that is, the bits of the data in which the flag of data FAULT is set, it is checked whether the syndrome is zero. If this is zero, It is determined that the error correction has succeeded, the corrected packet 10 is returned to the frame buffer circuit 3 (step ST6), and if the syndrome does not become zero even after the correction operation is performed, it is determined that the error correction has failed. The original packet 10 (packet 10 before correction) is returned to the frame buffer circuit 3 (step ST7).

Hereinafter, the CPU 5 uses the frame buffer circuit 3
The error correction in the vertical direction described above is sequentially performed on the remaining packets 10 stored in each of the packets, and the bits except for the data flagged as data OK, that is, the data flagged as FAULT Correction is performed on the bits (steps ST6 to ST8). This series of processing is performed for all 272 packets.

Next, when this process is completed, the CPU 5
Among the horizontal packets 10 stored in the frame buffer circuit 3, the data packets 10 for which the flag of data FAULT is set are sequentially taken out from the top of the frame (step ST9), and these are (272, 19).
0) The code is transferred to the code decoding circuit 6 to be decoded, and it is checked whether there is an error. If there is an error, it is corrected, and then it is checked whether the syndrome is zero. If this is zero, , It is determined that the error correction is successful.

Thereafter, the CPU 5 causes the (272, 19)
0) The error-corrected packet 10 is taken out from the code decoding circuit 6 and transferred to the CRC check circuit 7 for CR.
Check whether the data check by C code is OK.

Then, the error correction by the (272, 190) code decoding circuit 6 is successful, and the CRC check circuit 7
If the CRC check is OK, the CPU 5 determines that the data in the packet 10 is correct, sets a data OK flag in the packet 10, and sets the packet 10 as a corrected packet 10 in the frame buffer circuit. Return to 3.

If the error correction by the (272, 190) code decoding circuit 6 fails or an error is detected by the CRC check by the CRC check circuit 7, the CP
U5 determines that there is an error in the data of this packet 10, sets a flag of data FAULT for this packet 10, and returns the original packet 10 (packet 10 before correction) to the frame buffer circuit 3 (step ST10).

Hereinafter, the CPU 5 uses the frame buffer circuit 3
The horizontal error correction described above is sequentially executed for each of the remaining packets 10 in which the data FAULT flag is set, and either the data OK flag or the data FAULT flag is set for each packet. Set up (steps ST9 to ST11).

When the above-mentioned processing is completed for all the packets 10 stored in the frame buffer circuit 3, the CPU 5 causes the frame buffer circuit 3 to operate.
Each packet 10 stored in the frame buffer circuit 3 is read out and transferred to the data buffer circuit 8 so that only correct data is displayed on the data display circuit 9 and the contents of the frame buffer circuit 3 are cleared.

As described above, in this embodiment, it is determined whether or not each horizontal packet 10 has been correctly corrected by the horizontal decoding operation, and the correctly corrected packet 10 is flagged as data OK. Data FAU for packet 10 that could not be corrected
After the LT flag is set, it is determined whether or not each vertical packet 10 has been correctly corrected by the vertical decoding operation, and the data FAULT flag is set in the horizontal decoding operation for the packet 10 that has not been correctly corrected. Only the bits of the standing data are corrected, and the bits of the data in which the data OK flag is set are not corrected, and then the packet 10 in which the data FAULT flag is set is set in the first horizontal decoding operation. On the other hand, since it is determined by the horizontal decoding operation whether or not each horizontal packet 10 has been correctly corrected, it is possible to prevent an erroneous correction due to the vertical code while suppressing the calculation amount to be low. Thus, it is possible to prevent the data obtained correctly in (4) from being destroyed by decoding by the vertical code.

Further, in the above-described embodiment, when the vertical decoding operation is performed, only the bits of the data for which the data FAULT flag is set are corrected by the first horizontal decoding operation to make the data OK. Although the bit correction of the flagged data is not performed, the algorithm of this portion may be changed as shown in the flowchart of FIG.

As shown in this figure, in this algorithm,
First, every time each packet 10 is input, the synchronous reproduction circuit 1
Checks the presence or absence of a synchronization signal in 1-frame units, and switches the changeover switch 2 every time the synchronization signal is detected to store the packets 10 in the frame buffer circuits 3 alternately in frame units.

Further, in parallel with this operation, if the sync detection signal indicating that the sync signal is detected is output from the sync reproduction circuit 1, the CPU 5 is the one whose memory is full due to the previous packet fetch operation. For each packet 10 stored in the frame buffer circuit 3 of FIG. 2, lateral packets are sequentially taken out from the top of the frame, transferred to the (272, 190) code decoding circuit 6 for decoding, and an error is generated. If there is an error, it is corrected, and then it is checked whether the syndrome is zero. If it is zero, it is determined that the error correction is successful (step ST15).

After that, the CPU 5 causes the above (272, 19)
0) The error-corrected packet 10 is taken out from the code decoding circuit 6 and transferred to the CRC check circuit 7 for CR.
It is checked whether or not the data check by the C code is OK (step ST16).

Then, the error correction by the (272, 190) code decoding circuit 6 is successful, and the CRC check circuit 7
If the CRC check is OK, the CPU 5 determines that the data in the packet 10 is correct, sets a data OK flag in the packet 10, and sets the packet 10 as a corrected packet 10 in the frame buffer circuit. It returns to 3 (step ST18).

If the error correction by the (272, 190) code decoding circuit 6 fails or an error is detected by the CRC check by the CRC check circuit 7, the CP
U5 determines that there is an error in the data of this packet 10, sets a flag of data FAULT for this packet 10, and returns the original packet 10 (packet 10 before correction) to the frame buffer circuit 3 (step ST17).

Hereinafter, the CPU 5 is the frame buffer circuit 3
The horizontal error correction described above is sequentially executed for each of the remaining packets 10 stored in the packet, and either the data OK flag or the data FAULT flag is set for each packet 10 (step ST15). ~ ST
19). This series of processing is performed for all 272 packets.

Next, when this process is completed, the CPU 5
For each packet 10 stored in the frame buffer circuit 3, sequentially extracts each packet 10 in the vertical direction from the horizontal direction of the frame, transfers it to the (272, 190) code decoding circuit 6, and decodes it. It is checked whether there is an error, and if there is an error, correction is performed (step ST20), and it is checked whether the syndrome is zero (step ST21). If this is zero, the bit corrected by correction is corrected. It is checked whether all the flags in the horizontal direction for the packet 10 are data FAULT. And the modified bit packet 1
If all the flags in the horizontal direction for 0 are data FAULT, the CPU 5 determines that the error correction is successful, returns the corrected packet to the frame buffer circuit 3 (step ST22), and the syndrome is generated even if the correction operation is performed. If the data does not become zero, or if even one horizontal flag for the packet 10 of the bit corrected by the correction operation is data OK (steps ST21 and ST22), it is determined that the error correction has failed and the original packet 10 is detected. The (uncorrected packet 10) is returned to the frame buffer circuit 3 (step ST23).

Hereinafter, the CPU 5 uses the frame buffer circuit 3
The error correction in the vertical direction described above is sequentially performed on the remaining packets 10 stored in each of the packets, and the bits except for the data flagged as data OK, that is, the data flagged as FAULT Is corrected (steps ST20 to ST24).

Then, when this process is completed, the CPU 5
Of the packets 10 in the horizontal direction stored in the frame buffer circuit 3, the packets 10 with the flag of data FAULT set are sequentially taken out from the top of the frame (step ST25), and coded as (272, 190). The data is transferred to the decoding circuit 6 to be decoded, and it is checked whether there is an error. If there is an error, it is corrected, and then it is checked whether the syndrome is zero. If this is zero, error correction is performed. Judge as successful.

After that, the CPU 5 causes the above (272, 19)
0) An error-corrected packet 10 is taken out from the code decoding circuit 6 and transferred to the CRC check circuit 7 for CR.
Check if the data check by C code is OK.

Then, the error correction by the (272, 190) code decoding circuit 6 is successful, and the CRC check circuit 7
If the CRC check is OK, the CPU 5 determines that the data in the packet 10 is correct, sets a data OK flag in the packet 10, and sets the packet 10 as a corrected packet 10 in the frame buffer circuit. Return to 3.

If the error correction by the (272, 190) code decoding circuit 6 fails or an error is detected by the CRC check by the CRC check circuit 7, the CP
U5 determines that there is an error in the data of this packet 10, sets a flag of data FAULT for this packet 10, and returns the original packet 10 (packet 10 before correction) to the frame buffer circuit 3 (step ST26).

Hereinafter, the CPU 5 is the frame buffer circuit 3
The horizontal error correction described above is sequentially performed on each of the remaining packets 10 in which the data FAULT flag is set, and either the data OK flag or the data FAULT flag is applied to each packet 10. Is set up (steps ST25 to ST27).

When all the packets 10 stored in the frame buffer circuit 3 are processed as described above, the CPU 5 causes the frame buffer circuit 3 to operate.
Each packet 10 stored in the frame buffer circuit 3 is read out and transferred to the data buffer circuit 8 so that only correct data is displayed on the data display circuit 9 and the contents of the frame buffer circuit 3 are cleared.

Even in this case, as in the above-described embodiment, it is possible to prevent the erroneous correction due to the vertical code while suppressing the calculation amount low, and to decode the data correctly obtained by the horizontal code by the vertical code. Can be prevented from being destroyed.

In each of the above-described embodiments, the horizontal code is first decoded, then the vertical code is decoded, and finally the horizontal code is decoded only once again.
Each of these decoding operations may be repeated a preset number of times to further improve the correction capability.

[0056]

As described above, according to the first aspect of the invention, the vertical code is decoded by using the error correction code (CRC code) added to each packet, and the amount of calculation is thereby increased. Can be suppressed to a low level, erroneous correction due to the vertical code can be prevented, and data correctly obtained by the horizontal code can be prevented from being destroyed by decoding by the vertical code.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a decoding circuit when demodulating an FM multiplex broadcast for mobile reception by applying an embodiment of the decoding circuit according to the present invention.

2 is a mobile reception F demodulated by the decoding circuit shown in FIG.
It is a map figure which shows the format example of the packet used by M multiplex broadcasting.

3 is a flowchart showing an example of an operation algorithm of the decoding circuit shown in FIG.

4 is a flowchart showing another example of the operation algorithm of the decoding circuit shown in FIG.

[Explanation of symbols]

 1 Synchronous reproduction circuit 2 Changeover switch 3 Frame buffer circuit 5 CPU5 6 (272, 190) code decoding circuit 7 CRC check circuit 8 Data buffer circuit 9 Data display circuit

Front page continuation (72) Inventor Shigeki Moriyama 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology research institute of the Japan Broadcasting Corporation (72) Tomohiro Saito 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcast Technology Laboratory (72) Inventor Tadashi Isobe 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcast Technology Laboratory (72) Inventor Satoru Yamada 1-1-10 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation (56) References JP 62-183632 (JP, A) JP 62-24739 (JP, A) JP 62-271535 (JP, A) JP 62-245725 (JP) , A)

Claims (1)

(57) [Claims] 1. A decoding circuit for decoding a packet using a product code as an error correction method, wherein when a horizontal code is decoded for each packet, a CRC is used.
When performing horizontal code decoding on each packet processed by this horizontal code decoding unit, and a horizontal code decoding unit that adds a flag indicating whether or not each packet is correctly decoded by performing error detection by checking, A decoding circuit, comprising: a vertical code decoding unit that corrects only erroneous data using the flag information of each packet provided by the horizontal code decoding unit.