JP2528669B2 - Programmable minute delay time setting circuit - Google Patents

Description

The present invention relates to a programmable minute delay time setting circuit with high measurement accuracy, which is suitable for a phase margin test circuit in a magnetic disk device, and has a problem in a conventional programmable minute delay time setting circuit. In order to reduce the number of data measurements and to rationalize the time and cost when correcting the correction data, the VF in the phase margin test circuit of the magnetic disk device
In a circuit for setting the phase delay time of the data signal Di with respect to the O clock signal CLK, an address signal corresponding to the data signal Di and the delay time is input, and the data signal Di is delayed based on the address signal and output. Programmable delay line, correction data for the delay time, which is connected to the programmable delay line and is stored in a storage element in advance, is converted into a control voltage by a D / A converter and input, and the input control voltage Enables the active signal to correct the output signal of the programmable delay line.
And a delay line.

[Industrial applications]

The present invention relates to a programmable minute delay time setting circuit suitable for a phase margin test circuit in a magnetic disk device and having high measurement accuracy.

[Conventional technology]

FIG. 5 is a circuit diagram showing a conventional programmable minute delay time setting circuit, and FIG. 6 is its timing chart. In the figure, 1 is a CR charge / discharge type monostable multivibrator, 2 is a register, 3 is a programmable read only memory (PROM), 4 is a D / A converter, and 5 is a flip-flop.

Among various performance test items for magnetic disk devices, there is a phase margin test. This is the reference VFO when demodulating the data recorded on the magnetic disk.
It tests the allowable range of the phase shift between the clock signal CLK and the read data signal Di, and writes a pattern called the worst pattern on the medium that is most likely to cause a data error, and shifts the phase of the read pattern by an external circuit. Is a test for measuring the amount of phase shift that does not cause a data error.

Referring now to FIG. 5, the CR charge / discharge type monostable multivibrator 1 is triggered by the input data signal Di and has a time width τ determined by the output voltage V from the capacitor C, the resistor R and the D / A converter 4. Output DT. This signal DT acts as a gate signal on the VFO clock signal CLK in the flip-flop 5. That is, according to the timing chart of FIG. 6, the monostable multivibrator 1 is triggered by the rising edge of the data signal shown in FIG. 6C, and the output signal DT having the time width τ is output. The reference is when the rising timing t1 of the VFO clock signal CLK shown in FIG. 9A is at the intermediate position of the time width τ of the signal DT, but the position is deviated depending on the written pattern. If this deviation is large, the data cannot be demodulated. Therefore, as a test of the margin, a phase margin test is performed by a method of narrowing the time width τ.

If the phase margin is 2.0 nanoseconds (ns), a delay time circuit with a resolution of 0.1 ns is required to perform the test with sufficient accuracy. Conventionally, a desired delay time τ has been obtained by changing the charging voltage V in the CR charge / discharge type monostable multivibrator 1 by the D / A converter 4.

In order to set the delay time by the conventional circuit shown in FIG. 5, first, data having a weight of 1 bit 0.1 ns is set in the register 2 by a command from a microprocessor (not shown). This data is the value directly D /
Even if it is set in the A converter 4, the output signal DT is not accurately output with a resolution of 0.1 ns because of the non-linear characteristic of the monostable multivibrator 1. That is, the D / A converter 4
The output voltage V with respect to the input data of 1 changes linearly, but the delay time τ with respect to the charging voltage V in the monostable multivibrator 1 responds exponentially as shown in FIG. Therefore, the correction data is measured before the test. That is, in FIG. 5, input data is supplied to the D / A converter 4 by the switch group 6 and the delay time τ of the monostable multivibrator 1 corresponding thereto is measured. From the result, the correction data is written in the PROM 3 so that the delay time τ linearly proportional to the bit weight of the command from the microprocessor can be obtained. After that, the switch group 6 is separated during normal use.

[Problems to be solved by the invention]

As described above, in the conventional programmable micro delay time setting circuit system, the charging voltage V applied to the charging / discharging circuit by the capacitor C and the resistor R is corrected by the correction data stored in the PROM 3 after the command from the microprocessor is corrected. / A
The desired delay time τ was obtained by changing it by the converter 4. In general, this delay time τ has a width of about 20 ns, so that covering a resolution of 0.1 ns requires a large amount of correction data measurement of 200 times.

In addition, a PROM or EPRO is used as the correction data storage element 3.
M is used, but when correcting the correction data, it is necessary to remove, replace, or attach the parts. Further, a mechanical switch group 6 for measuring the correction data is also required.

The technical problem of the present invention is to solve such problems in the conventional programmable minute delay time setting circuit, reduce the number of times of correction data measurement, and rationalize time and cost when correcting correction data. To do so.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the technical means according to the present invention taken to solve this problem is a conventional CR in a circuit for measuring the phase delay time of the data signal Di with respect to the VFO clock signal CLK. Instead of the charge / discharge type monostable multivibrator, the data signal Di and the address signal corresponding to the delay time from the storage element 10 are input, and the data signal
A programmable delay line 7 for delaying and outputting Di based on an address signal, and correction data for the delay time, which is serially connected to the programmable delay line 7 and stored in a storage element 9 in advance, are stored in the D / A converter 13. Is converted into a control voltage by the input, and the active delay line 8 for correcting the output signal of the programmable delay line 7 by the input control voltage.
And a circuit configuration provided with.

[Action]

According to this technical means, the mode is determined in the register 12 by the instruction from the microprocessor (not shown), the mode of the storage elements 9 and 10 is determined, and the data signal DLTD is advanced with respect to the VFO clock signal CLK. To decide whether it is late or late. That is, in the correction data measurement mode, a value is set as the input data of the D / A converter 13 from the microprocessor and written in the storage element 9. In the operation mode, if the desired delay time is set in the register 12 by a command from the microprocessor, for example, the delay time obtained by the programmable delay line 7 and the active delay line 8 can be set to 1 by 1 ns step.
If it is ~ 10 ns, the data from the storage element 10 gives a delay time of an integer digit in 1 ns step in the programmable delay line 7, and the active delay line 8 stores it so as to have an accurate desired delay time. The correction data stored in the element 9 is converted into the control voltage V by the D / A converter 13 and given.

At this time, if the data signal DLDT output from the active delay line 8 is in phase advance with respect to the VFO clock signal CLK, the two AND circuits 14 and 15 in the AND circuits 14 and 15 are ANDed by the register 12.
Select circuit 14 and input data signal Di is AND circuit 14 and O
It is led to the programmable delay line 7 via the R circuit 16.

On the other hand, when the data signal DLDT is delayed with respect to the VFO clock signal CLK, the AND circuit 15 is selected by the register 12 and
The input data signal Di is input to the programmable delay line 7 via the delay line 11 which gives a delay time corresponding to a half cycle of the clock signal CLK. The correction data for the active delay line 8 at this time can be used by code conversion of the correction data used for the phase advance, and the correction data need only be measured once during the phase advance.

〔Example〕

Next, practical examples of how the programmable minute delay time setting circuit according to the present invention is embodied will be described. FIG. 2 shows an example in which the programmable minute delay time setting circuit according to the present invention is applied to a phase-magazine tester of a magnetic disk device. In the figure, those having the same functions as those of the configuration shown in FIG. It is attached. The delay line formed by the programmable delay line 17 and the active delay line 18 gives a delay time of 0.1 ns, and the delay line formed by the programmable delay line 19 and the active delay line 20 gives a delay time of 1 ns step. Delay circuit, 21, 22
Is a storage element for storing the correction data for the active delay lines 18 and 20, 23 is a storage element for selecting the delay time in the programmable delay lines 17 and 19, 24 and 25 are D / A converters, and 26 and 27 are VFO clock signals. A delay line and an active delay line that set a delay time corresponding to a half cycle of CLK.

Next, referring to the timing chart shown in FIG.
Since the cycle of the VFO clock signal CLK is 20 ns here, the delay time given to the input data signal Di with respect to the VFO clock signal CLK may be ± 10 ns. In the state shown in the figure, the rising edge of the input data signal Di is + Cns with respect to the rising edge timing t2 of the VFO clock signal CLK.
It indicates that the phase is advanced, and the maximum is 10 ns. Based on this, the delay time is given to the input data signal Di.In this way, when the phase is advanced, the AND circuit 14 is selected by the register 12 based on the instruction from the microprocessor, and the input data signal Di is selected. The signal Di is input to the programmable delay line 17 without passing through the delay line 26 and the active delay line 27. The programmable delay line 17 gives a delay time of 0.1 ns step, and 16 steps can be changed by the 4-bit address line from the storage element 23. The active delay line 18 is for making the delay time setting of the programmable delay line 17 accurate, the correction data for the desired delay time is read from the storage element 21 by the register 12, and the control voltage V2 is set by the D / A converter 24. Convert and add to active delay line 18.

The programmable delay line 19 gives a delay time of 1 ns step, and can be changed in 16 steps by a 4-bit address line from the storage element 23. The active delay line 20 is for accurately setting the delay time of the programmable delay line 19, and the register 12 reads the correction data for the delay time from the storage element 22, and the D / A converter 25 sets the control voltage V3. Convert and add to active delay line 20. That is, when the input data signal Di passes through the delay lines 17 to 20, 0 to 10n in 0.1ns steps.
A delay time of s is given.

On the other hand, in FIG. 3, when the output data signal DLDT delayed in time, that is, delayed from the timing t2 of the VFO clock signal CLK is obtained, the AND circuit 15 is selected by the register 12 based on the instruction from the microprocessor. Then, the input data signal Di is offset by the delay time To via the delay line 26 and the active delay line 27, and is input to the programmable delay line 17. The delay line 26 has a delay time To corresponding to a half cycle of the VFO clock signal CLK. By adjusting the control voltage V1 with the variable resistor 28 and adding it to the active delay line 27, the accuracy of the delay time To is improved. Go up. Output data signal
DLDT is the maximum from timing t2 of VFO clock signal CLK.
A delay of 10 ns is enough. For the setting, the delay line 17
Do by ~ 20. But in this case, VFO clock signal C
Considering the timing t2 of LK as a reference, and looking at the time width until the rising edge of the output data signal DLDT, the delay line 17
The delay time given by ~ 20 works in the opposite direction.
That is, 1 ns to the input data signal Di which has advanced by 10 ns
If the delay time is given, the time width from the timing t2 of the VFO clock signal CLK is 9 ns. On the other hand, if the pro-reset delay time is given to the input data signal Di by the delay lines 26 and 27 to obtain the delayed output data signal DLDT, the delay time by the delay lines 17 to 20 is directly output to the VFO clock signal CLK. The delay time of the data signal DLDT is 1 ns in this case. Therefore, considering the phase margin of ± with reference to the timing t2, the delay time given in the delay lines 17 to 20 acts in the direction of widening the phase margin on the + side and in the direction of narrowing it on the − side. From this relationship, it can be applied to the case of the late phase by converting the code of the correction data at the time of the early phase.

Further, as the storage elements 21 to 23, a PROM or an EPROM can be used as in the conventional case, but when the correction data is corrected, it has the above-mentioned problems.
This can be solved by using a non-volatile RAM (NOV.RAM) instead of the storage elements 21 to 23. FIG. 4 shows an embodiment thereof, which has a configuration applied to the 1 ns step delay line in FIG. In FIG. 4, 28 is a non-volatile RAM replacing the memory element 22 of FIG.
The / A converter 25 and the delay lines 19 and 20 are the same as those in FIG. 29, 30, and 31 are nonvolatile RAs, respectively.
The M28 address register, data register, and mode register are shown below. First, the procedure for measuring the correction data is to set the nonvolatile RAM 28 to the write mode by the register 31 based on a command from the microprocessor, and set the address 00-FF to 1 by the 8-bit address line from the register 29.
The data when increasing bit by bit is obtained from the register 30 and written. Next, set the read mode by register 31 and set the output data signal from active delay line 20.
The address value of the nonvolatile RAM 28 that can obtain a delay time of exactly 1 to 10 ns in the DLDT is stored in the memory of the microprocessor. Next, set the address value of the nonvolatile RAM 28 with the 1-bit weight of 1 ns to the rester 29, and
The address value is equivalent to s. The data obtained at the time of measuring the correction data for each address is set in the register 30 and written in the S.RAM in the nonvolatile RAM 28. This writing is executed by connecting / disconnecting the signal WT from the register 31. Further, after this writing is completed, the signal STOR from the register 31 causes the non-volatile E ² .PR in the non-volatile RAM 28.
Data is written to OM.

Immediately after the power is turned on, the operation of the correction circuit is as follows.
When LL occurs, the correction data is transferred from E ² .PRAM in the nonvolatile RAM 28 to S.RAM. Then the signal WI from register 31
Causes the nonvolatile RAM 28 to enter the read mode and register 2
By setting the desired delay time in 9, the correction data for the delay time is read out, and the D / A converter 25
Is converted into a control voltage V3, applied to the active delay line 20, and an output data signal DLDT delayed by a predetermined time is obtained.

By adopting the same structure as this also in the 0.1 ns delay line, the whole structure can be formed.

〔The invention's effect〕

As described above, according to the present invention, as a method for giving a delay time to a data signal, the address signal corresponding to the delay time from the data signal Di and the storage element is used instead of the CR charge / discharge type monostable multivibrator that is conventionally used. And are entered,
A programmable delay line that delays and outputs the data signal Di based on the address signal, and correction data that is connected in series to the programmable delay line and that is stored in advance in the storage element for the delay time is controlled by the D / A converter. An active delay line is used after being converted into a voltage and input, and the input control voltage corrects the output signal of the programmable delay line. With this control voltage, a minute delay time can be set with high accuracy, for example, 1 ns ± 0.1 ns.
Thus, for example, for a delay time width of 20ns, 0.1n
In order to obtain the accuracy of s resolution, conventionally, it was necessary to measure the correction data 200 times, whereas in the circuit of the present invention,
Consider 20 ns as ± 10 ns, and for this 10 ns time width, 1 ns
It is sufficient to divide the delay line of steps and the delay line of 0.1 ns steps and measure the correction data for 20 steps in each of 10 steps. For this measurement, for example, only the + side should be performed, and for the-side, the input data signal should be VF
By delaying the phase corresponding to a half cycle of the O clock signal, that is, 180 degrees in phase, the correction data obtained on the + side can be code-converted and used as it is. Therefore, it is possible to reduce the number of times of correction data measurement, which was conventionally required 200 times, to 20 times, which is 1/10, and it is possible to shorten the time and improve the measurement accuracy. Moreover, by using a delay line instead of the conventional CR charge / discharge monostable multivibrator, the reliability with respect to the change of the delay time with time and the change of temperature can be improved.

As a storage element, in the case of a conventional PROM, it is necessary to discard and replace it, and in the case of an EPROM, an erasing operation is required. In both cases, the power supply needs to be cut off, which is a waste of time.
However, by making this storage element a non-volatile ROM,
Since the correction data can be corrected while the power is on, other tasks can be started in the processor performing multitask processing, and it is possible to prevent deterioration of processing efficiency due to maintenance work.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic principle of a programmable minute delay time setting circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of the circuit, FIG. 3 is its timing chart, and FIG. Explanatory diagram when the storage element is a non-volatile ROM, FIG. 5 is a block diagram showing a conventional programmable minute delay time setting circuit, FIG. 6 is a timing chart of the circuit, and FIG. 7 is a CR charge / discharge type monostable circuit. It is a characteristic view which shows the relationship of the delay time with respect to the control voltage of a multivibrator. In the figure, 1 is a monostable multivibrator, 2, 12,
29, 30, 31 are registers, 3, 9, 10, 21, 22, 23, 28 are storage elements, 4, 13, 24, 25 are D / A converters, 7, 17, 1
9 is a programmable delay line, 8, 18, 20, 27 are active delay lines, and 11 and 26 are delay lines.

Claims (3)

(57) [Claims] 1. A circuit for setting a phase delay time of a data signal Di with respect to a VFO clock signal CLK in a phase margin test circuit of a magnetic disk device, wherein an address signal corresponding to the data signal Di and the delay time is input, A programmable delay line 7 that delays and outputs the signal Di based on the address signal, and correction data for the delay time, which is serially connected to the programmable delay line 7 and is stored in a storage element 9 in advance, is D / A programmable converter including an active delay line 8 which is converted into a control voltage by the A converter 13 and is input, and which corrects the output signal of the programmable delay line 7 by the input control voltage. Minute delay time setting circuit. 2. A delay line 11 for providing a delay time corresponding to a half cycle of the VFO clock signal CLK is programmable.
A data signal DLDT equivalent in phase to the VFO clock signal CLK is added by adding the delay time correction data to the preceding stage of the delay line 7 and performing code conversion of the delay time correction data as the correction data of the active delay line 8. The programmable minute delay time setting circuit according to claim (1). 3. The pluggable minute delay time setting circuit according to claim 1, wherein a non-volatile RAM is used as the memory element 9.