JP2527630Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2527630Y2 JP2527630Y2 JP3833091U JP3833091U JP2527630Y2 JP 2527630 Y2 JP2527630 Y2 JP 2527630Y2 JP 3833091 U JP3833091 U JP 3833091U JP 3833091 U JP3833091 U JP 3833091U JP 2527630 Y2 JP2527630 Y2 JP 2527630Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead wire
- solder
- metal
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【0001】[0001]
【考案の属する分野の説明】本考案はダイオード、トラ
ンジスタ等の半導体装置の電極構造に関するものであ
る。Description of the Field of the Invention The present invention relates to an electrode structure of a semiconductor device such as a diode and a transistor.
【0002】[0002]
【従来の技術】図1は従来のPN接合型半導体装置(チ
ップ)の断面図及びその組立説明図で図中1は半導体基
板(N)、2はP型領域、3は接合Jを保護するバシベ
ーションとしてのSiO2又はSi3N4、4は半田付
用金属(Ni、Cr等のオーミック用メタル)、5は半
田である。このチップを半田耐熱、温度サイクル、断続
通電等の温度ストレスに対し信頼性良く組み立てるに
は、(b)図に示す如く、接合近傍面の半田厚(矢印A
部)を確保し、温度ストレスに対し吸収してやる事が公
知の事実である。しかし乍ら、アキシャル形では、リー
ド線6の自重、リード線の加工バラツキその他組み立て
上のバラツキ等により、リード底部が直接半田付用金属
と接触してしまう事がある。(C)図は、リード底部の
凹凸により、その一部が半田付金属と接触した事を示す
図である。これらの素子に前記のストレスを加えると、
接触面にクラックCが入り、P−N接合特性を損なう事
がある。2. Description of the Related Art FIG. 1 is a sectional view of a conventional PN junction type semiconductor device (chip) and its assembly explanatory diagram. In FIG. 1, 1 is a semiconductor substrate (N), 2 is a P type region, and 3 is a junction J. SiO 2 or Si 3 N 4 as passivation, 4 is a soldering metal (ohmic metal such as Ni or Cr), and 5 is a solder. In order to assemble this chip with high reliability against temperature stress such as solder heat resistance, temperature cycle, and intermittent energization, as shown in FIG.
It is a well-known fact that a certain part is secured and absorbed against temperature stress. However, in the axial type, the lead bottom may come into direct contact with the metal for soldering due to the weight of the lead wire 6, variation in processing of the lead wire, and variation in assembly. (C) is a view showing that a part of the lead is in contact with the soldered metal due to the unevenness at the bottom of the lead. When the above stress is applied to these elements,
Cracks C may be formed on the contact surface and the PN junction characteristics may be impaired.
【0003】そこで本願出願人は上記の問題を改善する
ために先に図2の構造を提案した。この構造はショット
キバリアダイオードに適用した例を示すもので図中7は
モリブデン(Mo)等のショットキメタル、8はリード
線より軟らかく、且つ半田より高融点の金属層(A1
等)で上記構造に於いて温度ストレスによる各材料の伸
縮を半田で吸収していたのに対し、この構造は金属層8
を設ける事により、半田の代替をさせるところにある。[0003] The applicant of the present invention has previously proposed the structure shown in FIG. 2 in order to improve the above problem. This structure shows an example applied to a Schottky barrier diode. In the drawing, 7 is a Schottky metal such as molybdenum (Mo), 8 is a metal layer (A1) softer than a lead wire and having a higher melting point than solder.
In the above structure, the expansion and contraction of each material due to the temperature stress was absorbed by the solder.
Is to replace the solder.
【0004】[0004]
【従来技術の問題点】この構造のものは、A1が半田の
代替となり、極めて高い温度ストレスに対する信頼性を
得る事が確認されているが、チップ表面にA1が露出す
る為、耐湿性が劣る欠点がある。この理由は、パッケー
ジ内部には塩素系物質が存在しており、パッケージ内に
進入してきた水分を吸収し、それが溶液となってA1を
腐食し、絶縁膜3にA1が流れ出る。A1の腐食が発生
した場合、絶縁膜にA1が流れ出してしまい、絶縁膜上
を電流が流れやすくなり信頼性に問題がある。In this structure, it has been confirmed that A1 can be used as a substitute for soldering to obtain reliability against extremely high temperature stress. However, since A1 is exposed on the chip surface, the moisture resistance is inferior. There are drawbacks. The reason for this is that a chlorine-based substance is present inside the package and absorbs the moisture that has entered the package, which becomes a solution and corrodes A1, and A1 flows out into the insulating film 3. When the corrosion of A1 occurs, A1 flows out into the insulating film, and a current easily flows on the insulating film, and there is a problem in reliability.
【0005】[0005]
【考案の目的】本考案は、チップの両端を半田付するダ
イオードに於いて、温度ストレス耐量及び耐湿性の耐量
を向上せしめる構造を供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a diode for soldering both ends of a chip with a structure capable of improving a temperature stress resistance and a humidity resistance.
【0006】[0006]
【実施例】図3は本考案の一実施例構造を示す断面図で
PN接合型半導体装置の例を示す。本考案は温度ストレ
スを吸収するA1等の金属層8の端部周囲を絶縁層9で
覆うことにより該金属層の表面露出部を防ぐようにした
ものである。このように構成すれば、絶縁層9でA1を
コートカバーする事で塩素系物質の付着が防げられA1
の腐食が防止される。因みにこの構造の製法について説
明すると、先ずシリコン基板1の全面に絶縁膜3(Si
O2膜、PSG膜)を形成しエッチングを行なう。次い
で、全面に蒸着で膜厚3μmのA1膜8を形成し、エッ
チング後基板を450〜500℃、N2雰囲気中で15
分程度アニールする。さらに、全面に絶縁膜9(PSG
膜)を形成、エツチングしA1をコートカバーする。最
後に、半田との接触を容易にするため蒸着で膜厚450
0〜5000ÅのCr−Ni膜4を形成し、その後半田
付を行う。FIG. 3 is a sectional view showing the structure of an embodiment of the present invention and shows an example of a PN junction type semiconductor device. In the present invention, the surface of the metal layer 8 such as A1 which absorbs the thermal stress is prevented by covering the periphery of the metal layer 8 with an insulating layer 9. With this configuration, by covering A1 with the insulating layer 9, it is possible to prevent the chlorine-based substance from adhering.
Corrosion is prevented. Incidentally, the manufacturing method of this structure will be described. First, the insulating film 3 (Si
O 2 film performs formed by etching the PSG film). Next, an A1 film 8 having a thickness of 3 μm is formed on the entire surface by evaporation, and the substrate is etched at 450 to 500 ° C. in an N 2 atmosphere for 15 minutes.
Anneal for about a minute. Further, an insulating film 9 (PSG) is formed on the entire surface.
A film is formed and etched to cover A1. Finally, to facilitate contact with the solder, a film thickness of 450
A Cr—Ni film 4 of 0 to 5000 ° is formed, and then soldering is performed.
【0007】図4は本考案の他の実施例構造でショット
キバリア型半導体装置に適用した例を示す。FIG. 4 shows another embodiment of the present invention applied to a Schottky barrier type semiconductor device.
【0008】[0008]
【考案の効果】本考案の半導体装置によればA1を形成
したのち、絶縁膜でA1をコートカバーする事でアフタ
ーコロージョンが防止され、したがって信頼性の向上に
効果がある。According to the semiconductor device of the present invention, after A1 is formed, after-coating A1 with an insulating film prevents after-corrosion, which is effective in improving reliability.
【図1】従来装置の構造図FIG. 1 is a structural view of a conventional apparatus.
【図2】従来装置の構造図FIG. 2 is a structural view of a conventional device.
【図3】本考案の一実施例構造を示す断面図FIG. 3 is a sectional view showing the structure of the embodiment of the present invention;
【図4】本考案装置の他の実施例構造図FIG. 4 is a structural view of another embodiment of the present invention;
1 半導体基板 2 P型領域 3 酸化膜 4 半田付用金属(オーミックメタル) 5 半田 6 リード線 7 ショットキメタル(Mo) 8 金属層(A1) 9 絶縁層 Reference Signs List 1 semiconductor substrate 2 P-type region 3 oxide film 4 metal for soldering (ohmic metal) 5 solder 6 lead wire 7 Schottky metal (Mo) 8 metal layer (A1) 9 insulating layer
Claims (1)
導体基体の電極部とリード線もしくは接続子を半田を介
して接続するようにした半導体装置において、前記電極
部とリード線もしくは接続子の間に前記リード線もしく
は接続子の材質より軟らかく且つ前記半田より高融点を
もつ金属層を設けると共に前記金属層の端部に跨って絶
縁層を設けたことを特徴とする半導体装置。1. A semiconductor device in which an electrode portion of a semiconductor substrate having a Schottky junction or a PN junction is connected to a lead wire or a connector via solder, between the electrode portion and the lead wire or the connector. A semiconductor device, comprising: a metal layer softer than a material of the lead wire or the connector and having a higher melting point than the solder; and an insulating layer provided over an end of the metal layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3833091U JP2527630Y2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3833091U JP2527630Y2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04137042U JPH04137042U (en) | 1992-12-21 |
JP2527630Y2 true JP2527630Y2 (en) | 1997-03-05 |
Family
ID=31919884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3833091U Expired - Fee Related JP2527630Y2 (en) | 1991-03-05 | 1991-03-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2527630Y2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005286197A (en) * | 2004-03-30 | 2005-10-13 | Shindengen Electric Mfg Co Ltd | Semiconductor device and manufacturing method thereof |
US9202935B2 (en) * | 2013-10-01 | 2015-12-01 | Vishay General Semiconductor Llc | Zener diode haviing a polysilicon layer for improved reverse surge capability and decreased leakage current |
-
1991
- 1991-03-05 JP JP3833091U patent/JP2527630Y2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH04137042U (en) | 1992-12-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |