JP2527158B2 - Flickering compensator - Google Patents

Flickering compensator

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Publication number
JP2527158B2
JP2527158B2 JP18249383A JP18249383A JP2527158B2 JP 2527158 B2 JP2527158 B2 JP 2527158B2 JP 18249383 A JP18249383 A JP 18249383A JP 18249383 A JP18249383 A JP 18249383A JP 2527158 B2 JP2527158 B2 JP 2527158B2
Authority
JP
Japan
Prior art keywords
signal
voltage
load
circuit
flicker
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18249383A
Other languages
Japanese (ja)
Other versions
JPS6074961A (en
Inventor
健二 森貞
広隆 沢村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichicon Capacitor Ltd
Original Assignee
Nichicon Capacitor Ltd
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Filing date
Publication date
Application filed by Nichicon Capacitor Ltd filed Critical Nichicon Capacitor Ltd
Priority to JP18249383A priority Critical patent/JP2527158B2/en
Publication of JPS6074961A publication Critical patent/JPS6074961A/en
Application granted granted Critical
Publication of JP2527158B2 publication Critical patent/JP2527158B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/12Arrangements for reducing harmonics from ac input or output

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Power Conversion In General (AREA)

Description

【発明の詳細な説明】 本発明は、交流回路における大容量の間欠運転負荷で
特に抵抗溶接機などのフリッカーが発生する電力回路に
おいて、負荷と並列に接続したフリッカー補償装置に関
するものである。
Description: TECHNICAL FIELD The present invention relates to a flicker compensating device connected in parallel with a load in a power circuit in which flicker occurs, particularly in a resistance welding machine under a large capacity intermittent operation load in an AC circuit.

従来、フリッカー補償装置は第1図(a)のごとく溶
接機1の電流を交流器2で検出し、制御部3で電力用半
導体スイッチ(サイリスタ)4をON、OFF制御して直列
リアクトル5と進相コンデンサ6によって無効電力の制
御が行われていた。しかしながら、この方式では無効電
力の検出応答遅れによって、第1図(b)に示すように
無効電力補償後の回路電圧は、電力用半導体スイッチ4
の投入遅れによる最初の0.5サイクルと、負荷の通電終
了後の半導体スイッチの0.5サイクルの開放遅れによっ
て生じる回路電圧が凸凹状に降下および上昇し、充分な
フリッカーの改善効果が得られなかった。
Conventionally, the flicker compensator detects the current of the welding machine 1 by the AC device 2 as shown in FIG. 1 (a), and the control unit 3 controls the power semiconductor switch (thyristor) 4 to be turned on and off, and the series reactor 5 is connected. The reactive power was controlled by the phase advancing capacitor 6. However, in this method, due to the delay in the detection response of the reactive power, the circuit voltage after the reactive power compensation as shown in FIG.
The circuit voltage caused by the opening delay of the first 0.5 cycles due to the closing delay of the load and the opening delay of the 0.5 cycles of the semiconductor switch after the completion of the energization of the load drops and rises unevenly, and a sufficient flicker improvement effect cannot be obtained.

ここで、第1図(b)の縦軸は回路電圧の変動ΔV、
横軸tは時間、Tは溶接機の通電時間である。
Here, the vertical axis of FIG. 1 (b) is the circuit voltage fluctuation ΔV,
The horizontal axis t is time, and T is the energization time of the welding machine.

また、上記従来方式の応答遅れを改善する方法として
第2図(a)に示す、抵抗溶接機1の運転信号に同期し
て電力用半導体スイッチ4を作動させるフリッカー補償
回路も提案されているが、この方式では、例えば被溶接
物の材質変化や溶接条件の変化などによって負荷容量が
変化した場合、フリッカー補償装置の無効電力が追従で
きず、第2図(b)のような負荷容量の変化によって無
効電力の適正な補正ができず、回路電圧が変動(電圧降
下)し、フリッカーの改善効果が低下してしまう欠点が
あった。
As a method for improving the response delay of the above conventional method, a flicker compensation circuit for operating the power semiconductor switch 4 in synchronization with the operation signal of the resistance welding machine 1 is also proposed, which is shown in FIG. In this method, when the load capacity changes due to, for example, a change in the material to be welded or a change in welding conditions, the reactive power of the flicker compensation device cannot follow, and the change in the load capacity as shown in FIG. As a result, the reactive power cannot be properly corrected, the circuit voltage fluctuates (voltage drop), and the effect of improving flicker deteriorates.

なお、上記従来例の第1図(b)および第2図(b)
は、回路電圧の変動△Vと時間tの関係を示し、この中
でTは溶接機の通電時間である。この溶接機の通電時間
は一般的に10〜15サイクル(Hz)で、第1図(b)では
通電初期の0.5サイクルでは電圧降下を、通電終了後の
0.5サイクルでは電圧上昇することを示す。これは溶接
機の負荷電流に対して、その通電初期と通電終了時に負
荷電流(無効電力)の検出が0.5サイクルそれぞれ遅れ
を生じるために、この0.5サイクルの間無効電力を補償
しきれないためである。即ち、検出の応答遅れである。
1 (b) and 2 (b) of the above conventional example.
Indicates the relationship between the fluctuation ΔV of the circuit voltage and the time t, in which T is the energization time of the welding machine. The energization time of this welding machine is generally 10 to 15 cycles (Hz). In Fig. 1 (b), the voltage drop occurs at 0.5 cycles at the beginning of energization, and after the end of energization.
It shows that the voltage increases in 0.5 cycle. This is because the detection of the load current (reactive power) is delayed by 0.5 cycles at the beginning and end of energization with respect to the load current of the welding machine, and reactive power cannot be completely compensated during these 0.5 cycles. is there. That is, it is the response delay of the detection.

以上のことから分かるように、検出回路の応答遅れが
生じると、間欠運転負荷の投入時と引外し時に0.5サイ
クル進相無効電力の供給と停止の遅れが生じる。この
際、上記投入時の0.5サイクルと、引外し時の0.5サイク
ルの部分で電力系統に電圧変動が発生し、同一系統に接
続された照明灯のちらつき現象(フリッカーという)が
出たり、また各種制御機器がその都度不安定になるなど
の電力系統の障害がでてフリッカー補償装置に要求する
性能を満足し得ない。
As can be seen from the above, if the response delay of the detection circuit occurs, there is a delay in the supply and stop of 0.5-cycle advanced reactive power when the intermittent operation load is turned on and tripped. At this time, voltage fluctuations occur in the power system between the 0.5 cycle at the time of turning on and the 0.5 cycle at the time of tripping, causing the flickering phenomenon (called flicker) of the lighting connected to the same system, and various The control system becomes unstable each time, and the power system fails to meet the performance required of the flicker compensator.

本発明が解決しようとする問題点は、上記説明の従来
のフリッカー補償装置の欠点である負荷電流の検出応答
遅れによって生じる電源投入時および引外し時に生じる
0.5サイクルの電圧変動によって生じるフリッカー現象
を解消するものである。
The problem to be solved by the present invention occurs at the time of power-on and tripping, which is caused by the delay in the detection response of the load current, which is a drawback of the conventional flicker compensation device described above.
This is to eliminate the flicker phenomenon caused by the voltage fluctuation of 0.5 cycle.

即ち、本発明は電力用半導体スイッチ、直列リアクト
ルおよび進相コンデンサを直列接続した回路を、負荷に
並列接続してなる交流回路のフリッカー補償装置におい
て、フリッカー発生の負荷電流または無効電力を応答遅
れを有して検出し、等価直流電圧を送出する検出回路
と、負荷の運転と同期したパルス信号を受けて、その信
号の立上りでトリガーする第1の単安定マルチバイブレ
ータと、その信号の立下りでトリガーする第2の単安定
マルチバイブレータによって、負荷の運転開始時の立上
りパルスと運転終了時の立下りパルスで、上記単安定マ
ルチバイブレータが上記負荷電流または無効電力の検出
回路の応答遅れ時間分のパルス信号を発生させ、その信
号によって半導体スイッチを介して運転開始時は等価電
圧を、また運転終了時は上記検出回路の出力電圧を反転
させた等価電圧を各々加算器に送出し、上記検出回路の
出力電圧を加減算処理し、上記負荷電流または無効電力
の検出応答遅れ分を補正することにより、応答遅れを生
じることなく電力用半導体スイッチを制御することを特
徴とするフリッカー補償装置であり、第3図はその実施
例の回路である。
That is, the present invention is a flicker compensating device for an AC circuit in which a circuit in which a power semiconductor switch, a series reactor, and a phase-advancing capacitor are connected in series is connected in parallel to a load. A detection circuit that has and detects and sends an equivalent DC voltage, a first monostable multivibrator that receives a pulse signal that is synchronized with the operation of the load, and triggers at the rising edge of that signal, and at the falling edge of that signal. By the triggering second monostable multivibrator, the monostable multivibrator generates the load current or the reactive power detection delay time by the rising pulse at the start of the load operation and the falling pulse at the end of the operation. A pulse signal is generated, and the signal is used to generate an equivalent voltage at the start of operation via the semiconductor switch and at the end of operation. An equivalent voltage obtained by inverting the output voltage of the detection circuit is sent to each adder, the output voltage of the detection circuit is subjected to addition / subtraction processing, and the response delay is detected by correcting the detection response delay of the load current or reactive power. A flicker compensating device is characterized in that it controls a semiconductor switch for electric power without causing a noise, and FIG. 3 is a circuit of its embodiment.

本回路によれば、回路の負荷電流または負荷の無効電
力の検出応答遅れを補正するために、負荷(溶接器)の
実際の運転信号に同期させた他の信号発生器を備え、こ
の信号発生器で得た制御信号出力を、負荷投入時に生じ
る0.5サイクルの負荷電流の検出遅れ信号出力の頭部に
加えてフリッカー補償回路の投入開始時間を0.5サイク
ル早める補正を行う。
According to this circuit, in order to correct the detection response delay of the load current of the circuit or the reactive power of the load, another signal generator synchronized with the actual operation signal of the load (welder) is provided, and this signal generation is performed. The control signal output obtained by the instrument is added to the head of the detection delay signal output of the load current of 0.5 cycle that occurs when the load is turned on, and the turn-on start time of the flicker compensation circuit is corrected by 0.5 cycle.

次に、負荷引外し時に生じる0.5サイクルの負荷電流
の検出遅れ分は、上記信号発生器の制御信号出力の極性
を反転して負荷電流検出信号出力の末尾の0.5サイクル
に加えて制御信号を減算処理し、フリッカー補償回路の
引外し時間を0.5サイクル早める補正を行うものであ
る。この操作によりフリッカー補償回路の投入,引外し
タイミングを負荷の運転特性に確実に同期させることが
でき、電力系統のフリッカーを防止することができる。
Next, for the 0.5-cycle load current detection delay that occurs when the load is tripped, reverse the polarity of the control signal output of the signal generator and subtract the control signal in addition to the last 0.5 cycles of the load current detection signal output. The correction is performed to accelerate the trip time of the flicker compensation circuit by 0.5 cycle. By this operation, the timing of turning on and off the flicker compensation circuit can be surely synchronized with the operating characteristics of the load, and flicker of the power system can be prevented.

以下、第3図〜第5図に示す本発明の実施例について
説明する。
The embodiments of the present invention shown in FIGS. 3 to 5 will be described below.

第3図は本発明の実施例のフリッカー補償装置の回路
説明図で、1は回路に接続された溶接機、7は溶接機の
運転と同期したパルス信号Sを発生させるトランジス
タ。パルス信号Sは次段のホトカプラ8に伝送され、ホ
トカプラ8の出力信号S1を得る。次段9a,9bは単安定マ
ルチバイブレータで、上記信号S1の立上り、立下りに同
期し、単安定マルチバイブレータ9aの出力信号S2および
単安定マルチバイブレータ9bの出力信号S3を得る。次に
10a,10bは半導体スイッチで、上記信号S2およびS3でON
となり、それぞれ直流電圧S4およびS5を出力する。
FIG. 3 is a circuit explanatory view of the flicker compensating apparatus of the embodiment of the present invention, 1 is a welding machine connected to the circuit, and 7 is a transistor for generating a pulse signal S synchronized with the operation of the welding machine. The pulse signal S is transmitted to the next photocoupler 8 to obtain the output signal S1 of the photocoupler 8. The next stage 9a, 9b is a monostable multivibrator, which obtains the output signal S2 of the monostable multivibrator 9a and the output signal S3 of the monostable multivibrator 9b in synchronization with the rising and falling of the signal S1. next
10a and 10b are semiconductor switches, which are turned on by the above signals S2 and S3
And output DC voltages S4 and S5, respectively.

ここで、溶接機の運転開始時では、半導体スイッチ10
aから出力した信号S4(+VQ0)が、後述する信号Q1の等
価直流電圧として加算器11に入力される。次に、溶接機
の運転終了時では、負荷電流検出回路13の等価直流電圧
を反転増幅器14で逆極性に反転し、上記半導体スイッチ
10bを作動させて該半導体スイッチ10bから上記信号Q1の
等価直流電圧S5(−VQ1)を得て逆極性電圧として加算
器11に入力する。
At the start of operation of the welding machine, the semiconductor switch 10
The signal S4 (+ VQ0) output from a is input to the adder 11 as an equivalent DC voltage of the signal Q1 described later. Next, at the end of the operation of the welding machine, the equivalent DC voltage of the load current detection circuit 13 is inverted to an opposite polarity by the inverting amplifier 14, and the semiconductor switch
The semiconductor switch 10b is operated to obtain the equivalent DC voltage S5 (-VQ1) of the signal Q1 from the semiconductor switch 10b and input it to the adder 11 as a reverse polarity voltage.

一方、変流器2で溶接機1の負荷電流(交流)を検出
し、負荷電流検出回路13で等価直流電圧信号Q1を得て加
算器11に入力する。
On the other hand, the current transformer 2 detects the load current (AC) of the welding machine 1, and the load current detection circuit 13 obtains the equivalent DC voltage signal Q1 and inputs it to the adder 11.

ここで、信号Q1は第4図に示すように溶接機1の実際
の運転特性に同期した信号S1に対して0.5サイクル遅延
しており、上記信号S4をQ1の頭部に加算して0.5サイク
ル検出遅れを補正した信号Q2を得て選択回路12に入力す
る。
Here, the signal Q1 is delayed by 0.5 cycle with respect to the signal S1 synchronized with the actual operating characteristics of the welding machine 1 as shown in FIG. 4, and the above signal S4 is added to the head of Q1 for 0.5 cycle. The signal Q2 with the detection delay corrected is obtained and input to the selection circuit 12.

選択回路12は、信号Q2の等価直流電圧値のレベルに応
じて、供給すべき適正無効電力値を選定して電力用半導
体スイッチ4a,4b,4cの何れかを組み合わせてONし、直列
リアクトル5a,5b,5cと進相コンデンサ6a,6b,6cで構成し
た進相無効電力を電路に供給する。
The selection circuit 12 selects an appropriate reactive power value to be supplied according to the level of the equivalent DC voltage value of the signal Q2, and turns on by combining any of the power semiconductor switches 4a, 4b, 4c, and the series reactor 5a. , 5b, 5c and phase-advancing capacitors 6a, 6b, 6c are supplied to the circuit.

次に、溶接機の負荷電流(または無効電力)の検出回
路13では、上記電流を0.5サイクル毎にサンプリングホ
ールドして0.5サイクル遅れの等価直流電圧Q1を出力す
る(詳細は後述)。
Next, in the load current (or reactive power) detection circuit 13 of the welding machine, the current is sampled and held every 0.5 cycle and an equivalent DC voltage Q1 delayed by 0.5 cycle is output (details will be described later).

また、溶接機の運転でトランジスタ7が作動し、ホト
カプラ8を作動させ、その出力信号S1はHとなる。この
信号S1の立上りエッジにより第1の単安定マルチバイブ
レータ9aをトリガーし、0.5サイクルの間Hとして半導
体スイッチ10aをONにして溶接機の等価無効電力の加算
用等価直流電圧+VQ0を得る。この+VQ0を信号S4として
加算器11に入力する。なお、+VQ0は、負荷の公称定格
容量よりあらかじめ算定した無効電力の値を基準として
電圧設定を行う。
Further, the transistor 7 is activated by the operation of the welding machine and the photocoupler 8 is activated, and the output signal S1 thereof becomes H. The rising edge of the signal S1 triggers the first monostable multivibrator 9a to set the semiconductor switch 10a to ON for 0.5 cycle to turn on the semiconductor switch 10a to obtain the equivalent DC voltage + VQ0 for adding the equivalent reactive power of the welding machine. This + VQ0 is input to the adder 11 as the signal S4. In addition, + VQ0 sets the voltage based on the value of the reactive power calculated in advance from the nominal rated capacity of the load.

次に、溶接機運転終了時の出力信号S1が立下るとき、
第2の単安定マルチバイブレータ9bをトリガーし、0.5
サイクルの間半導体スイッチ10bをONさせ、上記検出回
路出力信号Q1を反転増幅器14で−VQ1信号を得る。この
−VQ1信号をS5として加算器11に入力する。
Next, when the output signal S1 at the end of welding machine operation falls,
Trigger the second monostable multivibrator 9b to 0.5
During the cycle, the semiconductor switch 10b is turned on, and the detection circuit output signal Q1 is obtained by the inverting amplifier 14 as the -VQ1 signal. This −VQ1 signal is input to the adder 11 as S5.

以上の各信号関係は第4図に示す通りで、溶接機の運
転開始と終了の各0.5サイクルの負荷電流(無効電力)
の検出を、溶接機の運転信号Sから得た補正信号により
補正する。つまり、溶接機運転出力信号Sの最初の立上
りより0.5サイクルの間のみ検出回路13の出力信号Q1と
同等の+直流電圧(+VQ0)を加算し、溶接終了時より
0.5サイクルの間のみ検出回路13の等価直流電圧Q1の反
転電圧(−VQ1)をQ1に加算して検出の遅れを相殺し補
正する。つまり、検出回路13の出力信号Q1と、上記半導
体スイッチ10a、10bから出力される第4図の補正出力信
号S4、S5の0.5サイクルを加減処理すれば同図の出力信
号Q2が得られる。このようにして得られた信号Q2は溶接
機の運転負荷タイミングに合致し、応答遅れなしで電力
用半導体スイッチ4a、4b、4cの何れかをONする。そして
溶接機の負荷容量(無効電力)の値が変動した場合に
は、検出回路13の出力信号の値Q1が変化し、上記Q2の値
が変化して選択回路12によって上記半導体スイッチ4a、
4b、4cが適正に選択され、同図ΔVに示すように回路電
圧が一定の値に補償できる。
The above signal relationships are as shown in Fig. 4, and the load current (reactive power) of each 0.5 cycle of starting and ending the welding machine operation.
Is corrected by the correction signal obtained from the operation signal S of the welding machine. That is, the + DC voltage (+ VQ0) equivalent to the output signal Q1 of the detection circuit 13 is added only for 0.5 cycles from the first rise of the welding machine operation output signal S, and from the end of welding.
Only during 0.5 cycles, the inverted voltage (-VQ1) of the equivalent DC voltage Q1 of the detection circuit 13 is added to Q1 to cancel the detection delay and correct it. In other words, if the output signal Q1 of the detection circuit 13 and the 0.5 cycles of the correction output signals S4 and S5 of FIG. 4 output from the semiconductor switches 10a and 10b are subjected to adjustment processing, the output signal Q2 of FIG. 4 is obtained. The signal Q2 thus obtained matches the operation load timing of the welding machine, and turns on any of the power semiconductor switches 4a, 4b, 4c without a response delay. When the value of the load capacity (reactive power) of the welding machine fluctuates, the value Q1 of the output signal of the detection circuit 13 changes, the value of Q2 changes, and the selection circuit 12 causes the semiconductor switch 4a,
4b and 4c are properly selected, and the circuit voltage can be compensated to a constant value as shown by ΔV in the figure.

次に、上記検出回路13の検出出力信号のタイミング
が、実際の溶接機負荷電流より0.5サイクル遅延する理
由とその動作原理について説明する。
Next, the reason why the timing of the detection output signal of the detection circuit 13 is delayed by 0.5 cycle from the actual welding machine load current and its operating principle will be described.

検出回路13は、溶接機電流(または無効電力)を0.5
サイクル積分してその等価直流電圧Q1を出力する。
The detection circuit 13 has a welding machine current (or reactive power) of 0.5.
Cycle integration is performed and the equivalent DC voltage Q1 is output.

一般に電力Paの理論式は、 より、0.5サイクルを積分し、その直流分が電力値とな
ることを利用し、0.5サイクルの積分値をサンプリング
ホールドして既積分値を瞬時にリセットする。次に、さ
らに次の0.5サイクルを積分開始させてこれをくり返
し、常に0.5サイクル毎の検出値を出力させる。このた
めに検出信号は常に0.5サイクル溶接機電流より遅延し
て出力することになり、その動作関係は第5図に示す通
りである。
Generally, the theoretical formula of electric power Pa is Therefore, 0.5 cycles are integrated, and the fact that the DC component becomes the power value is used to sample and hold the integrated value for 0.5 cycles to instantly reset the already integrated value. Next, the integration of the next 0.5 cycles is started and this is repeated, and the detection value for every 0.5 cycle is always output. For this reason, the detection signal is always output with a delay of 0.5 cycle welder current, and its operation relationship is as shown in FIG.

以上のように本発明によれば、溶接機の運転信号によ
り投入、引外し時の0.5サイクル間、等価直流電圧を、
負荷電流または無効電力検出等価直流電圧出力に加減算
処理して検出の応答遅れを補正し、かつ、投入,引外し
時の0.5サイクル以外の間は検出値により適性進相無効
電力を制御するために、フリッカー改善効果が著しく向
上するなどの利点を有し、工業的ならびに実用的価値は
極めて大なるものである。
As described above, according to the present invention, the equivalent DC voltage is supplied by the operation signal of the welding machine, for 0.5 cycles at the time of tripping, the equivalent DC voltage,
In order to correct the response delay of detection by adding / subtracting to the load current or reactive power detection equivalent DC voltage output, and to control the proper advanced reactive power by the detected value during periods other than 0.5 cycle at the time of making and tripping. In addition, it has the advantage that the effect of improving flicker is remarkably improved, and its industrial and practical value is extremely great.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)は従来のフリッカー補償装置の回路説明
図、同図(b)は同従来のフリッカー補償装置の回路電
圧の変動ΔVを示す特性図、第2図(a)は従来の他の
フリッカー補償装置の回路説明図、同図(b)は同従来
のフリッカー補償装置の回路電圧の変動ΔVを示す特性
図、第3図は本発明のフリッカー補償装置の一実施例の
回路説明図、第4図は同本発明のフリッカー補償装置の
動作波形説明図、第5図は本発明のフリッカー補償装置
に係る検出回路の検出値と溶接機電流の動作波形説明図
である。 1……溶接機 2……交流器 3……制御回路 4……4a,4b,4c,電力用半導体スイッチ 5……5a,5b,5c直列リアクトル 6……6a,6b,6c進相コンデンサ 7……溶接機の運転検出用トランジスタ 8……ホトカプラ 9a……第1の単安定マルチバイブレータ 9b……第2の単安定マルチバイブレータ 10a,10b……半導体スイッチ 11……加算器 12……選択回路 13……検出回路 14……反転増幅器 t……時間 T……溶接機(負荷)の通電時間 ΔV……回路電圧の変動
1 (a) is a circuit explanatory diagram of a conventional flicker compensation device, FIG. 1 (b) is a characteristic diagram showing a circuit voltage fluctuation ΔV of the conventional flicker compensation device, and FIG. 2 (a) is another diagram. FIG. 3B is a circuit diagram of a flicker compensating device of the present invention, FIG. 3B is a characteristic diagram showing a circuit voltage variation ΔV of the conventional flicker compensating device, and FIG. FIG. 4 is an operation waveform explanatory diagram of the flicker compensation device of the present invention, and FIG. 5 is an operation waveform explanatory diagram of a detection value and a welding machine current of the detection circuit according to the flicker compensation device of the present invention. 1 …… Welding machine 2 …… AC device 3 …… Control circuit 4 …… 4a, 4b, 4c, power semiconductor switch 5 …… 5a, 5b, 5c Series reactor 6 …… 6a, 6b, 6c Phase advance capacitor 7 ...... Welding machine operation detection transistor 8 ...... Photo coupler 9a ...... First monostable multivibrator 9b …… Second monostable multivibrator 10a, 10b …… Semiconductor switch 11 …… Adder 12 …… Selection circuit 13 …… Detection circuit 14 …… Inverting amplifier t …… Time T …… Welding machine (load) energization time ΔV …… Circuit voltage fluctuation

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電力用半導体スイッチ、直列リアクトルお
よび進相コンデンサを直列接続した回路を、負荷に並列
接続してなる交流回路のフリッカー補償装置において、
フリッカー発生の負荷電流または無効電力を応答遅れを
有して検出し、等価直流電圧を送出する検出回路と、負
荷の運転と同期したパルス信号を受けて、その信号の立
上りでトリガーする第1の単安定マルチバイブレータ
と、その信号の立下りでトリガーする第2の単安定マル
チバイブレータによって、負荷の運転開始時の立上りパ
ルスと運転終了時の立下りパルスで、上記単安定マルチ
バイブレータが上記負荷電流または無効電力の検出回路
の応答遅れ時間分のパルス信号を発生させ、その信号に
よって半導体スイッチを介して運転開始時は等価電圧
を、また運転終了時は上記検出回路の出力電圧を反転さ
せた等価電圧を各々加算器に送出し、上記検出回路の出
力電圧と加減算処理し、上記負荷電流または無効電力の
検出応答遅れ分を補正することにより、応答遅れを生じ
ることなく電力用半導体スイッチを制御することを特徴
とするフリッカー補償装置。
1. A flicker compensating device for an AC circuit, comprising a power semiconductor switch, a series reactor and a phase-advancing capacitor connected in series to a load in parallel.
A detection circuit that detects a flicker-generated load current or reactive power with a response delay and sends an equivalent DC voltage, and a pulse signal that is synchronized with the operation of the load and that triggers at the rising edge of the signal. The monostable multivibrator and the second monostable multivibrator triggered by the falling edge of the signal cause the monostable multivibrator to generate the load current at the rising pulse at the start of operation of the load and the falling pulse at the end of operation. Alternatively, a pulse signal for the response delay time of the reactive power detection circuit is generated, and the signal is used to invert the equivalent voltage at the start of operation and the output voltage of the detection circuit at the end of operation via a semiconductor switch. Send the voltage to each adder and add / subtract with the output voltage of the detection circuit to correct the detection response delay of the load current or reactive power. The Rukoto, flicker compensating apparatus characterized by controlling the power semiconductor switch without causing a response delay.
JP18249383A 1983-09-29 1983-09-29 Flickering compensator Expired - Lifetime JP2527158B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18249383A JP2527158B2 (en) 1983-09-29 1983-09-29 Flickering compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18249383A JP2527158B2 (en) 1983-09-29 1983-09-29 Flickering compensator

Publications (2)

Publication Number Publication Date
JPS6074961A JPS6074961A (en) 1985-04-27
JP2527158B2 true JP2527158B2 (en) 1996-08-21

Family

ID=16119246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18249383A Expired - Lifetime JP2527158B2 (en) 1983-09-29 1983-09-29 Flickering compensator

Country Status (1)

Country Link
JP (1) JP2527158B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7206128B2 (en) 2003-06-03 2007-04-17 Olympus Corporation Illumination unit of stereomicroscope

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4676369B2 (en) * 2006-03-31 2011-04-27 ニチコン株式会社 Voltage fluctuation compensation device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7206128B2 (en) 2003-06-03 2007-04-17 Olympus Corporation Illumination unit of stereomicroscope

Also Published As

Publication number Publication date
JPS6074961A (en) 1985-04-27

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