JP2526754Y2 - Inverter drive circuit - Google Patents

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to an inverter drive circuit that automatically corrects a resonance condition caused by a load.

(Prior Art) The applicant of the present invention has previously applied for a device using the circuit shown in FIG. As shown in FIG. 5, one primary winding 4 from the positive electrode side of the DC power supply 1 through the primary winding center tap 3 of the transformer 2 and the first switching, as shown in FIG. A first closed circuit 6 extending to the negative electrode side of the DC power supply 1 through a MOS type FET 5 as an element, and the other primary winding from the positive electrode side of the DC power supply 1 via the primary winding center tap 3 of the transformer 2 Line 7, a second closed circuit 9 extending to the negative electrode side of the DC power supply 1 via the MOS type FET 8 as the second switching element, and one of the first and second FETs 5 and 8 as the first and second switching elements. Turn on, turn off the other,
And a switching control circuit 10 for controlling a duty ratio, wherein the first and second closed circuits
Insert the capacitor 11 in one of the circuits 6, 9
An inverter 13 and a delay circuit 14 are interposed between the IC 12 of the switching control circuit 10 and the first FET 5, and a delay circuit 15 is interposed between the IC 12 and the second FET 8 of the switching control circuit 10. . Then, the first FET 5 and the second FET 8
, Capacitors 16 and 17 are inserted in parallel.

The secondary winding 18 of the transformer 2 has an inductor 1
9, rectifier diode 20, commutation diode 21, inductor 2
2, output terminal via rectifying and smoothing circuit 24 consisting of capacitor 23
25,26. The output terminals 25 and 26 are connected to the first FET through a detection circuit 27 that detects and amplifies a load change.
5. It is coupled to a switching control circuit 10 for alternately turning on and off the second FET 8.

(Problem to be Solved by the Invention) In the circuit configured as described above, it is difficult to set an optimum dead time due to the lightness of the load on the secondary side, and a duty ratio for turning on / off the switching element. Abruptly changes the voltage of the capacitor due to the magnetism of the transformer, which may cause the switching element to be destroyed.

This problem will be described with reference to FIGS. 6 to 8 together with the operation of the circuit.

In FIG. 6, S is the output voltage of the IC 12 of the switching control circuit 10, S is the output voltage of the inverter 13, and S is the second FET.
8, the gate-source voltage of the first FET 5, S is the drain-source voltage of the second FET 8, S
Denotes the current of the second FET 8, S denotes the drain-source voltage of the first FET 5, S to S show the waveforms at light load, and FIGS. 7S to S show the waveforms of the outputs S to S at heavy load. The waveform is shown.

The output voltage S of the IC 12 of the switching control circuit 10 and the output voltage S via the inverter 13 are pulse voltages inverted from each other, as shown in FIGS. When turning on the first FET 5 and the second FET 8 as the first and second switching elements, as shown in FIGS.
In the dead times d1 and d2, which are simultaneously turned off at 4, 15 and the predetermined time d1 and d2, the circuit of the inductance 28 of the transformer 2 and the capacitors 16 and 17 resonate to perform zero-cross switching, thereby causing a switching loss. Has been reduced. In this case, the resonance energy stored in the inductance 28 fluctuates due to the load current on the secondary side. That is, at light load, as shown in FIGS.
The voltage and current applied to the first FET 5 and the second FET 8 rise slowly, while the voltage and current applied to the first FET 5 and the second FET 8 rapidly increase under heavy load, as shown in FIGS. Therefore, dead time d3, d4 under heavy load
Must be set to the maximum value corresponding to the dead times d1 and d2 when the load is light, which causes a problem that an extra dead time is added when the load is heavy.

Next, a case where the duty ratio for turning on and off the switching element changes rapidly will be described with reference to FIG.

8, S is the output voltage of the IC 12 of the switching control circuit 10, S is the gate-source voltage of the second FET 8,
Represents a gate-source voltage of the first FET 5, S represents a current of the second FET 8, and S represents a current of the first FET 5, respectively.

This inverter has two switching elements, 1F
The ET5 and the second FET 8 are turned on and off alternately, and a DC voltage is generated across the capacitor 11 so that the voltage-time product applied to the transformer is equal, so that the transformer is demagnetized. Not working. Here, when the on / off duty ratio changes abruptly, the voltage change of the capacitor 11 is delayed, and the transformer 2 is demagnetized, so that the current S of the second FET 8 gradually increases as shown by S and S. Also, the current S of the first FET 5 gradually increases with the rapid voltage correction of the capacitor 11, and the transformer 2 reaches a saturation state, and the first F5 as a switching element
There is a problem that the ET5 and the second FET 8 may be destroyed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for automatically correcting a difference in a resonance condition caused by a load and for preventing a transformer from being saturated by charging and discharging a capacitor.

[Structure of the Invention] (Means for Solving the Problems) To achieve the above object, the structure of the inverter drive circuit of the present invention is a power supply and one primary winding via a primary winding center tap of a transformer. And a first closed circuit comprising a first switching element, a second closed circuit comprising a power supply, the other primary winding via a primary winding center tap of a transformer, and a second switching element. A switching control circuit for turning on and off the first and second switching elements alternately and controlling a duty ratio;
In the inverter drive circuit comprising a capacitor inserted in one of the closed circuits, a delay circuit that is variable depending on the load of the load is inserted between the switching control circuit and the first and second switching elements. Things.

The delay circuit includes first and second auxiliary switching elements connected to a control terminal of the first switching element and a control terminal of the second switching element, respectively.
A first resistor and a diode inserted in parallel between the output terminal of the switching control circuit and the control terminal of the second switching element, an auxiliary winding provided in the transformer, A second resistor inserted between the control terminals of the second auxiliary switching element, a third resistor inserted between the auxiliary winding and the control terminal of the first switching element, and a third resistor And a first capacitor having one end connected between the control terminals of the first switching element and the other end grounded, a control terminal of the second switching element, and the first resistor and the diode. And a second capacitor grounded at one end and grounded at the other end.

(Operation) The operation of the inverter drive circuit of the present invention having the above configuration will be described.

When the load is light, the voltage and current applied to the first and second switching elements rise slowly, the current is small, and the energy stored in the inductance of the transformer is small. If the energy is small, the rise of the voltage generated in the auxiliary winding provided in the transformer becomes gentle, and this is applied to the gates of the first and second switching elements via the delay element. Therefore, the dead time also becomes longer. At a heavy load, the voltage and current applied to the first and second switching elements rise sharply, the current is large, and the energy stored in the inductance of the transformer is large. Then, the rise of the voltage generated in the auxiliary winding provided in the transformer becomes sharp, and is applied to the gates of the first and second switching elements via the delay element. Therefore, the dead time is also shortened.

The second switching element is turned on by the output voltage of the auxiliary winding provided in the transformer. At this time, the first switching element is not turned on by the auxiliary switching element, and the first and second switching elements are alternately turned on. By turning on and off the switching element, saturation of the transformer due to charging / discharging current of the voltage clamp capacitor can be prevented.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a transformer 2
Through the center tap 3 of the primary winding of
1, a first closed circuit 6 extending to the negative side of the DC power supply 1 via one primary winding 4 and the MOS type first FET 5, and a center of the primary winding of the transformer 2 from the positive side of the DC power supply 1 A second closed circuit 9 is formed via the tap 3, the other primary winding of the transformer 2, the MOS type second FET 8, and the negative side of the DC power supply 1.
The first FET 5 and the second FET 8 are respectively connected in parallel with a capacitor 1
6,17 have been inserted.

The secondary winding 18 of the transformer 2 includes an inductor 19,
Rectifier diode 20, commutation diode 21, inductor 22,
Output terminal via rectifying / smoothing circuit 24 consisting of capacitor 23
25,26. The output terminals 25 and 26 are coupled to a switching control circuit 10 including an IC 12 via a detection circuit 27 that detects and amplifies a load change.

In FIG. 1, a portion 29 surrounded by a chain line is a delay circuit portion related to the present invention, and a MOS-type third FET 34 and a MOS-type fourth FET 35 as first and second auxiliary switching elements.
Are connected to the gate of the first FET 5 and the gate of the second FET 8, respectively. Further, a resistor 33 and a diode 32 as a first resistor are inserted between the output terminal of the switching control circuit 10 and the gate of the second FET 8 in parallel with each other. Further, a resistor 30 as a second resistor is inserted between the auxiliary winding 36 provided in the transformer 2 and the gate of the MOS-type fourth FET 35. Further, a resistor 31 as a third resistor is provided.
Is inserted between the auxiliary winding 36 and the gate of the first FET 5.

Further, in the delay circuit portion 29, a capacitor 41 as a first capacitor forming an equivalent circuit to the capacitor connected between the gate and the source of the first FET 5, one end is connected between the resistor 31 and the gate of the first FET 5, The other end is grounded, and a capacitor 42 as a second capacitor forming an equivalent circuit to the capacitor connected between the gate and the source of the second FET 8 is provided between the gate of the second FET 8 and the resistor 33 and the diode 32. Is connected at one end and the other end is grounded.

In the delay circuit portion 29, the auxiliary winding 36 and the resistor 30 or the resistor 31 of the transformer 2 constitute a gate voltage supply circuit for supplying a voltage to each switching element.

Next, the operation of this circuit will be described with reference to FIGS.

2, S is the output voltage of the IC 12 constituting the switching control circuit 10, S is the voltage generated in the auxiliary winding 36 of the transformer 2, S is the gate-source voltage of the second FET 8, and S is the first voltage.
The gate-source voltage of FET5, S is the drain-source voltage of the second FET8, S is the current of the second FET8, S is the drain-source voltage of the first FET5, S is the drain-source voltage of the third FET34, and S is 4 shows the gate-source voltage of the fourth FET 35, S and S to S and S, S show waveforms at light load, and FIG. 3 S and S to S show heavy load of the outputs S and S to S. The waveform at the time is shown.

The output voltage S of the IC 12 of the control circuit 10 has a delayed waveform due to the resistance 33 and the capacitor 42 constituting the delay circuit, and becomes the gate-source voltage S of the second FET 8. The gate-source voltage S of the first FET 5 is supplied from a gate voltage supply circuit comprising an auxiliary winding 36 of the transformer 2 and a resistor 31, and a resistor 31 and a capacitor constituting a delay circuit are provided.
Due to 41, the waveform is delayed in rising. This first FET
The gate-source voltage S of 5 is such that the third FET 34 is off,
In addition, since the voltage is applied when the second FET 8 is turned off and the polarity of the transformer is inverted, the gate-source voltage S of the first FET 5
And the gate-source voltage S of the second FET 8 has a pulse waveform that turns on and off alternately.

Here, when the output terminals 25 and 26 are lightly loaded, FIG.
As shown in S to S, the currents of the first FET 5 and the second FET 8 are small, and the drain-source voltage S of the second FET 8 and the first FE
The drain-source voltage S of T5 rises slowly, and the resonance energy stored in the inductance 28 of the transformer 2 is small. Therefore, the rise of the voltage S generated in the auxiliary winding 36 becomes slow, and the rise of the gate-source voltage S of the first FET 5 also becomes slow slowly. In addition, since the fall of the gate-source voltage S of the fourth FET 35 becomes gentle and the turn-off becomes slow slowly,
The rise of the gate-source voltage S of the second FET 8 also becomes slow. Thus, the dead times d1 and d2 become longer.

Next, when the output terminals 25 and 26 are under heavy load, as shown in FIGS. 3S to 3S, the current of the first FET 5 and the second FET 8 is large, and the drain-source voltage S and the first FE of the second FET 8 are increased.
The rise of the drain-source voltage S of T5 is sharp, and the resonance energy stored in the inductance 28 of the transformer 2 is large. Therefore, the rise of the voltage S generated in the auxiliary winding 36 also becomes sharp, and the rise of the gate-source voltage S of the first FET 5 also becomes sharp. 4th floor
The fall of the gate-source voltage S of the ET 35 also becomes sharp, and the turn-off also becomes sharp, so that the rise of the gate-source voltage S of the second FET 8 also becomes fast. In this way, the dead times d3 and d4 are shortened.

As described above, according to the lightness of the load, the control operation of the first switching element and the first auxiliary switching element is performed at a light load, and the control of the second switching element and the second auxiliary switching element is performed at a heavy load. By operation,
Dead time has been corrected.

Next, an operation in the case where the duty ratio of the pulse voltage waveform of the output voltage S of the IC 12 of the switching control circuit 10 sharply increases will be described with reference to FIG.

4, S is the output voltage of the IC 12 of the switching control circuit 10, S is the voltage generated in the auxiliary winding 36 of the transformer 2, S
Is the gate-source voltage of the second FET 8, S is the gate-source voltage of the first FET 5, S is the current of the second FET 8, and S is the first FET 5
Respectively.

Here, when the duty ratio of on and off changes abruptly, that is, when the on-time of the second FET 8 becomes longer and the voltage-time product applied to the transformer increases, and the second FET 8 turns off, the flyback of the transformer 2 The back voltage is clamped by a closed circuit 6 including the transformer primary winding 4, the capacitor 11, and the first FET 5. However, as the on-time of the second FET 8 increases, the off-time decreases and the discharge time to the capacitor 11 increases. At this time, a voltage having a polarity for turning on the fourth FET 35 as the second auxiliary switching element is generated in the auxiliary winding 36, and the fourth FET 35 is turned on, and the second FET 8 is turned on.
Is in the same state as when the OFF signal is input. Therefore, even if an ON signal is output from the IC 12 of the switching control circuit, the voltage S between the gate and the source of the second FET 8 is not applied until the discharge to the capacitor 11 by the flyback voltage of the transformer 2 is completed. Can be prevented.

[Effects of the Invention] According to the configuration of the present invention described in detail above, even if the load condition changes, the dead time is adjusted to the load condition and the optimum resonance condition can be maintained. ,on,
Even when the off duty ratio changes abruptly, it is possible to prevent a sudden charge / discharge current of the voltage clamp capacitor and prevent the switching element from being destroyed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an inverter drive circuit according to the present invention, FIGS. 2 to 4 are operation waveform diagrams of FIG.
FIG. 5 is a circuit diagram of the inverter drive circuit of the applicant, and FIGS. 6 to 8 are operation waveform diagrams of FIG. 1 DC power supply 2 Transformer 3 Primary winding center tap 4, 7 Primary winding 5 First FET 8
Second FET, 10: Switching control circuit, 11: Capacitor, 18: Secondary winding, 30, 31, 33: Resistor, 32: Diode, 34: Third FET, 35: Fourth FET, 36 .... Reinforcing winding.

Claims (2)

(57) [Scope of request for utility model registration] A first closed circuit comprising a power supply, one primary winding via a primary winding center tap of a transformer, and a first switching element; a power supply and a primary winding center tap of a transformer. A second closed circuit including the other primary winding via a second switching element and a second switching element;
An inverter drive circuit comprising a switching control circuit for turning on and off the switching elements alternately and controlling a duty ratio, and a capacitor inserted in one of the first and second closed circuits. An inverter drive circuit, wherein a delay circuit that varies depending on the load is inserted between a control circuit and the first and second switching elements. 2. The switching circuit according to claim 1, wherein the delay circuit includes first and second auxiliary switching elements connected to a control terminal of the first switching element and a control terminal of the second switching element, respectively. A first resistor and a diode inserted in parallel between the output terminal and the control terminal of the second switching element; an auxiliary winding provided in the transformer; an auxiliary winding and the second auxiliary switching A second resistor inserted between the control terminals of the element, a third resistor inserted between the auxiliary winding and the control terminal of the first switching element, a third resistor and the first resistor, A first capacitor having one end connected between control terminals of the switching element and the other end grounded; a control terminal of the second switching element; a first resistor and a diode; It is connected to one end between the de inverter circuit of claim 1, wherein a second capacitor whose other end is grounded, in that it consists of.