JPH08205533A - Rectifier circuit - Google Patents

Rectifier circuit

Info

Publication number
JPH08205533A
JPH08205533A JP3004295A JP3004295A JPH08205533A JP H08205533 A JPH08205533 A JP H08205533A JP 3004295 A JP3004295 A JP 3004295A JP 3004295 A JP3004295 A JP 3004295A JP H08205533 A JPH08205533 A JP H08205533A
Authority
JP
Japan
Prior art keywords
gate
voltage
free wheel
rectifier circuit
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3004295A
Other languages
Japanese (ja)
Inventor
Hiroyuki Suzuki
裕之 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP3004295A priority Critical patent/JPH08205533A/en
Publication of JPH08205533A publication Critical patent/JPH08205533A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To provide a rectifier circuit of a low loss by performing synchronous rectification by using a field-effect transistor for the free wheel element of a switching power supply. CONSTITUTION: The high level of the output voltage (j) of a second comparator 11 is applied to one input of an AND gate, and when the output voltage (i) of a first comparator 10 is changed from a low level to a high level, the output of an AND gate 13 becomes a high level. The output of the AND gate 13 is fed back to the input of an OR gate 12, and when the output voltage (j) of the second comparator 11 becomes a low level, the output level of the AND gate 13 becomes low. Therefore, the drive voltage of a free wheel element 6 can supply a constant gate-to-source voltage even when the reset period of a transformer 4 comes to an end and the voltage of a secondary winding becomes 0V, so that the effect of the low loss of a synchronous rectifier circuit may be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する分野】本発明はスイッチング電源に係わ
り、特に整流素子としてスイッチング素子を用いて同期
整流を行う整流回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply, and more particularly to a rectifier circuit that uses a switching element as a rectifier element to perform synchronous rectification.

【0002】[0002]

【従来の技術】図1は一般に知られた同期整流回路を用
いたスイッチング電源の回路構成図であり、その動作波
形を図2に示す。図1に於いて、1は直流電源、2は主
スイッチング素子駆動回路、3は主スイッチング素子、
4はトランス、5は整流用素子、例えば電界効果トラン
ジスタ、6はフリ−ホイ−ル用素子、例えば電界効果ト
ランジスタ、7は平滑用チョ−ク、8は平滑用コンデン
サ、9は負荷である。図2において、aはフリ−ホイ−
ル用素子6のゲ−ト・ソ−ス電圧、bはフリ−ホイ−ル
用素子6のドレイン・ソ−ス電流、cはトランス4の2
次巻線電圧、d (2) ・eはフリ−ホイ−ル用素子6の駆動信号のタイミング
が遅れた時の整流用素子5のドレイン・ソ−ス電流とフ
リ−ホイ−ル用素子6のドレイン・ソ−ス電流である。
2. Description of the Related Art FIG. 1 is a circuit configuration diagram of a switching power supply using a generally known synchronous rectification circuit, and its operation waveform is shown in FIG. In FIG. 1, 1 is a DC power supply, 2 is a main switching element drive circuit, 3 is a main switching element,
Reference numeral 4 is a transformer, 5 is a rectifying element such as a field effect transistor, 6 is a free wheel element such as a field effect transistor, 7 is a smoothing choke, 8 is a smoothing capacitor, and 9 is a load. In FIG. 2, a is a free wheel.
Gate source voltage of the device 6 for the routing, b is the drain source current of the device 6 for the freewheeling, and c is 2 of the transformer 4.
Next winding voltage, d (2) -e is the drain source current of the rectifying element 5 when the timing of the drive signal of the free wheel element 6 is delayed and the free wheel element 6 Drain source current.

【0003】図1の回路動作を簡単に説明する。スイッ
チング電源は直流電源1からの入力電圧を主スイッチン
グ素子駆動回路2で制御される主スイッチング素子3を
導通しトランス4をかいして整流用素子5により整流
し、平滑用チョ−ク7、平滑用コンデンサ8により平滑
し、所望の電力を負荷9へ供給する。また、主スイッチ
ング素子3が導通していない時は、平滑用チョ−ク7に
蓄えられたエネルギ−をフリ−ホイ−ル用素子6により
整流し、平滑用コンデンサ8により平滑し、所望の電力
を負荷9へ供給する。
The circuit operation of FIG. 1 will be briefly described. The switching power supply rectifies the input voltage from the DC power supply 1 through the main switching element 3 controlled by the main switching element drive circuit 2 through the transformer 4 and rectifies it by the rectifying element 5, smoothing choke 7 and smoothing. It smoothes by the capacitor 8 for supply, and supplies desired electric power to the load 9. When the main switching element 3 is not conducting, the energy stored in the smoothing choke 7 is rectified by the free wheel element 6 and smoothed by the smoothing capacitor 8 to obtain a desired power. Is supplied to the load 9.

【0004】[0004]

【発明の目的】図1の回路に於いて、整流用素子5、フ
リ−ホイ−ル素子6にダイオ−ドを使用するとオン電圧
が高いので、低損失化を図るために図1に示すように電
界効果トランジスタのようなスイッチング素子を使用す
る事が一般的である。フリ−ホイ−ル用素子6の駆動方
法であるが、一般的にトランス4の2次巻線電圧cを使
用している。しかしながら、図1の回路に於いて、トラ
ンス4のリセット期間が終了し、2次巻線電圧cが0V
となると、フリ−ホイ−ル用素子6のゲ−ト・ソ−ス電
圧は図2のaの如く0Vとなる。すなわち、2次巻線電
圧cが0Vとなるとフリ−ホイ−ル用素子6が非導通と
なり、電界効果トランジスタであるフリ−ホイ−ル用素
子6の寄生ダイオ−ドが導通する。すなわち、2次巻線
電圧cが0Vになった以降、順方向電圧の小さい電界効
果トランジスタが非導通となるため、同期整流回路によ
る低損失化の効果が薄れる。
The use of a diode for the rectifying element 5 and the freewheeling element 6 in the circuit of FIG. 1 results in a high on-voltage, so that the loss is reduced as shown in FIG. It is common to use a switching element such as a field effect transistor. Regarding the driving method of the free wheel element 6, generally, the secondary winding voltage c of the transformer 4 is used. However, in the circuit of FIG. 1, the reset period of the transformer 4 ends and the secondary winding voltage c becomes 0V.
Then, the gate-source voltage of the free wheel element 6 becomes 0V as shown in FIG. That is, when the secondary winding voltage c becomes 0 V, the free wheel element 6 becomes non-conductive, and the parasitic diode of the free wheel element 6 which is a field effect transistor becomes conductive. That is, after the secondary winding voltage c becomes 0 V, the field effect transistor having a small forward voltage becomes non-conductive, so that the effect of lowering the loss by the synchronous rectification circuit is diminished.

【0005】本発明は、上記問題点を解決するために創
案されたものであり、スイッチング電源において電界効
果トランジスタのようなスイッチング素子を使用し、ト
ランス4の2次巻線電圧cが0Vとなってもフリ−ホイ
−ル用素子6が非導通となり (3) 寄生ダイオ−ドが導通することがなく、同期整流を行な
う事により低損失な整流回路を提供する事を目的とす
る。また、フリ−ホイ−ル用素子6の駆動信号を第1の
スイッチング素子3の駆動信号のもととなるコンデンサ
と抵抗による充放電の三角波と第1のスイッチング素子
3の駆動信号のタイミングにより形成していることによ
り、フリ−ホイ−ル用素子6の駆動信号のタイミングを
任意に選ぶ事ができ、フリ−ホイ−ル用素子6の駆動信
号のタイミングの遅れによる、図2のd・eに示す短絡
電流をなくす事ができ、同期整流を行なう場合に最も低
損失な整流回路を提供する事を目的とする。
The present invention was devised to solve the above-mentioned problems, and uses a switching element such as a field effect transistor in a switching power supply, and the secondary winding voltage c of the transformer 4 becomes 0V. Even if the free wheel element 6 becomes non-conductive (3), the parasitic diode does not become conductive, and it is an object of the present invention to provide a low loss rectifier circuit by performing synchronous rectification. Further, the drive signal of the free wheel element 6 is formed by the timing of the triangular wave of charging / discharging by the capacitor and the resistor which is the source of the drive signal of the first switching element 3 and the drive signal of the first switching element 3. By doing so, the timing of the drive signal of the free wheel element 6 can be arbitrarily selected, and due to the delay of the timing of the drive signal of the free wheel element 6, d.e in FIG. It is an object of the present invention to eliminate the short-circuit current shown in (1) and to provide the lowest loss rectifier circuit when performing synchronous rectification.

【0006】[0006]

【発明の構成】上記の目的を達成する為の本発明におけ
る同期整流回路を図4またスイッチング電源のフリ−ホ
イ−ル用素子6の駆動回路の構成図を図3に示す。10
は第1の比較器、11は第2の比較器、12はORゲ−
ト、13はANDゲ−トである。図5に於いてfは第1
のスイッチング素子3の駆動信号のもととなるコンデン
サと抵抗による充放電の三角波、gは出力制御アンプ信
号、hは可変電圧、iは第1の比較器10の出力電圧、
jは第2の比較器11の出力電圧、kはORゲ−ト12
の出力電圧、1はANDゲ−ト13の出力電圧であり、
フリ−ホイ−ル用素子6のゲ−ト・ソ−ス電圧となる。
FIG. 4 shows a synchronous rectification circuit according to the present invention for achieving the above object, and FIG. 3 shows a configuration diagram of a drive circuit for a free wheel element 6 of a switching power supply. 10
Is a first comparator, 11 is a second comparator, and 12 is an OR gate.
And 13 are AND gates. In FIG. 5, f is the first
, A triangular wave of charging and discharging by a capacitor and a resistance that is a source of a driving signal of the switching element 3, g is an output control amplifier signal, h is a variable voltage, i is an output voltage of the first comparator 10,
j is the output voltage of the second comparator 11, k is the OR gate 12
Output voltage, 1 is the output voltage of the AND gate 13,
The gate-source voltage of the free wheel element 6 is obtained.

【0007】[0007]

【発明の作用】本発明はスイッチング電源のフリ−ホイ
−ル用素子6に電界効果トランジスタを用いて、同期整
流を行なう事により低損失な整流回路を提供し、フリ−
ホイ−ル用素子6の駆動信号を任意に選ぶ事により図2
のd・eに示す短絡電流をなくす事ができるようにする
ものである。
The present invention provides a low-loss rectifier circuit by performing synchronous rectification by using a field effect transistor for the free wheel element 6 of the switching power supply.
By selecting the drive signal of the wheel element 6 arbitrarily, as shown in FIG.
This makes it possible to eliminate the short-circuit current indicated by d.e.

【0008】[0008]

【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。図3の第1の比較器 (4) 10のプラス入力には図5の出力制御アンプ信号g、マ
イナス入力には三角波fがはいり第1の比較器10の出
力電圧はiとなる、iのハイレベルになる所でフリ−ホ
イ−ル用素子6のゲ−ト・ソ−ス電圧1のハイレベルに
なる所が決定する。
Embodiments of the present invention will now be described in detail with reference to the drawings. The output voltage of the output control amplifier signal g of FIG. 5 is input to the positive input of the first comparator (4) 10 of FIG. 3, and the triangular wave f is input to the negative input thereof, and the output voltage of the first comparator 10 becomes i. The place where the gate source voltage 1 of the free wheel element 6 becomes high level is determined at the place where it becomes high level.

【0009】第2の比較器11のプラス入力には図5の
可変電圧h、マイナス入力には三角波fがはいり第2の
比較器11の出力電圧はjとなる、jのロウレベルにな
る所でフリ−ホイ−ル用素子6のゲ−ト・ソ−ス電圧1
のロウレベルになる所が決定する。ORゲ−ト12の入
力には第1の比較器10の出力iが入り、iがハイレベ
ルの時にORゲ−ト12の出力はハイレベルとなる。
The variable voltage h of FIG. 5 is input to the positive input of the second comparator 11, and the triangular wave f is input to the negative input thereof, and the output voltage of the second comparator 11 is j. Gate-source voltage 1 of element 6 for freewheel
Where the low level of is decided. The output i of the first comparator 10 is input to the input of the OR gate 12, and the output of the OR gate 12 becomes high level when i is high level.

【0010】この信号がANDゲ−ト13の入力に入
る。この時ANDゲ−トの一方の入力には第2の比較器
11の出力電圧jのハイレベルが入っており第1の比較
器10の出力電圧iがロ−からハイとなったときにAN
Dゲ−ト13の出力はハイレベルとなる。ANDゲ−ト
の出力はORゲ−ト12の入力にフィ−ドバックされて
おりANDゲ−ト13の出力レベルがロウになるのは第
2の比較器11の出力電圧jがロウレベルになったとき
となる。以上によりANDゲ−ト出力であるフリ−ホイ
−ル用素子6の駆動信号を作ることが出来る。
This signal enters the input of the AND gate 13. At this time, one input of the AND gate contains the high level of the output voltage j of the second comparator 11, and when the output voltage i of the first comparator 10 changes from low to high, AN
The output of the D gate 13 becomes high level. The output of the AND gate is fed back to the input of the OR gate 12, and the output level of the AND gate 13 becomes low because the output voltage j of the second comparator 11 becomes low level. It will be time. As described above, a drive signal for the free wheel element 6 which is an AND gate output can be produced.

【0011】[0011]

【発明の効果】図5の1に示すようにフリ−ホイ−ル用
素子6の駆動電圧はトランス4のリセット期間が終了
し、2次巻線電圧cが0Vとなっても一定のゲ−ト・ソ
−ス電圧を供給することができる。よって同期整流回路
による低損失化の効果がえられる。
As shown in 1 of FIG. 5, the drive voltage of the free wheel element 6 is constant even if the secondary winding voltage c becomes 0V after the reset period of the transformer 4 is completed. A source voltage can be supplied. Therefore, the effect of lowering the loss by the synchronous rectification circuit can be obtained.

【0012】また第2の比較器11のプラス入力の可変
電圧hにより第2の比較器11の出力電圧jのタイミン
グを任意に選定できるためフリ−ホイ−ル用素子6の駆
動信号のタイミングを任意に選ぶ事ができ、フリ−ホイ
−ル用素子6の駆動信号のタイミングの遅れによる、図
2のd・eに示す短絡電流をなくす事ができ、同期整流
を行なう場合に最も低損失な整流回路を提供する事がで
きる。 (5)
Further, since the timing of the output voltage j of the second comparator 11 can be arbitrarily selected by the variable voltage h of the positive input of the second comparator 11, the timing of the drive signal of the free wheel element 6 can be set. It can be arbitrarily selected, the short-circuit current shown in d and e of FIG. 2 due to the delay of the timing of the drive signal of the free wheel element 6 can be eliminated, and the lowest loss occurs in the case of performing synchronous rectification. A rectifier circuit can be provided. (5)

【図面の簡単な説明】[Brief description of drawings]

【図1】スイッチング電源における従来の同期整流回路FIG. 1 is a conventional synchronous rectification circuit in a switching power supply.

【図2】従来の同期整流回路における各部動作波形FIG. 2 is an operation waveform of each part in a conventional synchronous rectification circuit

【図3】本発明におけるフリ−ホイ−ル用素子駆動回路FIG. 3 is an element drive circuit for a free wheel according to the present invention.

【図4】本発明における同期整流回路FIG. 4 is a synchronous rectification circuit according to the present invention.

【図5】本発明における各部動作波形FIG. 5 is an operation waveform of each part in the present invention.

【符号の説明】[Explanation of symbols]

1 直流電源 2 主スイッチング素子駆動回路 3 主スイッチング素子 4 トランス 5 整流用素子 6 フリ−ホイ−ル用素子 7 平滑用チョ−ク 8 平滑用コンデンサ 9 負荷 10 第1の比較器 11 第2の比較器 12 ORゲ−ト 13 ANDゲ−ト 14 フリ−ホイ−ル用素子駆動回路 a フリ−ホイ−ル用素子6のゲ−ト・ソ−ス電圧 b フリ−ホイ−ル用素子6のドレイン・ソ−ス電流 (6) c トランス4の2次巻線電圧 d フリ−ホイ−ル用素子6の駆動タイミングが遅れ
た時の整流用素子5のドレイン・ソ−ス電流 e フリ−ホイ−ル用素子6の駆動のタイミングが遅
れた時のフリ−ホイ−ル用素子6のドレイン・ソ−ス電
流 f 第1のスイッチング素子3の駆動信号のもととな
るコンデンサと抵抗による充放電の三角波 g 出力制御アンプ信号 h 可変電圧 i 第1の比較器10の出力電圧 j 第2の比較器11の出力電圧 k ORゲ−ト12の出力電圧 l ANDゲ−ト13の出力電圧であり、フリ−ホイ
−ル用素子6のゲ−ト・ソ−ス電圧 m 整流用素子5のゲ−ト・ソ−ス間電圧
1 DC power supply 2 Main switching element drive circuit 3 Main switching element 4 Transformer 5 Rectifier element 6 Freewheel element 7 Smoothing choke 8 Smoothing capacitor 9 Load 10 First comparator 11 Second comparison 12 OR gate 13 AND gate 14 Free wheel element driving circuit a Gate-source voltage of free wheel element 6 b Free drain element 6 drain Source current (6) c Secondary winding voltage of transformer d d Drain source current of rectifying element 5 when drive timing of free wheel element 6 is delayed e Free wheel Drain-source current of the freewheeling element 6 when the drive timing of the switching element 6 is delayed. F The charge and discharge by the capacitor and the resistor which are the source of the drive signal of the first switching element 3 are performed. Triangle wave g Output control Signal h variable voltage i output voltage of first comparator 10 j output voltage of second comparator 11 output voltage of OR gate 12 output voltage of AND gate 13 and free-wheel Gate-source voltage of the element 6 for gate m Voltage between the gate and source of the rectifying element 5

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 直流電圧源と第1のスイッチング素子の
直列回路をトランスの1次巻線に接続し、トランス2次
巻線と負荷の間に整流用素子とフリ−ホイ−ル用素子か
ら成る整流回路を持つフォワ−ドコンバ−タにおいて、
前記、フリ−ホイ−ル用素子がスイッチング素子である
電界効果トランジスタであることを特徴とする整流回
路。
1. A series circuit of a DC voltage source and a first switching element is connected to a primary winding of a transformer, and a rectifying element and a freewheel element are provided between a secondary winding of a transformer and a load. In a forward converter with a rectifying circuit consisting of
A rectifier circuit characterized in that the free wheel element is a field effect transistor which is a switching element.
【請求項2】 特許請求の範囲第1項に記載の整流回路
に於いて、第1のスイッチング素子の駆動信号をコンデ
ンサと抵抗による充放電の三角波と出力制御アンプ信号
との比較により形成していることを特徴とする整流回
路。
2. The rectifying circuit according to claim 1, wherein the drive signal of the first switching element is formed by comparing a triangular wave of charging / discharging by a capacitor and a resistor with an output control amplifier signal. Rectifier circuit characterized by
【請求項3】 特許請求の範囲第1項に記載の整流回路
にとらわれず整流回路としてフリ−ホイ−ル用素子を有
する事を特徴とする整流回路。
3. A rectifier circuit characterized by having a freewheeling element as a rectifier circuit regardless of the rectifier circuit according to claim 1.
JP3004295A 1995-01-26 1995-01-26 Rectifier circuit Pending JPH08205533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3004295A JPH08205533A (en) 1995-01-26 1995-01-26 Rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3004295A JPH08205533A (en) 1995-01-26 1995-01-26 Rectifier circuit

Publications (1)

Publication Number Publication Date
JPH08205533A true JPH08205533A (en) 1996-08-09

Family

ID=12292774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3004295A Pending JPH08205533A (en) 1995-01-26 1995-01-26 Rectifier circuit

Country Status (1)

Country Link
JP (1) JPH08205533A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980067235A (en) * 1997-01-31 1998-10-15 김광호 Surge voltage generation prevention circuit
WO2010062700A3 (en) * 2008-10-30 2010-08-19 Meredith Cameron B Active rectifier
US9143042B2 (en) 1997-01-24 2015-09-22 Synqor, Inc. High efficiency power converter
US10199950B1 (en) 2013-07-02 2019-02-05 Vlt, Inc. Power distribution architecture with series-connected bus converter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9143042B2 (en) 1997-01-24 2015-09-22 Synqor, Inc. High efficiency power converter
KR19980067235A (en) * 1997-01-31 1998-10-15 김광호 Surge voltage generation prevention circuit
WO2010062700A3 (en) * 2008-10-30 2010-08-19 Meredith Cameron B Active rectifier
US10199950B1 (en) 2013-07-02 2019-02-05 Vlt, Inc. Power distribution architecture with series-connected bus converter
US10594223B1 (en) 2013-07-02 2020-03-17 Vlt, Inc. Power distribution architecture with series-connected bus converter
US11075583B1 (en) 2013-07-02 2021-07-27 Vicor Corporation Power distribution architecture with series-connected bus converter
US11705820B2 (en) 2013-07-02 2023-07-18 Vicor Corporation Power distribution architecture with series-connected bus converter

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