JP2526566B2 - Memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a memory device having a high degree of integration and good data retention characteristics.

[Outline of Invention]

In the memory device of the present invention, by making the gate insulating film of the transistor forming the flip-flop circuit thinner than the gate insulating film of the switching transistor, it is possible to obtain high integration and good data retention characteristics. It is a thing.

[Conventional technology]

FIG. 4 shows a conventional SRAM cell pattern. It should be noted that, in the reference numerals of FIGS. 1 to 4 of the drawings, the same reference numerals are used for the portions common to the conventional example and the embodiment.

A memory device including a flip-flop circuit and a switching transistor includes, for example, a static MOS RA.
There are M (SRAM) and the like. As shown in the SRAM circuit diagram of FIG. 3, these are two driver transistors T ₁ and T _{2 for} holding data, and two access transistors T for reading and writing data in the memory cells. _{It is} composed of ₃ , T ₄ and two load resistors R ₁ , R ₂ .

The conventional SRAM cell pattern is as shown in FIG.
Assuming that the channel width of the transistor is W and the channel length is L (the active region in the figure is sand, the first polysilicon portion is a thick frame, the area of the gate insulating film is hatched, W is the width of the active region, L corresponds to the width of the first polysilicon.) Conventionally, access transistor
The current driving capability ratio of the transistors is obtained by making L of T ₃ and T ₄ and L of the driver transistors T ₁ and T ₂ substantially the same and changing W, that is, the area ratio. For example, normally, the W of the driver transistors T ₁ and T _{2 is set to} the W of the access transistors T ₃ and T ₄ .
More than 2.5 times larger than the transistor area ratio of 2.5
It is being done more than twice.

This is because by taking the area ratio of the gate insulating film of the transistor, the current drivability of the driver transistor holding the data is not made larger than the current drivability of the access transistors T ₃ and T ₄ for reading and writing data. When the memory cell is activated by the word line, the driver transistor may be affected by the potential of the bit line for inputting / outputting information of the memory cell, and the held data may be inverted.

The current drive capability of a transistor can be expressed by the following channel conductance (g), where W is the width of the active region of the transistor, L is the width of the polysilicon of the transistor, μ is the mobility of electrons, and Cox is the gate oxide film. The capacitance of (insulating film), V _G is the voltage applied to the gate, and V _TH is the threshold voltage at which the transistor turns on.

From this equation, conventionally, by increasing the area of the gate insulating film, the channel width W of the transistor is increased,
It can be seen that the current drive capability ratio of the transistor is taken.

[Problems to be solved by the invention]

As described above, the conventional memory device has access transistors T ₃ , T ₄ in order to prevent inversion of the data held in the memory cells.
Than the channel width W of the driver transistors T ₁ and T ₂ is 2.5
It was necessary to take more than twice the current drive capacity ratio. Therefore, there is a problem that the cell area of the memory becomes large and the degree of integration is lowered.

The present invention was created in view of the above problems, and an object of the present invention is to provide a memory device having a high degree of integration and good data retention characteristics.

[Means for solving problems]

In order to solve the above problems, the memory device of the present invention is
In a memory device in which the memory cell is composed of at least a flip-flop circuit and a switching transistor,
The gate insulating film of the transistor forming the flip-flop circuit is thinner than the gate insulating film of the switching transistor.

Configuration of the present invention as viewed in FIGS. 1 and 2, the gate insulating film 2a of the transistors T _1, T ₂ constituting the flip-flop circuit, 2b the switching transistor T _3, T ₄ of the gate insulating film 3a, 3b Is thinner than.

Conventionally, the current driving capability ratio (2.5 times or more) is obtained by the area ratio of the gate electrode of the transistor, but the capacitance (Cox) can also be obtained by the means for reducing the film thickness of the gate insulating film as in the configuration of the present invention. It has been found that the current drive capacity can be increased because of a large value and a desired current drive capacity ratio can be obtained.

In other words, even if the area of the gate insulating film of the transistors T ₁ and T ₂ which is conventionally wide is reduced to the same area as the switching transistors T ₃ and T ₄ , the film thickness of the gate insulating films 2a, 2b and 3a, 3b is reduced. By setting the ratio to 2: 5 (2.5 times), a desired current drivability ratio can be obtained, and good data retention characteristics can be maintained.

[Action]

Memory device of the present invention, the gate insulating film 2a of the transistors T _1, T ₂ constituting the flip-flop circuit, the gate insulating film 3a of 2b the switching transistor T _3, T _4, by thinning than 3b, transistor Since the current driving capability is improved and the data retention characteristic is improved, the cell area of the transistor can be reduced and the degree of integration can be increased.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. Of course, the following embodiment is an example, and the present invention is not limited to this example.

In this embodiment, a static MOS RAM (SRAM) is used.

1 is a memory cell pattern of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA 'of FIG. 1, and FIG. 3 is a circuit diagram of SRAM.

In this embodiment, as shown in the circuit diagram of FIG. 3, a flip-flop circuit which is a memory circuit of the memory cell 1 is formed.
Transistors (here, driver transistors are used) T ₁ and T ₂ , switching transistors (here access transistors are used) T ₃ and T ₄ , and load resistors R ₁ and R The circuit configurations of ₂ and other components are the same as those of the conventional SRAM.

The difference from the conventional example is that the channel width of the transistor is W and the channel length is L as shown in the cell pattern of FIG. 1 (the active region in the figure is sand, the first polysilicon part is a thick line frame, the gate insulating film is Area is indicated by hatching, W corresponds to the width of the active region, and L corresponds to the width of the first polysilicon.), The same as L of the access transistors T ₃ and T ₄ and the driver transistors T ₁ and T _2. In addition, W has almost the same length (the area ratio is about 1: 1) to reduce the cell area to improve the degree of integration, and the film of the gate insulating films 2a and 2b of the driver transistors T ₁ and T _2. By reducing the thickness and making the film thickness ratio of the access transistors T ₃ and T _{4 to} the gate insulating films 3a and 3b about 2: 5 (2.5 times) or more, the desired transistor current drive capability ratio can be obtained. That is, good data retention characteristics can be maintained.

As shown in FIG. 2 showing a cross section taken along the line AA ′ of the memory cell pattern of FIG. 1, the gate insulating film of the driver transistor T ₂ may be thinner than the access transistor T _4. Recognize.

Next, the manufacturing process of the memory device of this embodiment will be briefly described with reference to FIG.

A SiO ₂ film is formed on the surface of the silicon substrate 4, and selective oxidation is further performed by the LOCOS method to form an element isolation region.

Gate part (2a, 2b, 3a, 3b part that becomes the gate insulating film)
After removing the insulating film, the first gate oxidation is performed. (At this point, the gate insulating films of T ₄ and T ₂ have the same thickness.) Only the gate insulating films 2a and 2b in the driver transistor T ₁ and T ₂ regions are selectively removed using a resist, and Two
Access transistor by performing gate oxidation of
Oxidation is added to T ₃ and T ₄ , and a gate insulating film (SiO ₂ ) thicker than the driver transistors T ₁ and T ₂ is formed. (Here, the film thickness ratio of the gate insulating film is taken.) Subsequent steps are the same as the manufacturing steps of the conventional MOS IC, and the first polysilicon 5 is grown by CVD to form the gate electrode, and the source, Phosphorus diffusion for forming the n ⁺ region of the drain is performed, contact windows of the source and drain electrodes are opened to form the second polysilicon 6, and metallization of Al 7 is performed to complete the patterning. The SiO ₂ films 8 and 9 for insulating the layers are appropriately formed by CVD growth.

The gate insulating film 2a of the present embodiment the driver transistors T _1, T _2, the gate insulating film 2b and the access transistor T _3, T ₄
The film thickness ratio with 3a and 3b was set as (1) 150A: 400A (about 2.7 times) (2) 200A: 500A (2.5 times), but both (1) and (2) were driven by the current of the desired transistor. The capacity ratio was obtained, good data retention characteristics could be maintained, and the degree of integration could be increased.

It is also possible to improve the data retention characteristic by changing the film thickness ratio of the gate insulating film while making the cell shape the same as the conventional one.

Although the high resistance load type cell has been described in the present embodiment, the present invention can be applied as it is to a full CMOS type cell other than this.

〔The invention's effect〕

As described above, by using the memory device of the present invention, a memory device having a high degree of integration and good data retention characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a memory cell pattern of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1, FIG. 3 is a circuit diagram of SRAM, and FIG. It is a conventional SRAM cell pattern. 1 ... Memory cell, 2a, 2b ... Gate insulating film, 3a, 3b ...
Gate insulating film, T ₁ , T ₂ ... Transistors (driver transistors) that form a flip-flop circuit, T ₃ , T ₄ ...
… Switching transistor (access transistor).

Claims (1)

(57) [Claims] 1. A memory device in which a memory cell includes at least a flip-flop circuit and a switching transistor, wherein a gate insulating film of a transistor forming the flip-flop circuit is thinner than a gate insulating film of the switching transistor. Memory device.