JPS60167375A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor integrated circuit element while easily executing a complicate logic design by forming a gate oxide film and a gate electrode on both surfaces of a semiconductor layer and imparting different functions to upper and lower gate electrodes holding the semiconductor layer. CONSTITUTION:N<+> layers 5, 6 as source and drain regions, gate oxide films 7, source and drain electrodes 8, 9 and gate electrodes 10 are formed by using a normal silicon semiconductor technique, thus shaping a plurality of n channel MOS field-effect transistors. Since the thickness of a polycrystalline Si film 4 is reduced to 1mum through a plurality of thermal oxidation processes during a manufacturing process and the source and drain regions 5, 6 formed through thermal diffusion are shaped sufficiently thickly, the regions 5, 6 penetrate the polycrystalline Si film 4 and are in contact with an SiO2 film 3. The n channel MOS field-effect transistors have common second gates among elements and the first gates 10 independently for each element. Accordingly, these MOSFETs can be turned ON-OFF separately by using the first gates and can also be turned ON-OFF simultaneously by one signal by using the second gates.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device made of an amorphous semiconductor layer, a polycrystalline semiconductor layer, or a single crystal semiconductor layer.

[Background of the invention]

In conventional semiconductor devices, a gate electrode is usually formed on one side of a semiconductor layer with a gate insulating film interposed therebetween. Exceptionally, H.C. de Graaff and H.Koel
mans: ” The thin-film tra
nsistor” Ph1lips Technica
lReview, Vol 27. p, 200-20
6. (Nov, 1966), in thin film transistors, etc., first layers are formed on both sides of the semiconductor layer.
In some cases, a gate and a second gate are provided, but this is because two gates are provided to control the channel (current path) from both sides of the semiconductor layer, and the first gate and the second gate have different functions. It is not intended to have. As semiconductor integrated circuits become more complex, such conventional semiconductor devices have disadvantages such as increased element area and difficulty in logic design.

[Purpose of the invention]

A first object of the present invention is therefore to reduce the device area of a semiconductor integrated circuit device, and a second object is to facilitate complex logic design.

Furthermore, a third object of the present invention is to provide a semiconductor device in which a plurality of active elements are integrated, if any.

It is possible to turn on or FFL a plurality of active elements (or fewer than the above plurality) with a single signal, and in some cases, to turn on or turn off these active elements individually. It is about making it possible.

[Summary of the invention]

In order to achieve the above first and second objects, in the semiconductor device according to the present invention, in the semiconductor device of the type mentioned at the beginning, a gate oxide film and a gate electrode are present on both sides of the semiconductor layer, and the semiconductor layer is The gist is that the upper and lower gate electrodes inserted have different functions.

In order to achieve the third object mentioned above, in an advantageous embodiment of the invention, in addition to the usual first gate, a second gate is provided which is common to the plurality of active elements.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail using examples with reference to the drawings.

Example 1 A 5IO2 film is formed on a silicon single crystal substrate by thermal oxidation, a polycrystalline S1 film is formed on this 5IO2 film by vapor deposition in an ultra-high vacuum, and an n-channel MO8 electric field is applied using this polycrystalline Si film as a material. An embodiment in which a plurality of effect transistors are integrated will be described with reference to the structural cross-sectional view of FIG.

First, P is diffused onto the surface of a p-type wheel crystal silicon wafer l whose surface is the (100) plane by a normal thermal diffusion method.
An n+ layer 2 with a thickness of 0 nm is formed. Next, a 3102 film 3 having a thickness of 4001 m is formed by a normal thermal oxidation method. At this time, the thickness of the n+ layer 2 is reduced to about 300 nm. Next, the base vacuum degree is l x 1.0-10To
S at a substrate temperature of 500''C in an ultra-high vacuum apparatus of RR.
A polycrystalline S1 film 4 is deposited to a thickness of 1.5 μm. Although the formed polycrystal S1 was not intentionally doped, it is slightly p-type due to the B impurity contained in the evaporation source. Using ordinary silicon semiconductor technology, a plurality of n-channel MO, S Form a field effect transistor. The thickness of the polycrystalline Si film 4 has been reduced to 1 μm through multiple thermal oxidation steps during the manufacturing process, and the source and drain regions 5 and 6 formed by thermal diffusion are sufficiently thick. It penetrates through the polycrystalline S1 film 4 and contacts the 5102 film 3.

The n-channel MO3 field effect transistor formed as described above has an independent first gate 10 for each element and a second gate common to the elements. Therefore, these MOSFETs are individually connected to 0N10FF using the first gate.
It is also possible to use the second gate to simultaneously output 0 on one signal.
It is also possible to perform N10FF.

Although a polycrystalline Si film is used as the semiconductor film 4 here, it is also possible to use an amorphous Si film.

Example 2 A structure of a silicon single crystal substrate-8102-silicon single crystal thin layer was created by ion implantation of a certain number of silicon crystals, and this silicon single crystal thin layer was used to form a silicon single crystal thin layer.
An embodiment in which a plurality of channel MO3 field effect transistors are integrated will be described using the structural cross-sectional view of FIG. 1, which is the same as that used in the first embodiment.

First, using a p-type wheel crystal Noricon wafer 1 with a (100) surface as a substrate, sb was grown by molecular beam epitaxy.
Si epitaxial layer 2 containing X IQ18/cm3
is formed to a thickness of 1 μm. Next, Si containing 1×1o16/cm3 of sb was prepared using the same molecular beam epitaxy method.
An epitaxial layer 4 is formed to have a thickness of 2 μm. Next, O ion implantation is performed to form a 5102 layer 3 in the lower half of 1 μm in thickness. Thereafter, the S1 layer 4 is recrystallized by performing heat treatment at 900° C. in an N2 atmosphere. As a result of the above, p-type Si substrate-n”
Si layer-8IO2 layer-n Si layer was formed. In this case, all Si layers are single crystal layers. Using the n-Si single crystal layer 4 as a material, a plurality of p-channel MO3FETs are formed in the same manner as in Example 1 except that the conductivity types are reversed.

The obtained semiconductor device had the same functions as in Example 1,
Further, since the semiconductor layer 4 is an 81 single crystal layer, the mobility is large, and the characteristics of the obtained device are better than those in Example 1.

Example 3 Next, an example in which the semiconductor device according to the present invention is applied to an actual circuit will be described. FIG. 2 is an example in which the transistor according to the present invention is applied to a flip-flop circuit. Q...
Q2 is a load, Qa, Q<, Qs is a driver transistor, 21 is a silicon wafer, 22 is a second gate, 23
is a 5i021 model, 24 is a thin film corresponding to S1 layer 4 in Fig. 1, 25 is a SiO2 protective film, 26 is an electrode, 27 is a gate oxide film, 28 is a channel region of Q2, and 29 is a channel region of Q4 and Qs. be. Note that the gates of Q4°Qs are formed from the front and back surfaces of the thin film (24 in FIG. 2 (b)), respectively. When the back gate structure transistor Q5 is in the cut-off state,
The flop circuit has a monostable state, and output terminals 01',
02 is the value of VDD or VCC. Now, let us consider a state where the output terminal 01 is at VDD, that is, the original high level. In order to reverse this state, conventionally a low level signal was added to 01 or a high level signal was added to 02. In the conventional method, in order to change the internal state of a circuit with a single timing signal, the wiring pattern connected to the output terminal O1 or 02 must be designed so as not to touch other wiring up to a predetermined position. Therefore, in a memory circuit with a large number of wires or a random linear circuit, it is extremely difficult to route these wires, and a lot of time is required for designing.

By using the transistor according to the present invention, the above signal input can be performed without increasing the wiring area. Transistor Q5 in FIG. 2(a). Q4 is an element formed on both sides of the thin film 24 (FIG. 2(b)).

Now, when the output terminal 01 is at a high level, in order to invert the flip-flop circuit using the element according to the present invention, it is sufficient to apply a high level signal to the gate terminal of the transistor Q5 to make Qs conductive. That is, by adding a transistor in parallel with transistor Q4 (or Q,), the flip-flop circuit can be inverted, and Q4
(or Q), so there is no increase in the area of the circuit.

FIG. 3 shows an example in which the above element structure is applied to a memory circuit. Fil˜F''nm is a flip-flop circuit constituting one bit, and BOI''Blm is an output terminal of the flip-flop circuit, that is, a bit line. Now, suppose that due to a certain system design, Fll and F52 must be reset at the same time. In the conventional method, the bit lines connected to Fli and F52 and the word lines (Wo+ to Wn2) must be selected at the same time to input signals. Therefore, time is required to sequentially reset each cell.

By using the device structure according to the present invention, the above-mentioned drawbacks can be easily solved. That is, by connecting the gate terminals of transistors formed on the back surfaces of the driver transistors of cells Fll and F52 in common and applying a signal, a reset signal can be easily inputted. Just make a transistor on the back side. This can be applied to initializing memory during a power outage, etc.

Embodiment 4 FIG. 4 shows an example in which the semiconductor device according to the present invention is applied to an inverter circuit. In the inverter circuit shown in FIG. 4(a), Q6 is a load transistor, Q7. Qa are transistors formed on the back surface and the front surface, respectively. The transistor Q7 whose gate electrode is formed on the substrate side is Q6, Q
There is almost no increase in area due to the placement of Q7. In the circuit of FIG. 4, the signal appearing at output terminal O1 is the AND of input signals A and B. This circuit can be applied to a memory circuit as shown in FIG. Transistors Qa-Qm are transistors according to the present invention,
M1 to Mn are circuits (for example, PLA, NAND gate) in which memory hits are arranged in a 7-nox pattern. Transistors Qa-Qm are used as switches for supplying current to M1 to Mn.

That is, M1 to Mn and Qa to Qfn constitute an AND circuit. Therefore, by changing the gate voltage of Qa-Qm, the logic within M1 to Mn can be changed. Note that if Qa-Qm is configured inside the memory, the area of the memory will be further reduced.

〔Effect of the invention〕

As mentioned above, if the semiconductor device according to the present invention is used in a memory circuit, a reduction in area and a more complex logic design can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of the present invention, and FIG. FIG. 3 is a block diagram showing an example in which the flip-flop circuit shown in FIG. 2 is applied to a memory circuit, and FIG. 4 is a circuit diagram showing an example in which the semiconductor device according to the present invention is applied to an inverter circuit and its structure. FIG. 5 is a block diagram showing an example in which the inverter circuit shown in FIG. 4 is applied to a memory circuit. 1.21... Silicon wafer 2.22...'' layer, second gate, epitaxial layer 3.23... SiO2 film 4.24... Polycrystalline S1 film, epitaxial layer 5...
- Source region 6... Drain region 7... Gate oxide film 8... Source electrode 9... Drain electrode 10.
・Kate electrode Q,, Q2. Q6...Load Q3. Q4. Q5. Q,, Q,...driver...
Transistor Qa+Qb-Qm...Transistor 01, 02...Output terminal 25...51 according to the present invention
02 Protective film 26... Electrode 27... Gate oxidation 1 copy 2
8.29... Channel region Fil~Fnm... Flip-flop circuit Bo, 7 B, m, . . ., human line Wo, ~Wn constituting 1 bit
2. ．． ．． W1' line M, -Mn...Memory bits are arranged in a matrix Junnosuke Nakamura, a patent attorney representing a circuit

Claims (2)

[Claims] (1) In a semiconductor device consisting of at least two active elements formed using an amorphous semiconductor layer, a polycrystalline semiconductor layer, or a single crystal semiconductor layer, a gate oxide film and a gate electrode are present on both sides of the semiconductor layer. A semiconductor device characterized in that upper and lower gate electrodes into which the semiconductor layer is interposed each have different functions. (2) A semiconductor device according to claim 1, characterized in that a small number of gate electrodes (at least on one side) are common to a plurality of active elements.