JP2524362B2 - Micro Processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing technique and a technique particularly effective when applied to an instruction system in a program control system, for example, a memory having an array data structure called a queue. The present invention relates to a technique effectively applied to a microprocessor having an instruction regarding the handling of.

[Conventional technology]

In a microcomputer system, a memory area of a certain size called an entry is provided on a memory, and these are connected using an index called a pointer to configure a memory of an array data structure by software (operating system). The method is known.

As shown in FIG. 4, the queue structure is provided with a plurality of entries ENT ₀ , ENT ₁ , ... ENTn on the memory.
An address indicating the starting end of the next entry to be followed by the entry is placed in the pointer Pa prepared at the head of those entries, and the entries are connected to each other using this pointer to obtain a series of data arrays. In some cases, a pointer Pb indicating a connection in the reverse direction is provided next to the pointer area Pa of each entry to create a queue having a double link structure having a connection in the forward direction and a connection in the reverse direction. The queue configured in this way is such that, for example, jobs (or tasks) requested by a plurality of users are put in each entry, and a job satisfying a predetermined condition is selected from the jobs and executed. Used in cases.

Conventionally, for example, DEC (digital equipment
Computers such as the VAX11 manufactured by Corporation) provided instructions for inserting, deleting, and replacing entries in order to facilitate the creation of the queue described above (19
December 1979 VAX11 Architectural Handbook p176-p19
Five).

[Problems to be solved by the invention]

However, the above computer does not provide an entry search command for finding a desired entry in the queue. Therefore, when finding a desired entry, a list of data transfer commands (MOVE commands) or the like had to be used instead.

As a result, it takes a long time to search the queue entries, and there is a disadvantage that the operating system for managing tables in multitasking and multiuser processing is inefficient.

An object of the present invention is to speed up queue retrieval and improve the efficiency of an operating system that handles multitasking, multiuser processing, etc. in a microprocessor that has an instruction system that supports queue creation. The purpose is to

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a representative invention among the inventions disclosed in the present application is as follows.

That is, according to the present invention, in a microprocessor having an instruction system that supports the creation of a queue, a new queue search instruction is added, and the start of the search start entry necessary for the queue search is previously added to a predetermined register. After the address, the comparison value as the selection condition, and the offset value of the search data in the entry are entered, the search instruction of the queue is executed.

[Action]

According to the above-mentioned means, the queue search instruction and the register setting instruction preceding it can be used to obtain the start address of the desired entry, thereby speeding up the queue search and operating system handling multitasking, multiuser processing, etc. The above-mentioned object of improving the efficiency of can be achieved.

〔Example〕

FIG. 1 (A) shows the execution of an instruction format of a queue search instruction (hereinafter referred to as a queue search instruction) when the present invention is applied to a microprocessor having an instruction system in which 16 bits or 32 bits are used as an instruction composition unit. An example is shown.

The queue search instruction shown in FIG. 1 (A) includes operation designation sections OP ₁ and OP _{2 in} which an operation code consisting of upper 16 bits and lower 8 bits is entered, and an end condition designation EC for designating the end condition of the instruction and A size designation section Sz indicating the size of the comparison value, a bit Bi designating the instruction format, an M bit indicating whether R ₆ is masked or not, an E bit indicating the end value of the queue, and a U bit indicating the search direction. It is composed by.

FIG. 1B shows a second form of the queue search instruction according to the present invention. This second instruction format is the first
Is different from the instruction format (FIG. 1 (A)) in that it uses immediate addressing with respect to the offset value. In the second instruction format, the operation designation section OP ₂ in the first instruction format is used. That is, the lower 5 bits of the 7 bits are set as the immediate portion IM.

The first instruction format and the second instruction format of the queue search instruction are distinguished by the bit Bi described above. For example, if this bit Bi is "0", the lower 5 bits of the instruction word are the operation designating section. Treated as OP ₂ , Bit B
If i is "1", the lower 5 bits are immediate part I
Treated as M. However, IM Immediate Department IM is 5
Since it is a bit, in order to obtain a 32-bit offset, it is necessary to convert the 5-bit code of the immediate portion into a 32-bit width by sign extension or the like.

The end condition designating unit EC is composed of 4 bits in this embodiment, and the 4-bit code is shown in Table 1 below.
Is defined as

In the figure, each symbol =, ≠, <,> has a mathematical meaning. End conditions No.1 to No.5 show the case where the end condition is set by comparing the data read from the entry with the search in register R3, and end conditions No.6 to No.9 are in the registers R3 and R4. The case where the end condition is set by comparison with the value of is shown.

The size designation section Sz is composed of 2 bits. For example, if the 2 bits are "00", the comparison value is 8 bits,
"01" indicates 16 bits, and "10" indicates 32 bits. Therefore, if this comparison value is preloaded into a register (32 bits), as described below,
Depending on the contents of the size designation section Sz, the lower 8 bits of information in the register are treated as valid comparison values, or the lower 16 bits or all bits are treated as comparison values.

Further, in the above embodiment, when the M bit is 0, it means that there is no mask by the register R6, and when it is 1, it means that there is a mask. The E bit indicates the end condition of the queue,
The end condition is 0 when E = 0, and the register R ₂ when E = 1
It becomes the contents of. The code U of the least significant bit of the operation designation part OP ₂ is treated as a code indicating the search direction,
For example, if U is "0", the search is performed in the forward direction, and if U is "1", the search is performed in the reverse direction.

In the instruction formats shown in FIGS. 1A and 1B, the arrangement of each field within 32 bits has no essential meaning. However, in a microprocessor in which 16 bits are used as an instruction reading unit, the 32-bit queue search instruction is read as two words into the instruction register in 16-bit divisions twice.

FIG. 1C shows another embodiment of the queue search instruction according to the present invention. This cue search instruction consists of 16 bits. The fact that this command is a queue search command is specified by the operation specifying units OP ₁ , OP ₂ and OP ₃ . In addition to the 2-bit size designating section Sz and the 4-bit end condition designating section EC, the above M bits, U bits and the like are included. When executing this instruction, the necessary offset value is set in advance in a specific register, for example, register R ₅ or the like. The P bit specifies the size of data to be handled. For example, when P = 0, 32 bits, P = 1
Is set to 64 bits.

Next, FIG. 2 shows a processing flow of a microprogram in the microprocessor which decodes and executes the queue search instruction. However, in the microprocessor of this embodiment, the leading address of the search start entry, the comparison value, and the offset value (not required in the second instruction format) necessary for searching the queue are already stored in the predetermined general-purpose registers, for example, R ₁ , R ₃ , The queue search instruction is executed on the assumption that they are loaded into R ₅ respectively.

Furthermore, the status register in the microprocessor has a flag (hereinafter "F") indicating whether or not the search is completed.
(Referred to as a flag) is newly provided. When the "F" flag is "0", it indicates that the search is successful, and when it is "1", it indicates that the desired entry does not exist.

The procedure for executing the queue search instruction will be described according to the flow of FIG. 2. First, in step S1, the start address of the start entry in the register R ₀ is set to the temporary register TEMP.
Set (copy) to (lens not opened to user). Next, in step S2, the memory is accessed at an address obtained by adding the offset value in the register R ₅ or the immediate portion to the address in the lens R ₀ ,
The data is compared with the search data (comparison value) of the register R ₃ to determine whether or not the specified condition (see Table 1) is satisfied. In this example, the termination condition BBBB
Shows that 0001 is 0001. That is, assuming that the entry ENT ₀ is the search start entry in FIG. 4, the data Key at the address position obtained by adding the offset value OF to the start address A of the entry ENT ₀ is read out and stored in the register R ₃ . It is to determine whether or not the search data matches the entered search data.

If YES is determined in step S2, step S7
Then, the flow advances to and the "F" flag is cleared to "0" and the instruction is ended. That is, since the data read Key and search data (comparison value) and that matches in step S2, is at the head address of the entry to determine the address contained in the time register R _0, the address in the register R ₀ You can end the search while leaving. Fourth
In the example of the figure, the address A ₀ is stored in the register R ₀ , and the process ends.

If NO is determined in step S2, the process proceeds to step S3, in which it is determined whether the code of bit U is "0". If the bit U is "1", the step
The S4 by accessing the memory address obtained by adding "4" to the address in register R ₀ places the data in the register R _0. If the data width is 32 bits and addressing is possible in word units, the position where "4" is added to the entry start address stored in the register R ₀ is the reverse search position in FIG. It is a pointer Pb containing the start address of the next entry in the case.

Therefore, this causes a backward search of the queue. On the other hand, when the bit U is “0”, the step
Accesses the memory by the address contained shifts to S5 is the register R ₀ places the data in the register R ₀ in. That is, in FIG. 4, the head address of the next entry indicated by the pointer Pa in the forward direction of the entry that has been searched is stored in the register R ₀ .

After that, the process proceeds to step S6, and the value in the lens R _{0 at} that time is compared with the value in the tempo register TEMP containing the value of the register R _{0 in} step S1 to determine whether or not they match, If not, the process returns to step S2 to repeat the above procedure, and if they match, the process proceeds to step S8, sets "1" in the "F" flag, and ends. In other words, the fact that the values in both registers match in step S6 means that the entry to be searched in FIG. 4 has returned to the entry that started the search, and the queue has been searched through but the desired entry has It did not exist. Therefore, the search is unsuccessful and is ended.

In this way, the queue search instruction is executed and "F"
Is cleared to "0" and ends, the address stored in the register R ₀ at that time is the start address of the desired entry, and then the data in the corresponding entry is read based on the address in R ₀ . , Multitasking and multiuser processing proceed smoothly.

Thus, in the above embodiment, the registers R ₀ , R ₃ and R ₅ are previously set.
It is possible to execute the queue search with one instruction on the assumption that the start address, the comparison value, and the offset value of the search start entry are included in each. Therefore, without this queue search instruction, the operating system is much more efficient and the time required to search for an entry is shortened as compared with the method of searching with a MOVE instruction or the like.

In addition to the queue search instruction, the microprocessor of the above-described embodiment is provided with instructions such as entry insertion, deletion, and replacement.

FIG. 3 shows an example of a hardware configuration of a microprocessor that operates according to an instruction system having a queue search instruction according to the present invention.

The microprocessor of this embodiment includes a control unit of a micro program control system. That is, a micro ROM (read only memory) 2 in which a micro program is stored is provided in an LSI chip 1 which constitutes a microprocessor. The micro ROM 2 is accessed by the micro address generating circuit 5 and sequentially outputs micro instructions constituting a micro program.

The micro address generation circuit 5 is supplied with a signal obtained by decoding the code of the macro instruction fetched into the instruction register 3 by the instruction decoder 4. The micro address generation circuit 5 forms a corresponding micro address based on this signal and supplies it to the micro ROM 2. As a result, the first instruction of a series of microinstructions for executing the macro instruction is read. The micro-instruction code forms control signals for various temporary registers, data buffers, an execution logic unit ALU, an execution unit 6 including an address calculation unit AU, and the like.

2 of a series of microinstructions corresponding to macroinstructions
The reading of the micro instructions after the th is performed by supplying the code of the next address field of the micro instruction read immediately before to the micro ROM 2. That is, the microinstruction latch circuit 9 for holding the next address in the immediately preceding microinstruction is provided, and the second and subsequent microinstructions are read based on the output thereof and the address from the microaddress generation circuit 4. . The series of micro-instructions read in this way is
The instruction is decoded by the micro instruction decoder 10 and the output control signal controls the execution unit 6 to execute the macro instruction. The address calculation unit AU calculates the address of the memory based on the information such as the offset value.

In this embodiment, although not particularly limited, the buffer storage system is adopted, the cache memory 7 is provided in the microprocessor LSI, and the program data having a high address frequency among the data in the external memory 8 is stored in the cache memory 7. Will be registered within. This speeds up the loading of the program.

5 (A) to 5 (C) show another embodiment of the processing flow based on the queue search instruction according to the present invention. When this instruction is executed, information necessary for searching the queue is written in a predetermined register in the microprocessor in advance. That is, the first comparison value in the start address register R ₃ search end entry in the register R _2, the second comparison value in the register R _4, the offset value in the register R _5, mask the register R ₆ Data is set. The mask data is data used to give meaning only to a predetermined bit of a plurality of bits forming a certain data. Further, in this embodiment, two registers R ₀ and R _{1 for} setting the entry start address are provided. Here, the start address of the entry being searched is set in the register R ₀ ,
The start address of the entry immediately before the entry being searched is set in the register R ₁ . By providing the register R ₁ in addition to the register R ₀ , it is possible to increase the flexibility of means for recognizing the start address and the like of the entry being searched in the microprocessor. Further, a flag F and a flag V are provided in the status register in the microprocessor. The flag F is the register R ₃ described above.
Is used to display the result of the search using the first comparison value in the register V, and the flag V is used to display the result of the search using the second comparison value in the register R ₄ . Used for. Therefore, if the second comparison value is not used for the determination in the search, the information of the flag V has no meaning. Although not particularly limited, the flag F or V is 0
The case of "1" indicates that the search conditions are matched, and the case of "1" indicates that the search conditions are not matched. An example of the search condition is shown in Table 1 above.

Explaining the execution procedure of the queue search instruction according to the flow of FIG. 5A, it is first determined in step ST1 whether or not an interrupt request exists. If there is an interrupt, this takes priority, so the queue search instruction ends. If there is no interrupt, the process proceeds to step ST2. In step ST2, the contents of register R ₀ are set in register R ₁ . As a result, the content of the register R ₁ is updated. In step ST3, it is determined whether the U bit is 0 or not. If U = 0, it means that the search is a forward search. Therefore, the process proceeds to step ST9, the memory is accessed by the address in the register R ₁ and the data is stored in the register R ₀ . If U = 1, it means that the search is a backward search. Therefore, the process proceeds to step ST4, the memory is accessed at the address obtained by adding 4 to the address in the register R ₁ , and the data is stored in the register R ₀ . In step ST4 or ST9, the start address of the entry to be searched is set in the register R ₀ .
Next, in step ST5, it is determined whether the contents of the register R _{0 and} the contents of the register R ₂ match. If the above contents match, it means that the entry to be searched has reached the search end entry, so the flag F is set to 1 (step ST10), and then the search instruction is ended. If the above contents do not match, the process proceeds to step ST6 and it is determined whether or not a mask is necessary for the data used for the search. If M = 1, it means that a mask is required, and the process proceeds to step ST12 shown in FIG. 5 (B).
The processing flow shown in FIG. 5 (B) will be described later. M
If = 0, it means that the mask is not necessary, and the process proceeds to step ST7. In step ST7, it is determined whether or not the content of the register R ₄ is required in the determination of the search end condition. Steps shown in Fig. 5 (C) if necessary
Move to ST17. The processing flow shown in FIG. 5 (C) will be described later. If the register R ₄ is not required, the process proceeds to step ST8. At step ST8, the memory is accessed at the address obtained by adding the offset value in the register R _{5 to} the address in the register R ₀ , and the data and the register R ₅ are accessed.
By comparing with the comparison value in ₃ , it is determined whether the specified condition (see Table 1) is satisfied. In this example,
The case where the end condition BBBB is 0001 is shown. That is, in FIG. 4, assuming that the entry ENT0 is the search start entry, the offset value is set to the start address A of the entry ENT0.
The data Key in the address position to which OF is added is read out and it is determined whether or not it matches the search data in the register R ₃ . Step ST
If YES is determined in step 8, the process proceeds to step ST11, the flag F is cleared to "0", and the instruction is ended. That is, since the read that data Key and the search data (comparison value) and matches in step ST8, is the beginning address of the entry to determine the register at that time are in the register R _0, the address in the register R ₀ You can end the search while leaving. In the example of FIG. 4, it means that the address A ₀ is stored in the register R ₀ and the process ends. If NO is determined in step ST8, the process returns to step ST1.

Next, the processing flow shown in FIG. 5 (C) will be described. The processing flow shown in FIG. 5 (C) is a flow necessary when YES is determined in step ST7 shown in FIG. 5 (A). In the embodiment shown in FIG. 5 (C), the end condition BBBB is 1000. In step ST17, the memory is accessed at the address obtained by adding the offset value in the register R _{5 to} the address in the register R ₀ to judge the magnitude relation between the data and the first comparison value in the register R ₃ . When the data is larger than the first comparison value, one of the end conditions is satisfied, so the flag F is set to 0 (step ST20) and the process proceeds to step ST18. If the above data is equal to or smaller than the first comparison value, the end condition is not satisfied, so the flag F remains the initial value 1 and the process proceeds to step ST18. In step ST18, the above data and register R ₄
The magnitude relationship with the second comparison value within is determined. When the data is smaller than the second comparison value, one of the end conditions is satisfied, so the flag V is set to 0 (step ST21) and the process proceeds to step ST19. If the above data is equal to or larger than the second comparison value, the end condition is not satisfied, so flag V
Shifts to step ST19 while keeping the initial value 1. Step 19
Then, it is determined whether the flags F and V are both 0. If F = 0 and V = 0, all the end conditions are satisfied, so the instruction ends. If F = 1 or V = 1, the termination condition is not satisfied, and therefore the process returns to step ST1.

Next, the processing flow shown in FIG. 5 (B) will be described. The processing flow shown in FIG. 5 (B) is a flow necessary when YES is determined in step ST6 shown in FIG. 5 (A). In step ST12, as in step ST7 shown in FIG. 5 (A), it is determined whether the contents of the register R ₄ are necessary in the determination of the search end condition. The flow when the content of the register R ₄ is required is basically the same as the flow shown in FIG. If the contents of register R ₄ are not required, the process proceeds to step ST13. In step ST13, register R
_The memory is accessed at an address obtained by adding the offset value in the register R ₅ to the address in ₀ , and the data is masked by the contents of the register R ₆ . Specifically, the logical product (AND) of the above data and the contents of the register R ₆ is taken, and the result is set in the register R ₇ . In step ST14, the logical product (AND) of the comparison value in the register R ₃ and the contents of the register R ₆
And the result is set in the register R ₈ . In step ST15, the contents of the register R _{7 and} the contents of the register R ₈ are compared to determine whether the specified condition (see Table 1) is satisfied. In this embodiment, the termination condition BBBB is 0001
Shows the case. If YES is determined in step ST15, the process proceeds to step ST16, the flag F is cleared to 0, and the instruction is ended. If NO is determined in step ST15, the process returns to step ST1.

As described above, according to this embodiment, in a microprocessor having an instruction system for supporting the creation of a queue, a new queue search instruction is added, and a search necessary for the queue search is performed in advance in a predetermined register. Since the start address of the start entry, the comparison value as the selection condition, and the offset value of the search data in the entry are entered, the above-mentioned queue search command is executed, so the queue search command and the register setting command preceding it By the action that you can get the start address of the desired entry,
This has the effect of speeding up the queue search and improving the efficiency of the operating system that handles multitasking, multiuser processing, and the like.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the queue search can be executed by one instruction on the assumption that the start address, the comparison value, and the offset value of the search start entry are stored in the registers R ₀ , R ₃ , and R ₅ in advance. However, instead of setting the start address and the like in the register in advance with an instruction, they may be given as an operand of the queue search instruction.

In the above description, the case where the invention made by the present inventor is mainly applied to the instruction format of the microprocessor, which is the field of application of the background, has been described, but the present invention is not limited thereto, and a computer or a minicomputer is used. It can be used for the general command format of the data processing system of the program control system.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

That is, it is possible to speed up the queue search and improve the efficiency of the operating system that handles multitasking, multiuser processing, and the like.

[Brief description of drawings]

1 (A) to 1 (C) are explanatory views showing a configuration example of a format of a queue search instruction according to the present invention, and FIG. 2 is an example of a processing procedure when the queue search instruction is executed by a microprogram. FIG. 3 is a block diagram showing a configuration example of a microprocessor for executing a queue search instruction according to the present invention, FIG. 4 is an explanatory diagram showing a configuration example of a queue on a memory, and FIG. 5 (A). (C) is a flowchart showing another example of the processing procedure when the queue search instruction according to the present invention is executed by the microprogram. OP ₁ , OP ₂ , OP ₃ …… Operation designation part, EC …… End condition designation part, Sz …… Operand size designation part, IM …… Immediate part, AU …… Address calculation unit, ALU…
… Arithmetic logic unit.

Front page continuation (72) Inventor Koji Hashimoto 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer Engineering Co., Ltd. (72) Ikuya Kawasaki 1450, Kamimizumoto-cho, Kodaira, Tokyo Hitachi Ltd. Inside the Musashi Factory (72) Inventor Atsushi Hasegawa 1479 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Micro Computer Engineering Co., Ltd. In-house (56) Reference JP-A 52-2236 (JP, A) JP-A 59-60650 (JP, A) JP-A 61-289428 (JP, A) JP-A 63-55636 (JP, A) Actual Development Sho 54-16335 (JP, U)

Claims (1)

(57) [Claims] 1. Decoding means for decoding the content of an instruction,
There is an execution means for executing an instruction based on the output of the decoding means, and the instruction finds a desired data storage area from a plurality of data storage areas in the memory and indicates at least a search end condition and a search direction. A microprocessor, which is a search instruction including information, judges whether or not an interrupt request exists in the execution of the search instruction, terminates the search instruction if there is an interrupt, and if there is no interrupt, 1
A means for setting the address of the register in the second register and updating the address of the second register, and determining whether the bit indicating the search direction is the forward search or not, and if the forward search is performed, the second register Is accessed to set the address in the first register. On the other hand, in the case of reverse search, the memory is accessed at an address obtained by adding a predetermined value to the address in the second register to set this address to the first register. If the means for setting the register 1 and the address of the first register and the address of the third register in which the search end address is set match, and if the search end address is reached, then the search instruction is executed. And a means for shifting to the subsequent processing if the search end address has not been reached. Processor.