JP2519903B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2519903B2 JP2519903B2 JP61218807A JP21880786A JP2519903B2 JP 2519903 B2 JP2519903 B2 JP 2519903B2 JP 61218807 A JP61218807 A JP 61218807A JP 21880786 A JP21880786 A JP 21880786A JP 2519903 B2 JP2519903 B2 JP 2519903B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- adhesive
- lead frame
- heating
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置とリードフレームとのダイボンド
に関し、特に半導体装置の非能動素子面とリードフレー
ムを介する接着剤に関する。また、更に、該半導体装置
とリードフレームとの接着剤を脱泡し接着することに関
する。Description: TECHNICAL FIELD The present invention relates to a die bond between a semiconductor device and a lead frame, and more particularly to an adhesive between the inactive element surface of the semiconductor device and the lead frame. Furthermore, it further relates to defoaming and adhering the adhesive between the semiconductor device and the lead frame.
従来、ダイボンディングは第１図に示す様な工程を経
てダイボンディングしている。先ず１はリードフレー
ム、２は接着剤、３は半導体装置を示す。半導体装置の
組み立て工程に於けるダイボンディングはリードフレー
ム１のダイパット部上に接着剤であるAgペースト２を吐
出し、更にその上に半導体装置３を載せ、これを焼成炉
にて焼成し、半導体装置とリードフレームとを密着させ
ている。焼成に関しては恒温槽及びリフロー炉等を用い
て200℃で焼成を完了し次工程であるボンディングを実
施していた。Conventionally, die bonding has been performed by the steps shown in FIG. First, 1 is a lead frame, 2 is an adhesive, and 3 is a semiconductor device. For die bonding in the process of assembling a semiconductor device, the Ag paste 2 which is an adhesive is discharged onto the die pad portion of the lead frame 1, the semiconductor device 3 is further placed thereon, and the semiconductor device 3 is baked in a baking furnace. The device and the lead frame are in close contact. Regarding firing, firing was completed at 200 ° C using a thermostat and a reflow oven, and the next step, bonding, was performed.
しかし、この様な工程を経てダイボンドを実施すると
接着剤の粘度を一定に保たなければならない。その理由
は粘度変化により、リードフレームから半導体装置の能
動素子面までの高さに±50μｍのバラツキが生じ、オー
トワイヤーボンデュング装置での配線工程ができないと
いう大きな問題が生じる。また、この接着剤の粘度を一
定に保持しても必ず半導体装置とリードフレーム間にボ
イド（気泡）が発生する為に配線工程のボンディング途
中に半導体装置がリードフレームから剥離してしまうと
いう問題が生じ半導体装置組み立て工程の歩留りを低下
させる大きなネックとなっていた。However, when die bonding is performed through such steps, the viscosity of the adhesive must be kept constant. The reason is that there is a variation of ± 50 μm in the height from the lead frame to the active element surface of the semiconductor device due to the change in viscosity, which causes a big problem that the wiring process in the auto wire bonding device cannot be performed. Further, even if the viscosity of the adhesive is kept constant, voids (air bubbles) are always generated between the semiconductor device and the lead frame, so that the semiconductor device may be separated from the lead frame during the bonding process in the wiring process. This is a major bottleneck that reduces the yield of the semiconductor device assembly process.
そこで本発明はこの様な問題点を解決するもので、そ
の目的は半導体装置組み立て工程中の配線工程での歩留
りを向上させ、更にリードフレームと半導体装置との密
着性を向上させることを目的とする。Therefore, the present invention solves such a problem, and an object thereof is to improve the yield in the wiring process during the semiconductor device assembly process, and further to improve the adhesion between the lead frame and the semiconductor device. To do.
本発明は、リードフレーム上に硬化したフイルム状の
接着剤を載置する工程、前記接着剤上に半導体装置を載
せる工程、減圧雰囲気下で加熱し前記接着剤を硬化状態
から軟化状態へ変化させる前記接着剤を脱泡する第一加
熱工程、引き続き、減圧雰囲気下で加熱し前記接着剤を
軟化状態から再び硬化状態へ変化させ、前記リードフレ
ームと半導体装置を接着させる第二加熱工程を有するこ
とを特徴とする。According to the present invention, a step of placing a cured film-like adhesive on a lead frame, a step of placing a semiconductor device on the adhesive, and heating in a reduced pressure atmosphere to change the adhesive from a cured state to a softened state A first heating step of defoaming the adhesive, and a second heating step of subsequently heating the adhesive in a reduced pressure atmosphere to change the adhesive from a softened state to a cured state again and adhering the lead frame to the semiconductor device. Is characterized by.
本発明の作用を述べれば、Agペーストを厚さ数十ミク
ロンのフィルム状にし半導体装置に載せ、焼成時に熱軟
化から熱硬化に変化する途中で減圧を実施しているので
脱泡を行なうことができ、高気密性保持につながる。To describe the operation of the present invention, the Ag paste is formed into a film having a thickness of several tens of microns and placed on a semiconductor device, and decompression can be performed because decompression is performed during the change from thermal softening to thermosetting during firing. The result is high airtightness.
以下、本発明について、実施例に基づいて詳細に説明
する。Hereinafter, the present invention will be described in detail based on examples.
第２図は本発明の断面図である。４はリードフレーム
５はAgペースト（半導体装置と同一形状にした所のフィ
ルム状のペースト）である。６は半導体装置である。先
ず、本発明のダイボンディング工程を説明すると、リー
ドフレーム４のダイパット部に縦1.2mm、横1mm四方のAg
ペーストをフィルム化した物を吸着装置を用いて載せ、
更にその上に半導体装置（縦1mm、横0.8mm）の能動素子
面を上方にしてフィルム化したAgペースト５の上に載せ
る。更にこの半導体装置とリードフレームを密着させ接
着する為に減圧焼成炉を用いて接着剤が軟化した時に脱
泡作用が働く様に200℃で減圧焼成した。この様にして
リードフレームと半導体装置とを十分に接着した物のリ
ードフレームから半導体装置の能動面までの高さバラツ
キを測定した所、（各５ポイントを対象に測定）±５μ
ｍ以内のバラツキを示した。この物を配線工程であるボ
ンディング装置にてAu配線を施した。FIG. 2 is a sectional view of the present invention. Reference numeral 4 is a lead frame 5 is Ag paste (a film-like paste having the same shape as the semiconductor device). 6 is a semiconductor device. First, the die bonding process of the present invention will be described. In the die pad portion of the lead frame 4, 1.2 mm long by 1 mm square Ag
Place the paste film using an adsorption device,
Further, a semiconductor device (length 1 mm, width 0.8 mm) is placed on the Ag paste 5 formed into a film with the active element surface facing upward. Further, in order to bring the semiconductor device and the lead frame into close contact with each other and adhere to each other, a reduced pressure firing furnace was used to perform reduced pressure firing at 200 ° C. so that the defoaming action works when the adhesive softens. In this way, the variation in height from the lead frame of the article in which the lead frame and the semiconductor device are sufficiently adhered to the active surface of the semiconductor device is measured (measured for each 5 points): ± 5 μ
The variation was within m. This product was subjected to Au wiring by a bonding device which is a wiring process.
この様に接着剤の厚みバラツキが極力押さえられたこ
とによりボンディング工程での配線不可能という問題が
なくなった。また、減圧焼成炉を用いたことによりリー
ドフレームと半導体装置の中間に生じるガイド（気泡）
がなくなり配線工程で半導体装置がリードフレームから
剥離するという重大な問題が解決された。尚、今回使用
した接着剤はAgペーストを102μｍの厚みに切断したフ
ィルム状にしたペーストを用い、特性としては、初期に
は硬化しており、50℃近辺で軟化し、100℃近辺でまた
硬化に向かう物を選択した。以上の様な実施例に於い
て、接着剤をフィルム化し、この接着剤を用いて半導体
装置を接着し減圧焼成炉にて焼成することによりボンデ
ィング工程での不良率を軽減し、更には品質の向上に効
果が高まる。As described above, the thickness variation of the adhesive is suppressed as much as possible, so that the problem that wiring is impossible in the bonding step is eliminated. In addition, a guide (air bubble) generated between the lead frame and the semiconductor device by using the reduced pressure baking furnace.
The problem that the semiconductor device is separated from the lead frame in the wiring process is solved. The adhesive used this time was a film-shaped paste obtained by cutting Ag paste to a thickness of 10 2 μm. As a characteristic, it was hardened initially, softened at around 50 ° C, and softened at around 100 ° C. Moreover, the thing which goes to hardening was selected. In the above examples, the adhesive is formed into a film, the semiconductor device is bonded using this adhesive, and the defective rate in the bonding step is reduced by firing in a reduced-pressure firing furnace. The effect is improved.
本発明は、以上説明した様に、接着剤をフィルム化し
た物を用いることで接着剤のバラツキを均一化し、更に
減圧焼成炉を用いることで接着剤の中の気泡が脱泡で
き、ボイドの発生が押さえられ、ボンディング工程での
Au配線の信頼性が向上した。The present invention, as described above, uniformizes the dispersion of the adhesive by using a film of the adhesive, and by using a reduced-pressure firing furnace, the bubbles in the adhesive can be defoamed and Occurrence is suppressed, and in the bonding process
The reliability of Au wiring has been improved.
第１図は従来のダイボンディングを示す図である。第２
図は本発明のダイボンディングを示す図である。 1,4……リードフレーム ２……接着剤 3,6……半導体装置 ５……フィルム化した接着剤FIG. 1 is a diagram showing a conventional die bonding. Second
The figure shows the die bonding of the present invention. 1,4 ...... Lead frame 2 …… Adhesive 3,6 …… Semiconductor device 5 …… Filmed adhesive
Claims (1)
接着剤を載置する工程、前記接着剤上に半導体装置を載
せる工程、減圧雰囲気下で加熱し前記接着剤を硬化状態
から軟化状態へ変化させる前記接着剤を脱泡する第一加
熱工程、引き続き、減圧雰囲気下で加熱し前記接着剤を
軟化状態から再び硬化状態へ変化させ、前記リードフレ
ームと半導体装置を接着させる第二加熱工程を有するこ
とを特徴とする半導体装置の製造方法。1. A step of placing a cured film-like adhesive on a lead frame, a step of placing a semiconductor device on the adhesive, and heating the adhesive under a reduced pressure atmosphere to change the adhesive from a cured state to a softened state. A first heating step of defoaming the adhesive, followed by a second heating step of heating in a reduced pressure atmosphere to change the adhesive from a softened state to a cured state again and adhering the lead frame and the semiconductor device A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61218807A JP2519903B2 (en) | 1986-09-17 | 1986-09-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61218807A JP2519903B2 (en) | 1986-09-17 | 1986-09-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6373630A JPS6373630A (en) | 1988-04-04 |
| JP2519903B2 true JP2519903B2 (en) | 1996-07-31 |
Family
ID=16725653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61218807A Expired - Lifetime JP2519903B2 (en) | 1986-09-17 | 1986-09-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2519903B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125025A (en) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Manufacture of semiconductor device |
-
1986
- 1986-09-17 JP JP61218807A patent/JP2519903B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6373630A (en) | 1988-04-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |