JP2519876B2 - Information signal forming and supplying device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal forming and supplying device which obtains an information signal concerning a vehicle speed and a running state of a vehicle and supplies the information signal to a control unit provided in the vehicle.

[0002]

2. Description of the Related Art In vehicles, in order to measure vehicle speed,
2. Description of the Related Art Various rotation detection devices for detecting the rotation state of a rotating body placed in a rotation state according to the vehicle speed of an output shaft of a transmission and the like have been put into practical use. The general type of such rotation detection device is
A rotating disk that rotates with or in conjunction with the rotating body whose rotational state is to be detected is provided, and the rotating disk has a large number of light-reflecting parts, light-transmitting parts, or light-receiving parts along the circumferential direction. It is assumed that the detected parts such as magnetic parts are arranged in an annular shape, and the detector that optically or magnetically detects the detected parts and generates a detection signal according to the arrangement of the detected parts rotates. It is installed and configured on a disc so that the frequency or phase of the detection signal obtained from the detector will correspond to the rotating state of the rotating body when the rotating body whose rotation state is to be detected rotates. To be done.

In the rotation detecting device equipped with such a rotating disc, the detection accuracy depends on the fine density of the detected portions which are annularly arranged on the rotating disc.
For example, when each detected portion is a light reflecting portion or a light transmitting portion such as a through hole, there is a processing limit when forming a large number of light reflecting portions or light transmitting portions on the rotating disk, and there is a limit in processing. It is difficult to sufficiently increase the density. Further, if each light reflecting portion or light transmitting portion is made narrow so as to increase the fine density, there is a disadvantage that the S / N ratio of the detection signal obtained from the detector is lowered.

For this reason, some measures have been proposed for improving the detection accuracy while keeping the fine density of the light reflecting portions or light transmitting portions formed on the rotating disk within a predetermined range. For example, as described in Japanese Utility Model Laid-Open No. 55-172856, an annular array of light-reflecting portions or light-transmitting portions is provided in the radial direction of the rotating disk so as to be doubled inside and outside thereof. The two optical detectors corresponding to the respective annular arrangements of the light-reflecting portions or the light-transmitting portions are arranged, and the detection signals obtained from the respective optical detectors are combined. As a result, the detection accuracy is substantially improved. It is known to obtain a detection output that will be enhanced to.

However, as described above, in the rotation detecting device provided with the rotating disk, the annular array of the inner and outer light reflecting portions or the light transmitting portions is doubled on the rotating disk. In this case, the manufacturing process of the rotating disk becomes complicated and the rotating disk cannot be easily obtained, and the rotating disk tends to increase in size. As a result, the manufacturing cost of the device is increased. And the size of the entire device increases.

Therefore, a plurality of parts to be detected are formed in an annular shape so as to surround the center of rotation, and rotate with the rotating body whose rotational state is to be detected or in conjunction therewith, and this rotating disk. A plurality of detectors that are arranged close to the disk and that generate a detection pulse train signal according to the arrangement of the detected parts are provided, and the detection pulse train signals obtained from each of the plurality of detectors are predetermined. The detection signals are arranged so that they have a mutual phase difference, and the detection pulse train signals are combined to improve the detection accuracy. In addition, a rotation detection signal generating device that is designed to be easily manufactured is considered.

A plurality of detection pulse train signals from such a rotation detection signal generator need them in common. For example, a plurality of controls such as a meter control unit, an antilock brake control unit, an auto cruise control unit, etc. The control unit is supplied to the unit, and based on the plurality of detection pulse train signals, the rotation state of the rotating body whose rotation state is to be detected, and thus a signal corresponding to the vehicle speed of the vehicle, and further to the running state of the vehicle. The corresponding signal is obtained and the control required for each is performed.

[0008]

As described above, a predetermined detection output signal is supplied to each of the plurality of control units,
In each control unit, under the control system in which a signal according to the vehicle speed based on the supplied detection output signal, a signal according to the traveling state of the vehicle, etc. are formed, each of the plurality of control units is For example, a signal forming unit for forming a signal according to the vehicle speed based on the detection output signal, and a signal forming unit for forming a signal according to the traveling state of the vehicle based on the detection output signal It is said that That is, each of the plurality of control units, which are configured to perform respective control operations by commonly using the detection output signal from the rotation detection signal generator, forms a signal according to the vehicle speed and a vehicle. The signal forming units for forming signals according to the traveling state of No. 1 are individually provided, and the signal forming units are redundantly installed. Such overlapping installation of the signal forming units is not only unreasonable in that the number of signal forming units more than the truly required number is installed, and each of them is in an inefficient use state. The wiring for supplying signals to the parts is complicated, and the amount of wiring is increased, which is inconvenient.

In view of the above point, the present invention includes a detection unit that generates a detection output signal that changes with a change in the vehicle speed of the vehicle, and determines the vehicle speed of the vehicle based on the detection output signal from the detection unit. A signal forming unit for forming a signal, a signal forming unit for forming a signal according to the running state of the vehicle based on the detected output signal, and a signal formed by each signal forming unit for the vehicle. Provided is an information signal forming / supplying device, in which a signal supply unit for supplying a control unit can be used in a highly efficient use state and wiring for supplying a signal to the control unit can be simplified. The purpose is to do.

[0010]

In order to achieve the above object, an information signal forming / supplying device according to the present invention is provided in a vehicle.
A control circuit unit for controlling for a particular device that is configured to include a detection section for generating a detection output signal that varies with variations in the vehicle speed in the vehicle. And control times
A first signal and a second signal, in which the road portion obtains a vehicle speed information signal corresponding to a vehicle speed of the vehicle and a traveling state information signal representing a traveling state of the vehicle by subjecting a detection output signal obtained from the detection section to a predetermined process. The signal processing unit having the forming unit, and the vehicle speed information signal and the traveling state information signal obtained by the signal processing unit are not related to the above-mentioned specific device installed in the vehicle.
Is <br/> is to include a supply signal supply unit to have the control unit.

[0011]

In the information signal forming / supplying device according to the present invention having the above-mentioned structure, the detection output signal from the detecting section is
The detected signal is supplied to the signal processing unit included in the control circuit unit, and the detected signal is subjected to predetermined processing by the first signal forming unit to form a vehicle speed information signal corresponding to the vehicle speed of the vehicle. The detected signal is subjected to a predetermined process by the second signal forming means included in the signal processing unit to form a traveling state information signal representing the traveling state of the vehicle. Then, by the signal supply unit included in the control circuit unit ,
The vehicle speed information signal and the traveling state information signal, which are respectively formed by the first signal forming unit and the second signal forming unit in the signal processing unit , are identified by the signal processing unit as installed in the vehicle.
Is supplied to the control unit regardless of the device .

As a result, for example, when a plurality of control units installed in a vehicle require a signal corresponding to the vehicle speed of the vehicle based on a detection output signal from the detection unit and a signal corresponding to the running state of the vehicle. Included in the control circuit section
The vehicle speed information signal and the traveling state information signal obtained from the signal processing unit are supplied to each control unit by the signal supply unit included in the control circuit unit, so that each of the plurality of control units changes the vehicle speed of the vehicle. Therefore, it is not necessary to individually provide a signal forming unit for forming a corresponding signal and a signal forming unit for forming a signal according to the traveling state of the vehicle. That is, a signal corresponding to the vehicle speed of the vehicle and a signal corresponding to the running state of the vehicle are provided based on the detection output signal from the detection unit, which is provided in the control circuit unit as the first signal forming unit and the second signal forming unit. The signal forming section for forming each of them and the signal supply section for supplying the signals formed by them to the control unit provided in the vehicle are put into a highly efficient use state, and the control unit Wiring for supplying a signal to the device can be simplified.

[0013]

1 shows an example of an information signal forming / supplying device according to the present invention together with an electronic meter device for a vehicle to which the same is applied. This example is a rotating body placed in a rotating state according to the vehicle speed in the vehicle, for example, based on a detection output signal that is obtained by detecting the rotating state of the output shaft of the transmission and that changes with changes in the vehicle speed. It forms an information signal including a vehicle speed information signal corresponding to the vehicle speed of the vehicle and a traveling state information signal representing the traveling state of the vehicle, and distributes or selectively supplies them to a plurality of control units installed in the vehicle. The disk built-in unit 10, the logic circuit block 28 incorporated in the central control unit (CPU) 104 of the electronic meter control circuit unit 100 in the electronic meter device of the vehicle, and the electronic meter control circuit unit The wiring part 100a and the output terminal 100b in 100 are comprised.

The disc built-in section 10 detects the rotary disc 14 and the detected part provided in relation to the rotary disc 14 and provided on the rotary disc 14, and three detectors 2 for generating detection pulse train signals.
0A, 20B and 20C,
Specifically, for example, it is configured as shown in FIG.

An example of the disc built-in portion 10 shown in FIG.
A case 11 represented by an alternate long and short dash line is provided, and in the case 11, for example, a shaft 13 to which a cable 12 for transmitting the rotation of the output shaft of the transmission is coupled, and a rotation fixed to the shaft 13 are provided. The disk 14 is arranged. A large number of substantially rectangular through holes 16 of the same size are formed in the rotating disk 14 at intervals equal to the width of each of the through holes 16 so as to surround the center of rotation of the rotating disk 14 and form an annular array. Has been done. Each of the through holes 16 is a light transmitting part as a detected part, and a space between two adjacent through holes 16 is a light blocking part 18.

Three photoelectric type detectors 20A, 20B and 20C are arranged in the vicinity of the center of rotation of the rotating disk 14 and are arranged at equal intervals, that is, the rotating disk. The detectors 20A, 20B and 2 are arranged at an angle of 120 ° with respect to the center of rotation of the fourteen.
0C is fixed to the inner surface of the case 11.

Each of the detectors 20A, 20B and 20C has the same structure. For example, the detector 2 shown in FIG.
As shown in 0A, it is formed in a U shape as a whole,
The upper side portion 21a and the lower side portion 21b sandwich the rotating disk 14. A light emitting element 22 such as a light emitting diode is provided inside the upper side portion 21a which is located above the rotating disk 14, and inside the lower side portion 21b which is located below the rotating disk 14. Is provided with a light receiving element 24 such as a phototransistor, and the light emitting element 22 and the light receiving element 24 are opposed to each other via an annular array portion of the through holes 16 provided in the rotating disk 14. .
Therefore, in the state where the light blocking portion 18 is located between the light emitting element 22 and the light receiving element 24, the light from the light emitting element 22 is blocked by the light blocking portion 18 and does not reach the light receiving element 24.
With the through hole 16 positioned between the light emitting element 22 and the light receiving element 24, the light from the light emitting element 22 reaches the light receiving element 24 through the through hole 16.

The light-receiving element 24 generates a signal in response to the arrival of light from the light-emitting element 22, whereby the rotating disc 14 is rotated.
At the time of rotation, the light receiving element 24 generates a detection pulse corresponding to each through hole 16, and therefore the detection pulse train signal corresponding to the arrangement of the through holes 16 is output from the light receiving element 24 as a detection output for the detected portion. Obtained as a signal.

In this case, the annular arrangement of the through holes 16 provided in the rotating disk 14 is 1 with respect to the center of rotation of the rotating disk 14.
Detectors 20 arranged at intervals of 20 °
Each of A, 20B and 20C, when the rotary disc 14 is rotated, is adjacent to two of them, that is, the detectors 20A and 20B, the detectors 20B and 20C, or the detectors 20C and 20A, respectively. 2 obtained from the light receiving element 24 of
So that the two detection pulse train signals are arranged at positions having a mutual phase difference of 2π / 3,
Moreover, it is set so that each detection pulse forming one of these two detection pulse train signals and each detection pulse forming the other thereof have a portion where they overlap each other.

Then, the detectors 20A, 20B and 20C
Is connected to three wires W in a wire harness arranged in the vehicle body, and power is supplied from the battery to the light emitting element 22 in each of the detectors 20A, 20B and 20C through these wires W. Further, power is supplied from the battery to the light receiving element 24 in each of the detectors 20A, 20B and 20C, and the detection pulse train signal is derived from the light receiving element 24. In this way, the detector is formed by the detectors 20A, 20B and 20C which generate the respective detection pulse train signals.

In the disk built-in portion 10 in which the rotating disk 14 is housed in the case 11 and the three detectors 20A, 20B and 20C are fixed to the inner surface of the case 11 as described above. , A detector 20 forming a detector
Each of A, 20B, and 20C is connected to the electronic meter control circuit unit 100.

The electronic meter control circuit section 100 is constructed by using a microcomputer, and for example, the detection signal Sn from the engine speed sensor 106, the detection signal Sf from the fuel gauge 108 and the water temperature sensor 1 are used.
A detection signal such as the detection signal Ss from 10 or signals from various switches (not shown) is supplied.

Then, for example, the detection signal Sn is transmitted through the interface section 111, and the detection signals Sf and S are detected.
s is supplied to the CPU 104 via the A / D converter 113. In the CPU 104, for example, an engine speed signal C _N representing the engine speed, a fuel signal C _F representing the remaining fuel amount, and a water temperature signal C _S representing the engine cooling water temperature are supplied based on the supplied input signals. To be done. Then, the engine speed signal C _N , the fuel signal C _F, and the water temperature signal C obtained from the CPU 104.
_S is supplied to the drive unit 115, and from the drive unit 115, the engine speed signal C _N , the fuel signal C _F, and the water temperature signal C
Display signal C _N based on _S ', C _F' to obtain and C _S ', they, through the output terminal 100c of the electronic meter control circuit unit 100 is supplied to the display unit 120. The display unit 120 can be controlled by the electronic meter control circuit unit 100.
In addition, for example, a light emitting diode is used to perform digital display, and the supplied display signals C _N 'and C
_The engine speed, the remaining fuel amount, and the engine cooling water temperature are displayed according to F'and C _S '.

Further, the CPU 104 has three detectors 20A, 20B and 20 arranged in the above-mentioned disc built-in section 10.
Detection pulse train signals Pa, Pb and P respectively obtained from C
In the logic circuit block 28 which is also supplied with c and constitutes a signal processing unit incorporated in the CPU 104, the vehicle speed corresponding to the rotation speed of the output shaft of the transmission, and thus the vehicle speed, based on the detected pulse train signals Pa, Pb and Pc. Information signal Pn or Cx ′, detection pulse train signal Pa, P
An abnormality detection signal Pe, which is an information signal indicating the abnormality of each of b and Pc, and signals Ma and Mb, which are traveling state information signals that indicate the traveling state of the vehicle such as the forward state, the backward state, and the stopped state, are formed. . Then, the signal Pn or Cx ′ obtained from the logic circuit block 28 is the driving unit 1
15 and the signal Pn or C is output from the drive unit 115.
A display signal C _p ′ based on x ′ is also obtained, which is output through the output terminal 100c of the electronic meter control circuit unit 100.
It is supplied to the display unit 120 and the display unit 120 displays the vehicle speed according to the display signal C _P ′.

Further, the signal Pn or Cx 'obtained from the logic circuit block 28 is the other signal similarly obtained from the logic circuit block 28, that is, the abnormality detection signal Pe,
And, together with the signals Ma and Mb, it is sent out through the wiring part 100a and the output terminal 100b in the electronic meter control circuit part 100 forming the signal supply part, and the signal Pn or Cx ′ is sent to the antilock brake control unit or the like, and the abnormality detection. The signal Pe is used for a lamp control unit or the like for controlling the blinking of the warning lamp, and the signals Ma and Mb are
Electric brake (parking brake) control unit and 4
It is supplied to a WS (four-wheel steering) control unit and the like.

In this way, the CPU 10 of the electronic meter control circuit section 100 installed to display the engine speed, the remaining fuel amount, the engine cooling water temperature, the vehicle speed, etc.
4, which are formed in the detection pulse train signals Pa, Pb and Pc.
On the basis of the signal Pn or Cx ′ according to the vehicle speed, the detection pulse train signals Pa, Pb and Pc indicating the respective abnormality, and the signal Ma indicating the forward, backward and stop states of the vehicle. The logic circuit block 28 forming Mb has a configuration as shown in FIG. 4, for example.

In the concrete configuration example of the logic circuit block 28 shown in FIG. 4, detection pulse forming signals Pa, Pb and Pc obtained from the detectors 20A, 20B and 20C are respectively supplied, and a detection output forming section and an output selection section are provided. An output sending unit 30 including a unit, an abnormality detection unit 40, an abnormality countermeasure signal formation unit 50, and a forward / backward movement determination unit 80 are included. Then, the abnormality detection signal Pe from the abnormality detection unit 40 is sent to the output transmission unit 30.
Also, the abnormality countermeasure signal Cx from the abnormality countermeasure signal forming section 50 is supplied, and the signals Pr and P from the abnormality detecting section 40 are also supplied.
d is supplied to the abnormality countermeasure signal forming unit 50.

As shown in FIG. 5, the output transmitting section 30 is supplied with the detection pulse train signal Pa from the detector 20A and the detection pulse train signal Pb from the detector 20B.
AND gate circuit 31, detection pulse train signal Pb from the detector 20B and detection pulse train signal P from the detector 20C
c, the second AND gate circuit 32, the third AND gate circuit 33 to which the detection pulse train signal Pc from the detector 20C and the detection pulse train signal Pa from the detector 20A are supplied, and each AND gate. The detection output forming unit 30A is composed of an OR gate circuit 34 to which the signals P ₁ , P ₂ and P ₃ obtained from the gate circuits 31, 32 and 33 are supplied, and the signal Pn obtained from the OR gate circuit 34 is a rotation detection output. Has been formed. Further, the abnormality countermeasure signal Cx is supplied from the abnormality countermeasure signal forming unit 50,
A frequency multiplication circuit 36 for multiplying the input signal frequency by 3, a fixed contact 35a to which a signal Pn obtained from the OR gate circuit 34 of the detection output forming unit 30A is supplied, and an abnormality countermeasure signal C
a fixed contact 35b to which a signal Cx 'obtained by multiplying x by 3 by a frequency multiplication circuit 36 is supplied;
An output selection unit 30B is formed which is controlled by the abnormality detection signal Pe obtained from the abnormality detection unit 40 and includes a switch circuit 35 having a movable contact 35c that is selectively connected to one of the fixed contacts 35a and 35b.

In this way, the output sending unit 30 performs the predetermined processing on the detection pulse train signals Pa, Pb and Pc obtained from the detectors 20A, 20B and 20C, respectively, and further outputs them from the abnormality countermeasure signal forming unit 50. A signal forming means for taking in the abnormality countermeasure signal Cx and forming a signal Pn or Cx ′ which is a vehicle speed information signal corresponding to the vehicle speed of the vehicle is configured.

The abnormality detecting section 40, as shown in FIG.
An OR gate circuit 41 and an AND gate circuit 42 to which the detection pulse train signals Pa, Pb and Pc from the detectors 20A, 20B and 20C are respectively supplied, and an OR gate circuit 4
1 is directly supplied with the signal Pr, and the signal Pd obtained from the AND gate circuit 42 is composed of the AND gate circuit 44 supplied through the inverter 43, and the output signal of the AND gate circuit 44 is the abnormality detection signal. P
e.

In the abnormality countermeasure signal forming section 50, as shown in FIG.
, The detected pulse train signals Pa, Pb and Pc
Are supplied to the set terminals S, respectively, and the abnormality detection section
The signal Pr obtained from the OR gate circuit 41 of 40
Signal Pr 'obtained by level inversion by the barter 57
Is supplied to each reset terminal R
51, 52 and 53 and these RS flip flocks
The signals obtained at the output terminals Q of the
No. S₁, S₂And S₃Are delay circuits 51a, 52a and 5
Signal obtained by delaying a minute time by 3a
S₁’, S₂’And S ₃'Is supplied to the data terminal D, respectively.
At the same time, the signal Pr is supplied to each clock terminal C.
D-flip-flops 54, 55 and 56 and detection
The pulse train signals Pa, Pb and Pc are respectively fed to the inverter 6
Signal obtained by level inversion by 7, 68 and 69
Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
And the AND gate circuit 42 of the abnormality detection unit 40.
Is supplied to each reset terminal R.
RS flip-flops 61, 62 and 63 and these
Output of each of the RS flip-flops 61, 62 and 63
The signal S obtained at the force terminal Q₇, S₈And S₉Is a delay circuit
61a, 62a and 63a delay a minute time
Signal S obtained by₇’, S₈’And S₉'Is data
The signal Pd is supplied to the terminal D, and
D-flip-flops 64 and 65 supplied to the child C and
And 66, and D-flip-flops 54 and 6
Signal S obtained from each of the 4_FourAnd S_TenOr gate times
D-flip-flops 55 and 65, respectively, on path 58
Signal S obtained from_FiveAnd S₁₁Or gate circuit 59
And D-flip-flops 56 and 66, respectively.
Signal S obtained from₆And S₁₂Or gate circuit 60
, Respectively.

Further, the signal S from the OR gate circuit 58
₄ or S ₁₀ is directly supplied to the AND gate circuit 71, level-inverted by the inverter 77 and supplied to the AND gate circuit 72, and the signal S ₅ or S ₁₁ from the OR gate circuit 59 is directly supplied to the AND gate circuit 72. In addition, the level is inverted by the inverter 78 and supplied to the AND gate circuit 73, and the signal S ₆ or S ₁₂ from the OR gate circuit 60 is directly supplied to the AND gate circuit 73, and the level is inverted by the inverter 79 to perform the AND gate operation. It is supplied to the circuit 71. Further, the AND gate circuits 71, 72 and 73 have
The detection pulse train signals Pa, Pb and Pc are supplied respectively.

The signals C ₁ , C ₂ and C ₃ obtained from the AND gate circuits 71, 72 and 73, respectively, are supplied to the OR gate circuit 76, and the output signal of the OR gate circuit 76 is used as the abnormality countermeasure signal Cx.

Under the combination of the disk built-in section 10 and the logic circuit block 28 configured as described above,
When the vehicle is traveling, the rotating disk 14 is rotated according to the vehicle speed, and when all the detectors 20A, 20B and 20C are operating normally, the detectors 20A, 20B and 20C respectively , Period T ₀ before time t ₁ in A, B and C of FIG. 7, and A, B of FIG.
As shown at time t ₄ previous period T ₄ in the B and C, sequentially 2 [pi / 3, i.e., the detection pulse train signal Pa which is assumed to have a phase difference of each 120 °, Pb and Pc is obtained. These detection pulse train signals Pa and Pb
And Pc are two of them having a mutual phase difference of 120 °, that is, the detection pulse train signals Pa and Pb, Pb.
And Pc, or each detection pulse forming one of Pc and Pa and each detection pulse forming the other,
It is supposed to have portions that overlap each other, that is, portions that take a high level at the same time.

Such detection pulse train signals Pa, Pb and P
c indicates the detection of the output sending unit 30 in the above-described manner.
The first, second and third sensors in the output / output forming unit 30A.
It is supplied to the gate circuits 31, 32 and 33. Soshi
From the first AND gate circuit 31.
Each detection pulse forming the signal Pa and the detection pulse train signal Pb
Corresponds to the overlapping part with each detection pulse forming
Signal P formed by a train of pulses₁Is obtained
2 from the AND gate circuit 32, the detection pulse train signal Pb
Forming each detection pulse and detection pulse train signal Pc forming
Corresponding to the overlapping part of each detected pulse
The signal P formed by the row of lus₂And further,
From the third AND gate circuit 33, the detection pulse train signal P
Shape each detection pulse forming c and the detection pulse train signal Pa
Corresponds to the overlapping part with each detection pulse
Signal P formed by a train of pulses₃Is obtained. this
Signal P₁, P₂And P₃Is supplied to the OR gate circuit 34
From the OR gate circuit 34.₁, P₂as well as
P₃The period in D of FIG. 7 obtained by combining
T ₀, And the period T in D of FIG._FourShown in
A signal Pn which is a pulse train signal as described above is obtained. This
The pulse train signal forming the signal Pn of
Frequency of 3 times each of the numbers Pa, Pb and Pc
It has, and this is used as the rotation detection output.

Therefore, as compared with the case where the detection pulse train signal Pa, Pb or Pc obtained according to the annular arrangement of the through holes 16 provided in the rotary disc 14 is directly used as the rotation detection output by this rotation detection output. As a result, rotation detection is performed with significantly increased detection accuracy.

As described above, each of the detection pulse train signals Pa, Pb and Pc is normally obtained from the detection output forming section 30A, and the signal Pn having a frequency three times that frequency is obtained.
8 is obtained, the OR gate circuit 41 and the AND gate circuit 42 in the abnormality detection unit 40 of the logic circuit block 28 also have the periods T ₀ in A, B and C of FIG. Of the detection pulse train signals Pa and P shown in the period T ₄ in A, B and C of
b and Pc are supplied. As a result, the OR gate circuit 4
1 and the AND gate circuit 42 output the signal Pr and the low level which are high level LH as shown in the periods T ₀ in E and F of FIG. 7 and the period T ₄ in E and F of FIG. 8 respectively. A signal Pd taking LL is obtained.
The signal Pr having the high level LH is unchanged, and the signal Pd having the low level LL is converted into a signal having the high level by the inverter 43 and supplied to the AND gate circuit 44. The abnormality detection signal P having the high level LH as shown in the period T ₀ in G of 7 and the period T ₄ in G of FIG.
e is obtained.

In this way, when all of the detection pulse train signals Pa, Pb and Pc from the detectors 20A, 20B and 20C are properly obtained, the OR gate circuit 41 and the AND gate in the abnormality detecting section 40 are provided. The signals Pr and Pd obtained from the circuit 42 have a high level LH and a low level LL, respectively, and as a result, the abnormality detection signal Pe has a high level LH.

The abnormality detection signal Pe having the high level LH is supplied to the control end of the switch circuit 35 in the output selection section 30B of the output transmission section 30 and a warning is issued from the output terminal 100b of the electronic meter control circuit section 100. It is supplied to the lamp control unit that controls the blinking of the lamp,
In the lamp control unit, the abnormality detection signal Pe has a high level L
When taking H, the warning lamp is kept in the off state.

As described above, the detection pulse train signals Pa, P
When each of b and Pc is normally obtained, the RS flip-flop 5
The set terminals S of 1, 52 and 53 are connected to the set terminals S of FIG.
And the period T ₀ in C, and, A in FIG. 8, the detection pulse train signal P shown in the period T ₄ in the B and C
a, Pb and Pc are respectively supplied, and the set terminals S of the RS flip-flops 61, 62 and 63 are obtained from the inverters 67, 68 and 69 based on the above-mentioned detection pulse train signals Pa, Pb and Pc. Signal P
a ', Pb' and Pc 'are provided.

At this time, the RS flip-flops 51,
Each of the reset terminals R of 52 and 53 has an abnormality detecting section.
The signal Pr which takes the high level LH from 40 is the inverter 5
Inverted to the low level by 7 and supplied,
Output terminals Q of the respective flip-flops 51, 52 and 53?
The signal S that continuously takes a high level₁, S₂And S₃But
Obtained, these signals S₁, S₂And S₃Are delay circuits
51a, 52a and 53a through H, I and
Period T in J₀Continuously, as shown in
Signal S taking high level LH₁’, S₂’And S₃'age
D-flip-flops 54, 55 and 56 respectively
It is supplied to the data terminal D. D-flip flop 5
The clock terminals C of 4, 55 and 56 have high levels.
The signal Pr that takes the level LH is continuously low due to the level inversion.
Supplied as a bell taker, D-Flip Float
7 to the output terminals Q of the amplifiers 54, 55 and 56, respectively.
Period T in K, L and M₀As shown in
Signal S of low level LL _Four, S_FiveAnd S₆Got
These are OR gate circuits 58, 59 and 60, respectively.
Is supplied to one of the input terminals.

Further, at this time, the RS flip-flops in which the signals Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
The reset terminal R of each of the flops 61, 62, and 63 is continuously low as shown in the period T ₀ in F of FIG. 7 and the period T ₄ in F of FIG. 8 obtained from the abnormality detection unit 40. The signal Pd having the level LL is supplied to the output terminals Q of the RS flip-flops 61, 62 and 63, and the signal S ₇ having the high level continuously.
S ₈ and S ₉ are obtained, these signals S _7, S ₈ and S ₉
There each delay circuit 61a, through 62a and 63a, signal S ₇ take H in Figure 8, the as shown in the period T ₄ in the I and J, a continuous high level LH ', S _8'
And S ₉ ′ are supplied to the respective data terminals D of the D-flip-flops 64, 65 and 66. A signal Pd having a low level LL is continuously supplied to the clock terminals C of the D-flip-flops 64, 65 and 66, and the signals Pd are output to the output terminals Q of the D-flip-flops 64, 65 and 66, respectively. , Period T ₄ in K, L and M of FIG.
Signals S ₁₀ , S ₁₁ and S ₁₂ having a low level LL are obtained as shown in (4) and are supplied to the other input terminals of the OR gate circuits 58, 59 and 60, respectively.

For this reason, the output signals of the OR gate circuits 58, 59 and 60 all take a low level, and therefore the AND gate circuits 71, 72 and 73.
From each of the signals C ₁ , C ₂ and C having a low level LL as shown in the period T ₀ in N, O and P of FIG. 7 and the period T ₄ in N, O and P of FIG.
₃ is obtained, and the abnormality countermeasure signal Cx obtained from the OR gate circuit 76 continuously takes the low level.

The abnormality countermeasure signal Cx having the low level is
It is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30.

In this case, since the abnormality detection signal Pe having the high level LH obtained from the abnormality detection unit 40 is supplied to the control end of the switch circuit 35 of the output transmission unit 30, the movable contact of the switch circuit 35 is supplied. 35c is a fixed contact 35
A signal Pn, which is connected to a and has a frequency three times that of each of the detection pulse train signals Pa, Pb, and Pc, which is obtained from the detection output forming unit 30A, is sent from the movable contact 35c of the switch circuit 35 as a rotation detection output. It

The signal P sent from the output sending unit 30
n is supplied to the driving unit 115 of the electronic meter control circuit unit 100, and the output terminal 100 of the electronic meter control circuit unit 100.
It is used for displaying the vehicle speed on the display unit 120 through c and the wiring unit 100 of the electronic meter control circuit unit 100.
It is distributed and supplied to a plurality of control units through a and the output terminal 100b. As a result, when appropriate detection pulse train signals Pa, Pb and Pc are respectively obtained from the detectors 20A, 20B and 20C arranged in the disc built-in section 10,
Each control unit controls the rotational speed of the transmission output shaft, and
Highly accurate control according to the vehicle speed will be performed.

On the other hand, for example, in the state where the detection pulse train signal Pa cannot be properly obtained due to an accident such as a disconnection at the detector 20A itself or its output side,
The respective portions of the signal in A~P 7, following the period T ₀ of the above, the as shown in the period T ₁ of the from time t ₁ to t _2. That is, the detection pulse train signals Pb and Pc from the detectors 20B and 20C are normally obtained as shown in the period T ₁ in B and C of FIG. 7, but the detection pulse train signal Pa from the detector 20A is shown in FIG. As shown in the period T ₁ in A of FIG. As a result, in the detection output forming unit 30A of the output sending unit 30, the signals P ₁ and P ₃ obtained from the AND gate circuits 31 and 33 continuously take the low level, and only the signal P ₂ obtained from the AND gate circuit 32 is obtained. Becomes a pulse train signal synchronized with the detected pulse train signal Pc. As a result, the output signal Pn from the OR gate circuit 34 becomes the same as the output signal P _{2 from the} AND gate circuit 32, as shown in the period T ₁ in D of FIG.

At this time, the signal Pr from the OR gate circuit 41 in the abnormality detecting section 40 is synchronized with the falling portion of the detection pulse train signal Pc as shown in the period T ₁ in E of FIG. And the signal Pd from the AND gate circuit 42.
As shown in the period T ₁ in F of FIG.
It takes the low level LL. As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 is G
As shown in the period T ₁ in, the same signal Pr from the OR gate circuit 41, the detection pulse train signal Pc
It has a low level portion in synchronization with the trailing edge portion.

The abnormality detection signal Pe which takes a low level periodically is supplied to the control end of the switch circuit 35 in the output selection section 30B of the output transmission section 30 and also to the lamp control unit for controlling the blinking of the warning lamp. To be done.
When the abnormality detection signal Pe takes a low level periodically, the lamp control unit turns on the warning lamp and warns that any of the detection pulse train signals Pa, Pb and Pc has become abnormal.

As described above, in the state where the detection pulse train signal Pa becomes abnormal and continuously takes the low level, the abnormality countermeasure signal forming section 50 causes the RS flip
At the respective set terminals S of the flops 51, 52 and 53, the detection pulse train signal Pa having a low level and the normal detection pulse train signals Pb and Pc as shown in the period T ₁ in A, B and C of FIG. Signals Pa ′, Pb which are supplied to the respective set terminals S of the RS flip-flops 61, 62 and 63 and whose detection pulse train signals Pa, Pb and Pc are level-inverted by the inverters 67, 68 and 69. 'And Pc' are provided.

At this time, the RS flip-flops 51,
Each of the reset terminals R of 52 and 53 has an abnormality detecting section.
Period T in FIG. 7E from 40₁Shown in
The detection pulse obtained by inverting the level of the signal Pr
The high-level part is synchronized with the falling part of the column signal Pc.
A signal Pr 'having is supplied. And RS flip
From the respective output terminals Q of the flops 51, 52 and 53
Signal S obtained₁, S ₂And S₃Are delay circuits 51, respectively.
a, 52a and 53a, H, I of FIG.
And period T in J₁Signal S as shown in
₁’, S₂’And S₃'Is the D-flip flop 5
It is supplied to the respective data terminals D of 4, 55 and 56.
D-flip-flops 54, 55 and 56 respectively
The lock terminal C has a period T in E of FIG.₁At
The signal Pr as shown is level-inverted and supplied,
The output of each of the D-flip-flops 54, 55 and 56.
To the input terminal Q, the period T in K, L and M of FIG.₁To
Signal S as shown _Four, S_FiveAnd S₆Is obtained
These are the OR gate circuits 58, 59 and 60, respectively.
It is supplied to one input terminal.

Further, at this time, the RS flip-flops in which the signals Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
The reset terminal R of each of the flops 61, 62 and 63 is continuously low level LL, as shown in the period T ₁ in F of FIG.
Is supplied to the respective output terminals Q of the RS flip-flops 61, 62 and 63 to obtain signals S ₇ , S ₈ and S ₉ which continuously have a high level, and
The signal Pd having the low level LL is also supplied to the clock terminals C of the D-flip-flops 64, 65 and 66, and the signals Pd of the D-flip-flops 64, 65 and 66 are continuously supplied to the respective output terminals Q. The signals S ₁₀ , S ₁₁ and S ₁₂ having a low level LL are obtained, and these signals are supplied to the other input terminals of the OR gate circuits 58, 59 and 60, respectively.

Therefore, the OR gate circuits 58, 59 and 60 directly obtain the signals S ₄ , S ₅ and S ₆ as shown in the period T ₁ in K, L and M of FIG. Then, the AND gate circuit 71 outputs the signal S as shown in the period T ₁ in K of FIG.
₄ , a signal obtained by level-inverting the signal S ₆ as shown in the period T ₁ in M of FIG. 7 by the inverter 79, and the detection pulse train signal P that continuously takes the low level.
a and the signal C ₁ obtained from the AND gate circuit 71 has a low level LL as shown in the period T ₁ in N of FIG. Further, in the AND gate circuit 72, the signal S ₅ as shown in the period T ₁ in L of FIG. 7 and the signal S ₄ as shown in the period T ₁ in K of FIG. The signal thus obtained and the normal detection pulse train signal Pb are supplied, and the normal detection pulse train signal Pb is obtained from the AND gate circuit 72 as the signal C ₂ as shown in the period T ₁ in O of FIG. To be Further, in the AND gate circuit 73, the signal S ₆ as shown in the period T ₁ in M of FIG. 7 and the signal S ₅ as shown in the period T ₁ in L of FIG. And a normal detection pulse train signal Pc are supplied to the AND gate circuit 7
The signal C ₃ obtained from ₃ is the period T _{1 in} P of FIG.
The low level LL is taken as shown in FIG.

Accordingly, at this time, the OR gate circuit 76 outputs the abnormality countermeasure signal Cx as the AND gate circuit 72.
A signal C ₂ obtained from the above, that is, a normal detection pulse train signal Pb is obtained. The detection pulse train signal Pb as the abnormality countermeasure signal Cx is output by the output selection unit 30B of the output transmission unit 30.
Is supplied to the fixed frequency contact circuit 35b of the switch circuit 35 as a signal Cx ′ whose frequency is tripled.

In this case, the control terminal of the switch circuit 35 of the output transmission unit 30 is supplied with the abnormality detection signal Pe which is periodically low level and which is obtained from the abnormality detection unit 40, and the switch circuit 35 has such a configuration. When the abnormality detection signal Pe which takes a low level periodically is supplied, the movable contact 35c is connected to the fixed contact 35b. As a result, the detection pulse train signal Pb from the frequency multiplication circuit 36 is output from the movable contact 35c of the switch circuit 35.
A signal Cx ′ obtained by multiplying the frequency of 3 by 3 is sent as a detection output instead of the signal Pn from the detection output forming unit 30A.

The signal C sent from the output sending unit 30
x ′ is an electronic meter control circuit unit 100 instead of the signal Pn.
Is supplied to the drive unit 115 and each control unit. As a result, when the detection pulse train signal Pa from the detector 20A arranged in the disc built-in unit 10 becomes abnormal and becomes a low level continuously, the frequency of the normal detection pulse train signal Pb is The signal Cx ′ obtained by being multiplied by 3 is automatically set to the state of being the emergency rotation detection output to each control unit.

Further, in the state where the detection pulse train signal Pb or Pc cannot be properly obtained due to an accident such as a disconnection at the detector 20B or 20C itself or its output side, the signals of the respective parts are indicated by A to P in FIG. , the period T ₂ of the from the time t ₂ subsequent to the period T ₁ of the above to t _3, or becomes a as shown at time t ₃ after the period T ₃ following the period T _2, the detection pulse train from the detector 20A and 20C The signals Pa and Pc are properly obtained as shown in the period T ₂ in A and C of FIG. 7, but the detection pulse train signal Pb from the detector 20B continues as shown in the period T ₂ in B of FIG. Becomes low level, or detectors 20A and 20B
The detection pulse train signals Pa and Pb from P are obtained properly as shown in the period T ₃ in A and B of FIG. 7, but the detection pulse train signal Pc from the detector 20C is obtained in the period T ₃ in C of FIG. As shown in the figure, the level becomes continuously low, which is the same as the state where the detection pulse train signal Pa cannot be properly obtained due to the disconnection or the like at the detector 20A itself or the output side thereof. .

That is, the signal Pn of the OR gate circuit 34 of the detection output forming section 30A is the signal Pn obtained from the AND gate circuit 33 as shown in the period T ₂ in D of FIG.
_The same as ₃ , or the period T _{3 in} D of FIG.
7, the signal becomes the same as the signal P ₁ obtained from the AND gate circuit 31, and at this time, the abnormality detection signal Pe obtained from the abnormality detection unit 40 is G in FIG.
As shown in period T ₂ or T ₃ in
It is the same as the signal Pr obtained from the OR gate circuit 41 and takes a low level periodically. The abnormality detection signal Pe which takes a low level periodically is also supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and also to the lamp control unit that controls the blinking of the warning lamp. The lamp control unit turns on the warning lamp.

Further, the OR gate circuits 58, 5 of the abnormality countermeasure signal forming section 50 are operated under the same operation as in the case where the detection pulse train signal Pa continuously takes the low level.
From 9 and 60, the period T in K, L and M of FIG.
₂ or signals S ₄ , S _{5 as} shown at T ₃ .
And S ₆ are obtained as they are, and as a result, from the OR gate circuit 76, as the abnormality countermeasure signal Cx, the signal C ₃ obtained from the AND gate circuit 73, that is, the normal detection pulse train signal Pc or the AND gate circuit 71 is obtained. The obtained signal C ₁ , that is, the normal detection pulse train signal Pa is obtained. The detection pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and the fixed contact 35b of the switch circuit 35 as the signal Cx ′ whose frequency is tripled. Is supplied to.

Also in this case, the output sending unit 30
Since the abnormality detection signal Pe which is periodically low level and is obtained from the abnormality detection unit 40 is supplied to the control end of the switch circuit 35, the movable contact 35c of the switch circuit 35 is connected to the fixed contact 35b, From the contact point 35c, the detection pulse train signal Pc or P from the frequency multiplication circuit 36
A signal Cx ′ obtained by multiplying the frequency of a by 3 is sent as a detection output instead of the signal Pn from the detection output forming unit 30A, and the driving unit 11 of the electronic meter control circuit unit 100.
5 and the emergency rotation detection output for each control unit.

On the other hand, for example, when a short circuit accident occurs in the detector 20A and the detection pulse train signal Pa cannot be obtained properly, the signals of the respective parts are as shown in A to P in FIG.
A period T from time t ₄ to time t ₅ following the period T ₄ described above
_As shown in ₅ . That is, the detection pulse train signals Pb and Pc from the detectors 20B and 20C are as shown in FIG.
Although normally obtained as shown in the period T ₅ in B and C, the detection pulse train signal P from the detector 20A is obtained.
As shown in the period T ₅ in A of FIG. 8, a becomes continuously high level. As a result, in the detection output forming unit 30A of the output sending unit 30, the signal P obtained from the AND gate circuits 31 and 33 is generated.
₁ and P ₃ continuously take the high level, and only the signal P ₂ obtained from the AND gate circuit 32 is the detection pulse train signal P.
It becomes a pulse train signal synchronized with c. As a result, the signal Pn from the OR gate circuit 34 remains in the period T in D of FIG.
_As shown in ₅ , the detection pulse train signal Pc has a low level part in synchronization with the falling part.

Then, at this time, the signal Pr from the OR gate circuit 41 in the abnormality detecting section 40 becomes the high level LH as shown in the period T ₅ in E of FIG. 8, and from the AND gate circuit 42. Signal Pd has a high level portion in synchronization with the rising portion of the detection pulse train signal Pc, as shown in period T ₅ in F of FIG. As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 is
As shown in the period T _{5 in} , the low level part is provided in synchronization with the rising part of the detection pulse train signal Pc, which corresponds to the signal Pd from the OR gate circuit 42 whose level is inverted.

The abnormality detection signal Pe which takes a low level periodically is also supplied to the control end of the switch circuit 35 in the output selection section 30B of the output transmission section 30 and also to the lamp control unit for controlling the blinking of the warning lamp. Supplied,
The lamp control unit turns on the warning lamp.

As described above, in the state in which the detection pulse train signal Pa continuously takes the high level, the RS flip-flops 51, 5 in the abnormality countermeasure signal forming section 50.
The detection pulse train signal Pa having a high level and the normal detection pulse train signals Pb and Pc are supplied to the respective set terminals S of 2 and 53, and the respective set terminals S of the RS flip-flops 61, 62 and 63 are supplied. In addition, the detection pulse train signals Pa, Pb, and Pc described above have the inverter 6
Signal P obtained by level inversion by 7, 68 and 69
a ', Pb' and Pc 'are provided.

At this time, the RS flip-flops 51,
A signal Pr ′ having a low level, which is obtained by inverting the level of the signal Pr as shown in the period T ₅ in E of FIG. 8 from the abnormality detection unit 40, is supplied to the reset terminals R of 52 and 53, respectively. As a result, the signals S ₁ , S ₂ and S ₃ that continuously have a high level are obtained at the output terminals Q of the RS flip-flops 51, 52 and 53, respectively, and the D-flip-flop 54 , 55 and 56, respectively, are also supplied with the low level signal Pr ′, and the D-flip-flops 54, 55 and 56 are supplied.
The signals S ₄ , S ₅ and S ₆ that continuously take the low level LL are obtained at the respective output terminals Q of the two, and these signals are supplied to one input terminals of the OR gate circuits 58, 59 and 60, respectively. .

Further, at this time, the signals RS ', Pb' and Pc 'are supplied to the set terminal S respectively.
The reset terminal R of each of the flops 61, 62 and 63 has a detection pulse train signal Pc obtained from the abnormality detection unit 40 as shown in a period T ₅ in F of FIG.
Signal P having a high level portion in synchronization with the rising portion of
d is supplied. And RS flip-flop 6
The signal S obtained at the respective output terminals Q of 1, 62 and 63
₇ , S ₈ and S ₉ are delay circuits 61a, 62a and 6 respectively.
The signals S ₇ ′, S ₈ ′ and S ₉ ′ as shown in time period T ₅ in H, I and J of FIG.
Are supplied to the respective data terminals D. A signal Pd having a high level portion is supplied to the clock terminals C of the D-flip-flops 64, 65 and 66 in synchronization with the rising portion of the detection pulse train signal Pc, and the D-flip-flops 64, 65 are provided. And 66 at their respective output terminals Q, the signals S ₁₀ , S ₁₁ and S ₁₂ are obtained as shown in the period T ₅ in K, L and M of FIG. 8, which are respectively OR gate circuits 58, 59 and. It is supplied to the other input terminal of 60.

Therefore, the OR gate circuits 58, 59 and
From 60, the period T in K, L and M of FIG._FiveTo
Signal S as shown_Ten, S₁₁And S₁₂As it is
can get. The AND gate circuit 71 has
Period T in K_FiveSignal S as shown in
_TenAnd the period T in M of FIG._FiveAs shown in
Signal S₁₂Is level-inverted by the inverter 79
Signal and the detection pulse train signal P that continuously takes a high level
a and the signal obtained from the AND gate circuit 71.
Issue C₁Is the period T in N of FIG._FiveShown in
Such a low level LL is obtained. Also, Andge
The gate circuit 72 has a period T in L of FIG. _FiveAt
Signal S as shown₁₁And the period T in K of FIG._Five
Signal S as shown in_TenWith inverter 77
Bell-inverted signal and normal detection pulse train signal
No. Pb is supplied, and the AND gate circuit 72 sends a signal.
Issue C₂As the period T in O of FIG._FiveShown in
As described above, the normal detection pulse train signal Pb is obtained. It
In addition, the AND gate circuit 73 has a period in M of FIG.
Interval T_FiveSignal S as shown in₁₂And L in FIG.
Period T_FiveSignal S as shown in₁₁Is in
The signal obtained by level inversion by the barter 78 and normal
The detection pulse train signal Pc is supplied to the AND gate circuit.
Signal C obtained from 73₃Is the period T in P of FIG.
_FiveAs shown in, the low level LL should not be taken.
You.

Therefore, at this time, the OR gate circuit 76 outputs the abnormality countermeasure signal Cx as the AND gate circuit 72.
A signal C ₂ obtained from the above, that is, a normal detection pulse train signal Pb is obtained, is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and the switch circuit is provided as a signal Cx ′ whose frequency is tripled. 35 fixed contacts 3
5b.

In this case, since the abnormality detection signal Pe, which is periodically low level and is obtained from the abnormality detection unit 40, is supplied to the control end of the switch circuit 35 of the output transmission unit 30, the switch circuit 35. The movable contact 35c is connected to the fixed contact 35b. Thereby, the switch circuit 3
From the movable contact 35c of No. 5, from the frequency multiplication circuit 36,
A signal Cx ′ obtained by multiplying the frequency of the detection pulse train signal Pb by 3 is sent as a detection output instead of the signal Pn of the detection output forming unit 30A.

Therefore, even when the detection pulse train signal Pa from the detector 20A arranged in the disc built-in portion 10 becomes abnormal and continuously takes a high level, the normal detection pulse train signal Pb is The signal Cx ′ obtained by multiplying the frequency by 3 is automatically taken as the emergency rotation detection output for each control unit.

In the state where the detector 20B or 20C is short-circuited and the detection pulse train signal Pb or Pc cannot be properly obtained, the signals of the respective parts are as shown in FIG.
Of the A-P, the period T ₆ from the time t ₅ following the period T ₅ above to t _6, or, when following the period T ₆ t
_As shown in the period T _{7 from 6} onward, the detection pulse train signals Pa and Pc from the detectors 20A and 20C are obtained.
Is properly obtained as shown in the period T ₆ in A and C of FIG. 8, but the detection pulse train signal Pb from the detector 20B is continuously at the high level as shown in the period T ₆ in B of FIG. Or the detection pulse train signal P from the detectors 20A and 20B
Although a and Pb are properly obtained as shown in the period T ₇ in A and B of FIG. 8, the detection pulse train signal Pc from the detector 20C is continuously obtained as shown in the period T ₇ in C of FIG. This is the same as the state in which the detection pulse train signal Pa cannot be properly obtained due to a short circuit accident in the detector 20A described above.

That is, the signal Pn of the OR gate circuit 34 of the detection output forming section 30A has a low level portion in synchronization with the falling portion of the detection pulse train signal Pa, as shown in the period T ₆ in D of FIG. , Or D in FIG.
As shown in the period T ₇ in the detection pulse train signal P
A low level portion is provided in synchronism with the trailing edge portion in b, and at this time, the abnormality detection signal Pe obtained from the abnormality detection unit 40 is shown in the period T ₆ or T ₇ in G of FIG. Or gate circuit 42
The signal Pd obtained from the above is periodically low level, which corresponds to the level-inverted signal. The abnormality detection signal Pe which takes a low level periodically is also supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and also to the lamp control unit that controls the blinking of the warning lamp. The lamp control unit turns on the warning lamp.

Further, the OR gate circuits 58, 5 of the abnormality countermeasure signal forming section 50 are operated under the same operation as in the case where the detection pulse train signal Pa becomes continuously high level.
From 9 and 60, the period T in K, L and M of FIG.
₆ or signals S ₁₀ , S _{11 as} indicated at T ₇ .
And S ₁₂ are obtained as they are, and as a result, from the OR gate circuit 76, as the abnormality countermeasure signal Cx, the signal C ₃ obtained from the AND gate circuit 73, that is, the normal detection pulse train signal Pc or the AND gate circuit 71 is obtained. The obtained signal C ₁ , that is, the normal detection pulse train signal Pa is obtained. The detection pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and the fixed contact 35b of the switch circuit 35 as the signal Cx ′ whose frequency is tripled. Is supplied to.

Also in this case, the abnormality detection signal Pe, which is obtained from the abnormality detection unit 40 and has a periodically low level, is supplied to the control terminal of the switch circuit 35 of the output transmission unit 30. The movable contact 35c of 35 is connected to the fixed contact 35b, and from the movable contact 35c, the detection pulse train signal Pc or Pa from the frequency multiplication circuit 36 is transmitted.
The signal Cx ′ obtained by multiplying the frequency of 3 by 3 is transmitted as a detection output in place of the signal Pn from the detection output forming unit 30A, and is used as an emergency rotation detection output for each control unit.

As described above, the logic circuit block 28
The output sending unit 30, the abnormality detecting unit 40, and the abnormality countermeasure signal forming unit 50 provided in the above-mentioned unit can provide a rotation detection output capable of improving detection accuracy, and further, of the detection pulse train signals Pa, Pb, and Pc. If any of the above becomes abnormal, appropriate measures are automatically taken by effectively using the other detected pulse train signals that have not caused abnormalities. Circuit block 2
A forward / backward traveling determination unit 80 provided in 8 obtains a traveling state information signal representing a traveling state including a forward traveling state, a backward traveling state, and a stopped state of the vehicle.

That is, the forward / backward movement determining section 80, as shown in FIG. 9, includes six D-flip-flops 81, 82, 8
3, 84, 85 and 86 and 6 AND gate circuits 9
1, 92, 93, 94, 95 and 96 and two OR gate circuits 97 and 98. Then, the detection pulse train signal Pa becomes the D-flip flops 81 and 82.
Directly to the data terminal D of the D-flip-flop 85 and the clock terminal C of the D-flip-flop 85.
Is supplied to the clock terminal C of the D-flip-flops 83 and 8 after being level-inverted and supplied.
4 directly to the data terminal D and the clock terminal C of the D-flip-flop 81, and to the D-flip-flop 8
The level-inverted signal is supplied to the second clock terminal C, and the detection pulse train signal Pc is further supplied directly to the data terminal D of the D-flip-flops 85 and 86 and the clock terminal C of the D-flip-flop 83. D-flip
The level is inverted and supplied to the clock terminal C of the flop 84.

D-flip-flops 81, 83 and 8
The signals Fa, Fb and F obtained at the respective output terminals Q of
c is connected to one input terminal of each of AND gate circuits 91, 93 and 95, and D-flip flops 82, 8
The signals Ra and R obtained at the output terminals Q of 4 and 86 respectively.
b and Rc are supplied to one input terminal of each of the AND gate circuits 92, 94 and 96, and a signal Fa ′ obtained at the inverting output terminal −Q of each of the D-flip flops 81, 83 and 85, Fb 'and Fc' are connected to the other input terminals of the AND gate circuits 92, 94 and 96, respectively, and D-flip-flops 82, 84 and 86.
Signals Ra ', R obtained at the respective inverting output terminals -Q of
b'and Rc 'are AND gate circuits 91, 93 and 95
Of the output signals F ₁ and F ₁ supplied to the other input terminals of the AND gate circuits 91, 93 and 95, respectively.
₂ and F ₃ are output signals R obtained from the OR gate circuit 97 and the AND gate circuits 92, 94 and 96, respectively.
₁ , R ₂ and R ₃ are supplied to the OR gate circuit 98.

When the vehicle is moving forward, the forward / rearward traveling determination section 80 having the above-described configuration has the period T ₀ in A, B and C of FIG. 7 and the period T in A, B and C of FIG. _The detection pulse train signals Pa, Pb, and Pc, which are sequentially set to have a phase difference of 2π / 3 as shown in ₄ , are supplied.

At this time, the D-flip flops 81,
The signal F obtained from the respective output terminals Q of 83 and 85
a, Fb and Fc, and D-flip flop 8
Signals Ra ', Rb' and Rc 'obtained from the respective inverting output terminals -Q of 2, 84 and 86 are at high levels, and are high levels from the AND gate circuits 91, 93 and 95, respectively. F ₁ , F ₂ and F ₃ are obtained.
On the other hand, Fa ′, Fb ′ and Fc ′ obtained from the inverting output terminals −Q of the D-flip flops 81, 83 and 85, and the output terminals Q of the D-flip flops 82, 84 and 86, respectively. Ra, Rb and R obtained from
c becomes a low level, and the AND gate circuit 9
2,94 and 96 give low levels of R ₁ , R ₂ and R _{3, respectively} . As a result, the OR gate circuit 97 obtains the signal Ma that continuously attains the high level, and the OR gate circuit 98 obtains the signal Mb that continuously attains the low level.

On the other hand, when the vehicle moves backward,
The rotating disk 14 rotates in the direction opposite to that in forward movement, and the detection pulse train signals Pa, Pb, and Pc have a mutual phase advance / retard relationship opposite to that in forward movement. Therefore, the forward / backward movement determination unit 80
, The detection pulse train signals Pa, Pb, and Pc having a phase delay of 2π / 3 each are sequentially supplied in the order of Pc → Pb → Pa.

Therefore, the D-flip-flop 81,
The signal F obtained from the respective output terminals Q of 83 and 85
a, Fb and Fc, and D-flip flop 8
Signals Ra ', Rb' and Rc 'obtained from the respective inverting output terminals -Q of 2, 84 and 86 have low levels, and the signals take low levels from the AND gate circuits 91, 93 and 95, respectively. F ₁ , F ₂ and F ₃ are obtained, and the signals Fa ′, Fb ′ and Fc ′ obtained from the inverting output terminals −Q of the D-flip flops 81, 83 and 85, respectively, and the D-flip. The signals Ra, Rb obtained from the respective output terminals Q of the flops 82, 84 and 86
And Rc become high level, and the signal R which takes high level from the AND gate circuits 92, 94 and 96, respectively.
₁ , R ₂ and R ₃ are obtained. As a result, the OR gate circuit 97 obtains the signal Ma that continuously attains the low level, and the OR gate circuit 98 obtains the signal Mb that continuously attains the high level.

Further, when the vehicle is stopped, all of the detection pulse train signals Pa, Pb and Pc are continuously low level, or one or two of them are continuously high level and Of the OR gate circuits 97 and 98, since those of the OR gate circuits 97 and 98 continuously take the low level.
The signals Ma and Mb respectively obtained from the above are continuously low level.

As described above, the signals Ma and Mb which reverse the level relationship between the high level and the low level when the vehicle is moving forward and backward and take the low level when the vehicle is stopped are As the traveling state information signal, each control unit, for example, an electric brake (parking brake) control unit is supplied through the wiring section 100a and the output terminal 100b of the electronic meter control circuit section 100 forming the signal supply section. As a result, in the electric brake control unit, operation control corresponding to the forward, backward, and stopped states of the vehicle is performed according to the levels of the supplied signals Ma and Mb.

As described above, in the forward / rearward traveling determination section 80 which constitutes the signal forming means for transmitting the signals Ma and Mb as the traveling state information signals, all of the detection pulse train signals Pa, Pb and Pc are as described above. Not only in the normal state in which the detection pulse train signals Pa, Pb and P
Even in the abnormal time when any of the values c cannot be obtained properly, the running state including the forward state, the backward state and the stopped state of the vehicle is determined.

For example, when the detection pulse train signal Pa continuously becomes high level or low level when the vehicle moves forward or backward, both signals F ₁ and R ₁ obtained from the AND gate circuits 91 and 92 are low level. becomes as taking the signal F _2, R _2, F ₃ and R ₃ obtained respectively from the other of the aND gate circuit 93 to 96, since becomes to take the same level as normal, gate circuit 9
The signals Ma and Mb obtained from 7 and 98 respectively have the same level as in the normal state.

Further, even when the detection pulse train signal Pb or Pc continuously takes the high level or the low level when the vehicle moves forward or backward, the detection pulse train signal Pa continuously takes the high level or the low level. OR gate circuits 97 and 98 in the same manner as in the case of
The signals Ma and Mb obtained from the respective signals have the same level as in the normal state.

Therefore, no matter which of the detection pulse train signals Pa, Pb, and Pc is abnormal, the forward / rearward traveling determination unit 80 takes a high level when the vehicle is moving forward, and when the vehicle is moving backward or is stopped, as in the normal state. A signal Ma that takes a low level,
A signal Mb that takes a low level when the vehicle moves forward and stops, and has a high level when the vehicle moves backward is obtained, and the forward, backward, and stopped states of the vehicle are discriminated.

In the above example, the rotary disc 14
The through-holes 16 as the detected portions are arrayed and formed, and photoelectric type detectors 20A, 20B, and 20C are used as the detection units that obtain the detection pulse train signals according to the array of the detected portions. The detection unit used in the information signal forming and supplying device according to the present invention is not limited to the one having a combination of the detection target portion provided as a through hole in the rotary disc 14 and the photoelectric detector, and the rotation circle A light reflecting portion may be formed in the plate 14 in place of the through hole, and the light reflecting portion may be combined with a photoelectric detector for irradiating the light and receiving the reflected light. Further, other various detected parts such as a magnetized part are arrayed and formed on the rotating disk 14, and the detected parts are various other than photoelectric detectors such as electromagnetic detectors. It may be provided with a detector.

[0089]

As is apparent from the above description, according to the information signal forming / supplying device of the present invention, for example, in a plurality of control units installed in a vehicle, a detection output signal that changes with a change in vehicle speed. When a signal according to the vehicle speed of the vehicle and a signal according to the traveling state of the vehicle based on the above are required, they are respectively obtained by the first and second signal forming means in the signal processing unit included in the control circuit unit. The vehicle speed information signal and the traveling state information signal are supplied to each control unit by the signal supply unit included in the control circuit unit, so that each of the plurality of control units responds to the vehicle speed of the vehicle. It is not necessary to individually provide a signal forming unit for forming a signal and a signal forming unit for forming a signal according to the traveling state of the vehicle. That is, the control circuit unit is provided as the first signal forming unit and the second signal forming unit,
A signal forming unit for forming a signal corresponding to the vehicle speed of the vehicle and a signal corresponding to the traveling state of the vehicle based on the detection output signal from the detection unit, and the signal formed by the signal forming unit are provided in the vehicle. The signal supply unit that supplies the control unit is in a highly efficient use state, and the wiring for supplying the signal to the control unit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an information signal forming / supplying device according to the present invention together with an electronic meter device to which it is applied.

FIG. 2 is a perspective view showing a specific configuration example of a disc built-in portion used in the example shown in FIG.

FIG. 3 is a side view including a partial cross section used for explaining a photoelectric detector used in the example shown in FIG.

FIG. 4 is a block diagram showing an example of a logic circuit block used in the example shown in FIG.

5 is a block diagram showing a specific configuration example of an output transmission unit in the logic circuit block shown in FIG.

6 is a block diagram showing a specific configuration example of an abnormality detection unit and an abnormality countermeasure signal formation unit in the logic circuit block shown in FIG.

FIG. 7 is a waveform diagram provided for explaining the operation of the logic circuit block shown in FIG.

FIG. 8 is a waveform diagram provided for explaining the operation of the logic circuit block shown in FIG.

FIG. 9 is a block diagram showing a specific configuration example of a forward / backward movement determination unit in the logic circuit block shown in FIG.

[Explanation of symbols]

10 Disk Built-in Section 14 Rotating Disk 16 Through Hole 20A, 20B, 20C Detector 28 Logic Circuit Block 30 Output Sending Section 35 Switch Circuit 36 Frequency Multiplier Circuit 40 Abnormality Detection Section 50 Abnormality Countermeasure Signal Forming Section 51, 52, 53, 61, 62, 63 RS flip-flop 54, 55, 56, 64, 65, 66, 81, 82, 8
3, 84, 85, 86 D-flip-flop 80 forward / backward movement determination section 100 electronic meter control circuit section 100a wiring section 100b, 100c output terminal 104 CPU 106 engine speed sensor 108 fuel gauge 110 water temperature sensor 111 interface section 113 A / D Conversion unit 115 Drive unit 120 Display unit

Front Page Continuation (56) References JP-A-57-64166 (JP, A) JP-A-57-56758 (JP, A) JP-A-52-1391 (JP, A) Actual development Sho-53-54003 (JP , U) Actually open Sho 58-66361 (JP, U) Actually open Sho 60-136211 (JP, U) Actually open Sho 58-24801 (JP, U) Actually open Sho 60-51467 (JP, U) Special public Sho 60-28063 (JP, B2)

Claims (3)

(57) [Claims] 1. Control for a specific device provided in a vehicle
A control circuit section for performing, and a detection section for generating a detection output signal that varies with variations in the vehicle speed in the vehicle, the control circuit unit, the predetermined processing on the detection output signal obtained from the detector The vehicle speed information signal corresponding to the vehicle speed of the vehicle is obtained by performing predetermined processing on the detection output signal obtained from the first signal forming means and the detection section to obtain a traveling state information signal representing the traveling state of the vehicle. A signal processing unit having a second signal forming unit , and the vehicle speed information signal and the traveling state information signal obtained by the signal processing unit are independent of the specific device installed in the vehicle. An information signal forming / supplying device configured to include a signal supply unit for supplying the control unit. 2. The information signal forming / supplying apparatus according to claim 1, wherein the signal processing section is composed of a logic circuit block. Wherein the control circuit unit, according to claim 1 information signals forming the supply device, wherein a is an electronic meter control circuit section for controlling the display unit for displaying the state of the vehicle.