JPS61292563A - Rotation detector - Google Patents

Abstract

PURPOSE:To simplify the wiring necessary for the transmission or processing of a plurality of detection pulse train signals or the like, by arranging a detector support member to support a detection signal generating section and a logical circuit section integrally. CONSTITUTION:At a detection signal generating section, detectors which generate detection pulse train signals corresponding to the array of a part to be detected formed on a rotary disc 14 are so arranged that there will be a phase difference or 2pi/3 in substance between first and second detection pulse train signals obtained from adjacent two thereof to make detection pulses forming the first and second detection pulse train signals overlap partially. A logical circuit section forms a signal corresponding to the speed or direction of rotation of a rotor on the basis of the detection pulse train signal obtained from the detection signal generating section, a signal indicating the abnormality in detection pulse train signals or the like. Then, a detector support member 21 has a circuit-housing section 23 formed integral with a projection arm section 22 to support the detection signal-generating section containing detectors 24A-24C and the logical circuit section integrally.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a rotation detection device used for detecting the rotation speed, two rotation directions, one rotation angle, etc. of a rotating body.

(Prior Art) In vehicles, various rotation detection devices are put into practical use to detect the rotational state of an output shaft of a transmission, etc., in order to measure vehicle speed and the like. A typical rotation detection device is equipped with a rotating disk that rotates along with or in conjunction with a rotating body whose rotational state is to be detected, and a large number of rotating disks are arranged along the circumference. The detected parts such as the light reflecting part, the light transmitting part, or the magnetized part are arranged in a ring shape, and the detected parts are detected optically or magnetically to form an array. A detector that generates a detection signal corresponding to It is made to correspond to the rotational state of the body.

In a rotation detection device equipped with such a rotating disk,
Detection accuracy is affected by the fineness of the detected parts arranged in a ring shape on the rotating disk. For example, when each detected part is a light reflecting part or a light transmitting part such as a through hole. However, there are limitations in processing when forming a large number of light reflecting portions or light transmitting portions on a rotating disk, making it difficult to sufficiently increase their fineness. Also, if each light reflecting part or light transmitting part is made narrow to increase the density,
This results in a disadvantage that the S/N ratio of the detection signal obtained from the detector decreases.

For this reason, several measures have been proposed to improve the detection accuracy while keeping the density of the light-reflecting parts or light-transmitting parts arrayed on the rotating disk within a predetermined range. As described in Japanese Patent Publication No. 55-172856, a rotating disc is provided with an annular array of light reflecting parts or light transmitting parts in a double radial direction of the rotating disc, and the inner and outer light reflecting parts are arranged on the rotating disc. Two optical detectors are arranged corresponding to each of the annular arrays of sections or light-transmitting sections, and the detection signals obtained from each optical detector are combined, so that the detection accuracy is substantially increased. It is known to obtain different detection outputs.

However, as described above, when a rotation detection device equipped with a rotating disk is formed with a double ring-shaped arrangement of inner and outer light reflecting parts or light transmitting parts on the rotating disk, , the manufacturing process of the rotating disk becomes complicated, making it impossible to obtain the rotating disk easily, and the rotating disk tends to become larger.As a result, the manufacturing cost of the device increases and This results in an increase in the size of the entire device.

Therefore, a plurality of detected parts are arranged in an annular shape surrounding the rotation center, and there is a rotating disk that rotates with or in conjunction with the rotating body whose rotational state is to be detected, and a rotating disk that is close to the rotating disk. The sensor is equipped with a plurality of detectors that are arranged to generate detection pulse train signals according to the arrangement of the detected parts, and the detection pulse train signals obtained from each of the plurality of detectors are arranged in a predetermined mutual phase. The rotation detection output signal is arranged so as to have a phase difference and each detection pulse train signal is combined to improve detection accuracy. A rotation detection signal generating device that can be easily produced has been considered.

Each detected pulse train signal from a rotation detection signal generator including such a rotating disk and a plurality of detectors from which a plurality of detected pulse train signals having a predetermined mutual phase difference is obtained,
They are supplied to multiple control units that commonly require them, such as a meter control unit, anti-lock brake control unit, auto cruise control unit, etc., and each control unit determines the rotational state based on the multiple detection pulse train signals. A rotation detection output signal representing the rotational speed of the rotating body to be detected and a signal representing the rotational direction of the rotating body whose rotational state is to be detected are obtained to perform the respective required controls.

(Problems to be Solved by the Invention) As described above, a plurality of detection pulse train signals having a predetermined mutual phase difference are supplied to each of a plurality of control units, and each control unit receives a plurality of detection pulse train signals that are supplied to each control unit. In a control system in which a rotation detection output signal and other necessary signals are formed based on a signal, each of a plurality of control units generates a rotation detection output signal based on a plurality of detection pulse train signals. It is assumed that a logic circuit section for forming the signal and other necessary signals is included.

In other words, a logic circuit unit for a plurality of control units configured to control the husband H using a plurality of detection pulse train signals in common to obtain the same signal from a plurality of commonly supplied detection pulse train signals. This means that multiple signal processing units are installed. Duplicate installation of signal processing sections like this is not only unreasonable as the number of signal processing sections on the floor board that is truly required is installed, but each signal processing section is in an inefficient state of use. This results in the inconvenience that the wiring for supplying signals to the parts becomes complicated and the amount of wiring increases.

In view of these points, the present invention provides a rotating member in which a plurality of detected parts are arranged in an annular manner surrounding a rotation center, and each rotating member rotates in accordance with a rotating body whose rotational state is to be detected; A plurality of detectors are arranged close to the member and are arranged to generate detection pulse train signals according to the arrangement of the detected parts, and are arranged so that each detection pulse train signal has a predetermined mutual phase difference. When used to perform the respective control operations of the plurality of control units based on the detection pulse train signals respectively obtained from the plurality of detectors, the information required in each control unit from the plurality of detection pulse train signals is used. , the logic circuit section for forming signals corresponding to the rotational speed or rotational direction of the rotating body to be detected, or signals representing abnormalities in each detection pulse train signal, etc., is put into use with excellent efficiency. It is an object of the present invention to provide a rotation detection device that can simplify wiring required for transmitting or processing a plurality of detection pulse train signals and signals obtained based on them.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the rotation detection device according to the present invention includes a plurality of detected parts arranged in a manner surrounding a rotation center,
A rotating member that rotates in accordance with the rotating body whose rotational state is to be detected, and n pieces (n is 3 or more positive pulse train signals) that are arranged close to the rotating member and generate detection pulse train signals according to the arrangement of the detected parts. (integer) detectors detect first and second detected pulse train signals obtained from two adjacent ones of them with a substantially 2π
/n, and each detection pulse forming the first detection pulse train signal and each detection pulse forming the second detection pulse train signal partially overlap. and a signal corresponding to the rotation speed or direction of rotation of the rotating body whose rotational state is to be detected, or each detection pulse train signal, based on the detection pulse train signal obtained from the detection signal generator and the detection signal generator. The detection signal generation section and the logic circuit section are further provided with a detector support member that supports the detection signal generation section and the logic circuit section so as to be integrated with each other.

(Function) In the rotation detection device according to the present invention configured as described above, the detection pulse train signals obtained from the n detectors in the detection signal generation section are transmitted to the n detectors by the detector support member. The rotational speed of the rotating body whose rotational state is to be detected is supplied to a logic circuit unit integrally supported with a detection signal generation unit including A rotation detection output signal corresponding to the one-rotation state, a signal corresponding to the rotation direction of the rotating body in which the state of one rotation is to be detected, a signal indicating an abnormality in each detection pulse train signal, etc. are formed. Then, the plurality of signals obtained from the logic circuit section are distributed and supplied to the plurality of control units that require them.

As a result, it is possible to detect the rotation of the rotating body whose rotation state is to be detected with high precision, and also to detect various signals based on the plurality of detection pulse train signals that enable such high precision rotation detection. It is assumed that the logic circuit section for obtaining the signal is used efficiently by avoiding duplicative installation, and that the wiring of each part including the wiring for supplying the detection pulse train signal from the detection signal generation section to the logic circuit section is This simplifies the structure and further improves the space efficiency in arranging the detection signal generating section and the logic circuit section.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a rotation detection device according to the present invention. This example forms a rotation detection device that detects the rotational state of an output shaft of a transmission in a vehicle, etc., and includes a built-in disc part 10 and a detector fixing part 20 related thereto.
It is equipped with

The internal disc part 10 has a case 11 represented by a dashed line, and within this case 11 is a shaft 13 connected to a cable 12 that transmits the rotation of the output shaft of a transmission, for example.
and a rotating disk 14 fixed to the shaft 13. This rotating disk 14 has a large number of substantially rectangular first, second and third through holes 16a, 16b and 1.
6C are provided to form a triple annular arrangement surrounding the center of rotation of the rotating disk 14. A plurality of first . Second or third through hole 16a.

16b or 16c are each of the same size and are spaced apart from each other by a distance equal to their respective widths. These first. Second and third through holes 16a.

Each of 16b and 16c is a light transmitting part as a detected part, and the first . Second and third through holes 16a, 16b
In each annular arrangement formed by each of 16C and 16C, the first . Second and third light blocking section 18
a, 18b and 18C.

The detector fixing part 20 arranged in relation to the disc built-in part 10 includes a detector support member 21 fixed to the rotating disc 14.
The detector support member 21 is formed into a mouth shape as a whole, and as shown in FIG.
2a and the lower part 22b sandwich the rotary disk 14, and a protruding arm portion 22 that protrudes from the outer circumferential side of the rotary disk 14 toward its center of rotation, and is formed integrally with the protruding arm portion 22. It has a circuit accommodating portion 23.

The protruding arm portion 22 is connected to the first. Second and third through holes 16a.

Three photoelectric detectors 24A, 24B, and 24C detect 16b and 16C, respectively, and generate detection pulse train signals.
is supported. Detectors 24A, 24B and 24C are
Light-emitting elements 25a, such as light-emitting diodes, are disposed within the upper portions 22a of the protruding arms 22, which are located above the rotating disk 14, respectively.

25b and 25c, and a light receiving element 26a such as a phototransistor arranged in the lower part 22b of the protruding arm part 22, which is located below the rotating disk 14.

26b and 26C, and the light-emitting element 25a and the light-receiving element 26a constituting the detector 24A are mutually connected to each other through an annular array of a plurality of first through holes 16a provided in the rotating disk 14. The light-emitting element 25b and the light-receiving element 26b, which face each other and constitute the detector 24B, are connected to the rotating disk 14.
The light-emitting element 25C and the light-receiving element 26C which face each other via the annular array of the plurality of second through holes 16b provided in the rotary disk 14 and which constitute the detector 24C are are opposed to each other via an annular array of third through holes 16b. Therefore, the light from the light emitting element 25a reaches the light receiving element 26a, the light from the light emitting element 25b reaches the light receiving element 26b, and the light from the light emitting element 25c reaches the light receiving element 26c, respectively. 1. This is done through the second and third through holes 16a, 16b and 16c, and the first through hole in the rotating disk 14. 2nd and 3rd
through holes 16a, 16b and 16C and detector 24A.

24B and 24C, as the rotating disk 14 rotates, light from the light emitting element 25a reaches the light receiving element 26a, light from the light emitting element 25b reaches the light receiving element 26b, The light from the light emitting element 25c reaches the light receiving element 26c sequentially and repeatedly, and the light from the light emitting element 25a reaches the light receiving element 26c.
173 on the terminal side of the period reaching 6a and the light emitting element 25b
1 on the starting end side of the period in which the light from reaches the light receiving element 26b.
73, and the light from the light emitting element 25b is transmitted to the light receiving element 2.
173 on the terminal side of the period reaching 6b and the light emitting element 25c
1 on the starting end side of the period in which the light from the reaches the light receiving element 26c.
73 is further connected to 173 and the light emitting element 25 at the end of the period in which the light from the light emitting element 25C reaches the light receiving element 26c.
It is set so that the starting 1/3 of the period during which the light from a reaches the light receiving element 26a overlaps with each other.

The light receiving elements 26a, 26b and 26c generate signals in response to the arrival of light from the light emitting elements 25a, 25b and 25c, respectively, so that when the rotating disk 14 rotates, the light receiving elements 26a, 26b and 26c , respectively, the first
．． Detection pulses corresponding to the second and third through holes 16a, 16b and 16c are generated respectively, and therefore the light receiving element 26
a, 26b and 26c, a plurality of first . Second
Detection pulse train signals corresponding to the respective arrangements of the third through holes 16a, 16b, and 16C are obtained as detection output signals regarding the detected portion, and these three detection pulse train signals are sequentially arranged in substantially 2π each detection pulse forming one of each set of two having a mutual phase lag of /3 and having a mutual phase difference of substantially 2π/3, and each detection pulse forming the other; have mutually overlapping parts.

That is, each of the three detectors 24A, 24B, and 24C is connected to the first detector provided on the rotating disk 14. It generates detection pulse train signals according to the respective arrangements of the second and third through holes 16a, 16b and 16C, and detects the detectors 24A and 24B and the detector 24 when the rotating disk 14 rotates.
The two detection pulse train signals obtained from the detectors B and 24C1 or the detectors 24C and 24A are substantially two.
They are arranged so that they have a mutual phase difference of π/3 and each detection pulse forming one of these two detection pulse train signals and each detection pulse forming the other have a mutually overlapping portion. This forms the detection signal generating section.

Further, the circuit housing portion 23 in the detector support member 21 is
It is formed into a box shape and has three detectors 24 inside.
It supports a logic circuit block 28 which is connected to each of the detectors 24A, 24B and 24C and is supplied with three detection pulse train signals obtained therefrom, and supplies power to the detectors 24A, 24B and 24C and the logic circuit block 28. A signal deriving wire Ws for sending a signal obtained from the logic circuit block 28 and the logic circuit block 28 is derived.

In this way, three detectors 24A, 24B and 24
The detection signal generation section including C and the logic circuit block 28 are as follows:
It is integrally supported by the detector support member 21.

As shown in FIG. 3, the logic circuit block 2 supported by the circuit housing portion 23 in the detector support member 21
8 includes detectors 24A, 2 which are supported by the protruding arm portion 22 of the detector support member 21 and form a detection signal generating portion.
Detection pulse train signal P obtained from each of 4B and 24C
an output sending unit 30 including a detection output forming unit and an output selecting unit, to which the signals Pb, Pb and Pc are supplied; Abnormality detection unit 40. It includes an abnormality countermeasure signal forming section 50 and a forward/reverse motion determining section 80. The output sending unit 30 includes an abnormality detecting unit 40.
The anomaly detection signal Pe from the anomaly countermeasure signal forming section 50 and the anomaly countermeasure signal Cx from the anomaly countermeasure signal forming section 50 are also supplied.
The signals Pr and Pd from 0 are supplied to the abnormality countermeasure signal forming section 50.

The output sending unit 30 includes a detector 2 as shown in FIG.
4A and the detection pulse train signal Pb from the detector 24B are supplied to the first AND gate circuit 31. Detection pulse train signal pb from detector 24B
and a second AND gate circuit 32. to which the detection pulse train signal Pc from the detector 24C is supplied. A third AND gate circuit 33 to which the detection pulse train signal Pc from the detector 24C and the detection pulse train signal Pa from the detector 24A are supplied.
, and an OR gate circuit 34 to which signals P+, Pz and P3 obtained from each AND gate circuit 31, 32 and 33 are supplied, and the output signal P of the OR gate circuit 34 is
A detection output forming section 30A is formed in which n is a rotation detection output. Further, a frequency multiplier circuit 36 for multiplying the input signal frequency by three, to which the abnormality countermeasure signal Cx from the abnormality countermeasure signal forming section 50 is supplied, and a detection output forming section 30
A fixed contact 35a is supplied with the output signal Pn obtained from the OR gate circuit 34 of A, and a signal C is obtained by multiplying the frequency of the abnormality countermeasure signal CX by three in the frequency multiplier circuit 36.
Fixed contact 35b to which x' is supplied and abnormality detection section 4
An output selection section 30B is formed, which is controlled by an abnormality detection signal Pe obtained from 0, and includes a switch circuit 35 having a movable contact 35C selectively connected to one of the fixed contacts 35a and 35b.

The abnormality detection section 40 includes a detector 24 as shown in FIG.
Detection pulse train signals Pa, P from A, 24B and 24C
The OR gate circuit 41 and the AND gate circuit 42 are supplied with b and Pc, respectively, and the signal Pr obtained from the OR gate circuit 41 is directly supplied, and the signal Pd obtained from the AND gate circuit 42 is supplied via an inverter 43. The output signal of the AND gate circuit 44 is used as the abnormality detection signal Pe.

In the abnormality countermeasure signal forming section 50, as shown in FIG. Inverter 57
An RS flip-flop 51.5 in which a signal Pr' obtained by inverting the level is supplied to each reset terminal R.
2 and 53 and these RS flip-flops 51.5
The signals S1.2 and S1.2 obtained at the respective output terminals Q of S1. S
2, S, + are delayed by a minute amount of time by delay circuits 51a, 52a, and 53a, resulting in a signal St',
D-, where Sz' and S3° are supplied to the data terminals, respectively, and the signal Pr is supplied to each clock terminal C.
Flip-flops 54, 55 and 56 and detection pulse train signals Pa, Pb and Pc are connected to inverters 67 and 68, respectively.
and 69, the signal Pa' obtained by inverting the level
, Pb'' and Pc' are respectively supplied to the cent terminal S, and the signal Pd obtained from the AND gate circuit 42 of the abnormality detection section 40 is supplied to each reset terminal R.
Flip-flops 61, 62 and 63 and these RS
The signal S? available at the output terminal Q of each of the flip-flops 61, 62 and 63? .

A signal St'+se obtained by delaying Sll and S by a minute time by delay circuits 61a, 62a and 63a.
D-flip-flops 64, 65 and 66 are arranged, in which signals Pd and C are respectively supplied to the data terminals, and a signal Pd is supplied to each clock terminal C. The signals S4 and Sl obtained from respectively.

is connected to the OR gate circuit 58, and the D-flip-flop 55
and 65, the signals S and S11 are sent to the OR gate circuit 59 and the D-flip-flop 56.
and 66, respectively, are supplied to the OR gate circuit 60.

Furthermore, the signal S4 or S from the OR gate circuit 58
l. is directly supplied to the AND gate circuit 71, and its level is inverted by the inverter 77 and supplied to the AND gate circuit 72, and the signal S from the OR gate circuit 59 is
Alternatively, S11 is directly supplied to the anchor circuit 72, its level is inverted by the inverter 78, and supplied to the AND gate circuit 73, or the OR gate circuit 6
The signal S from 0 or sI□ is directly supplied to the AND gate circuit 73 and is inverted in level by the inverter 79 and supplied to the AND gate circuit 71. Furthermore, detection pulse train signals Pa, Pb, and Pc are supplied to AND gate circuits 71, 72, and 73, respectively.

Then, the signals CI, C2 and c3 obtained from the AND gate circuits 71, 72 and 73, respectively, are sent to the OR gate circuit 7.
6, and the output signal of the OR gate circuit 76 is used as the abnormality countermeasure signal Cx.

In the combination of the disc built-in portion 1o and the logic circuit block 28 configured as described above, the rotating disc 14 is rotated according to the vehicle speed when the vehicle is running, and the detectors 24A, When both 24B and 24C are operating normally, the detectors 24A and 24
B and 24C to time points 1.B and 24C in FIG. 6A, B and C, respectively. As shown in the previous period T0 and at time t in FIGS. 7A, B and C, in the previous period T4,
Detection pulse train signals Pa, Pb, and Pc having a phase difference of 2π/3, that is, 120° are sequentially obtained. These detection pulse train signals Pa, Pb and Pc
are detected pulse train signals Pa and pb, pb and Pc, which have a mutual phase difference of 120°.
Alternatively, each detection pulse forming one of Pc and Pa and each detection pulse forming the other have a mutually overlapping portion, that is, a portion that takes a high level at the same time.

These detection pulse train signals Pa, Pb and Pc are, respectively,
In the manner as described above, the first . It is supplied to second and third AND gate circuits 31, 32 and 33. A signal P1 is obtained from the first AND gate circuit 31, which is formed by a train of pulses corresponding to the overlap portion between each detection pulse forming the detection pulse train signal Pa and each detection pulse forming the detection pulse train signal pb. A signal P2 is obtained from the second AND gate circuit 32, which is formed by a train of pulses corresponding to the overlap portion between each detection pulse forming the detection pulse train signal Pb and each detection pulse forming the detection pulse train signal Pc. Furthermore, the third AND gate circuit 33 outputs a signal P3 formed by a train of pulses corresponding to the overlap portion between each detection pulse forming the detection pulse train signal Pc and each detection pulse forming the detection pulse train signal Pa. is obtained. These signals P+, P
z and P3 are supplied to the OR gate circuit 34, and from the OR gate circuit 34, signals P+, Pz and P3 are combined to produce a signal as shown in period T0 in the sixth diagram and period T4 in the seventh diagram. An output signal Pn in the form of a pulse train signal is obtained. This output signal Pn
The pulse train signals forming the detection pulse train signals Pa, P
It has a frequency three times the frequency of each of b and Pc, and this is used as the rotation detection output.

Therefore, this rotation detection output is significantly more effective than when the detection pulse train signal Pa, Pb, or Pc obtained according to the annular arrangement of the through holes 16 provided in the rotating disk 14 is directly used as the rotation detection output. Rotation detection will be performed with increased detection accuracy.

As described above, in a state in which each of the detection pulse train signals Pa, Pb, and Pc is normally obtained from the detection output forming section 30A, and an output signal Pn having a frequency three times that frequency is obtained, The OR gate circuit 41 and the AND gate circuit 42 in the abnormality detecting section 40 of the logic circuit block 28 also have the period T in FIGS. 6A, B, and C described above.

, and detection pulse train signals Pa, Pb, and Pc shown in period T4 in FIGS. 7A, B, and C are supplied. As a result, from the OR gate circuit 41 and the AND gate circuit 42, the period T in FIG. 6E and F, respectively. , and a signal Pr taking a high level h and a signal Pd taking a low level β as shown in periods T4 in FIGS. 7E and F are obtained. Then, the signal Pr that takes a high level h is sent as is, and the signal Pd that takes a low level l is converted into a signal that takes a high level h by an inverter 43 and is supplied to an AND gate circuit 44, and from the AND gate circuit 44, Period T in FIG. 6G. , and the seventh
An abnormality detection signal Pe having a high level h as shown in period T4 in FIG. G is obtained.

In this way, in a state where all of the detection pulse train signals Pa, Pb, and Pc from the detectors 24A, 24B, and 24C are properly obtained, the OR gate circuit 41 and the AND gate circuit 42 in the abnormality detection section 40 The obtained signals Pr and Pd take a high level h and a low level l, respectively, and as a result, the abnormality detection signal P
e takes a high level h.

The abnormality detection signal Pa taking this high level is transmitted to the switch circuit 35 in the output selection section 30B of the output sending section 30.
The wire W is supplied from the output terminal 28a of the logic circuit block 28 as shown in FIG.
For example, the signal is supplied to a lamp control unit that controls blinking of a warning lamp through the signal s, and the lamp control unit keeps the warning lamp in an extinguished state when the abnormality detection signal Pe takes a high level.

As described above, in a state where each of the detection pulse train signals Pa, Pb, and Pc is normally obtained, the abnormality countermeasure signal forming section 5
0, the RS flip-flops 51, 52 and 5
period T0 in FIGS. 6A, B, and C, and period T4 in FIGS. 7A, B, and C.
The detection pulse train signals Pa, Pb and Pc shown in
are supplied respectively, and the RS flip-flop 6
1. The inverter 6 is connected to each of the cent terminals S of 62 and 63 based on the above-mentioned detection pulse train signals Pa, Pb and Pc.
Signals Pa', Pb' and Pc' obtained from 7.68 and 69 are supplied.

At this time, the RS flip-flops 51, 52 and 53
A high-level signal Pr from the abnormality detecting section 40 is inverted to a low level by an inverter 57 and supplied to each of the positive terminals R of the RS flip-flop 51.
．． Signals S+, Sz and S3, which continuously take a high level h, are obtained from the output terminals Q of 52 and 53, respectively, and these signals S1, S2 and S3 are sent to the delay circuits 51a and 52, respectively.
a and 53a, the D-flip signal s,', s2' and 83° continuously take a high level, as shown in period T0 in FIGS. 6H, I and J.
The data terminals of flops 54, 55 and 56 are provided. D-Flip Flop 54.55 and 56
A signal P that takes a high level h is applied to each clock terminal C of
r is supplied to the output terminals Q of the D-flip-flops 54, 55 and 56, respectively, as shown in FIG. 6 during the period T0 in L and M. Signals S, , S5 and S, which take a low level l, are obtained and are supplied to one input terminal of OR gate circuits 58, 59 and 60, respectively.

Further, at this time, the reset terminals R of the RS flip-flops 61, 62 and 63, to which the signals Pa', Pb' and PC'' are supplied to the set terminal S, respectively, are As shown in period T in Figure 6F and period T4 in Figure 7F,
A signal Pd that continuously takes a low level l is supplied, and the RS
At the output terminals Q of each of the flip-flops 61, 62 and 63, the signal S? continuously assumes a high level h. , Sll and S are obtained, and these signals S7. S8 and S9 are connected to each other through delay circuits 61a, 62a and 63a, respectively.
, I and J as shown in period T4,
Signal S that continuously takes a high level? '＋S@'
and 89'' to the respective data terminals of the D-flip-flops 64, 65 and 66.A signal which takes a low level l is supplied to the clock terminal C of each of the D-flip-flops 64, 65 and 66. Pd is continuously supplied to the respective output terminals Q of the D-flip-flops 64, 65 and 66, as shown in FIG.
4, the signal Sl takes a low level l, as shown in
(+, Sl+ and S1□ are obtained and supplied to the other input terminals of OR gate circuits 58, 59 and 6o, respectively.

For this reason, the respective output signals of the OR gate circuits 58, 59 and 6° all take a low level l, and therefore, the output signals at N, O and P in FIG. Period T0 and seventh
Low level, as shown in period T4 in Figures N, O and P! Signals CI, Cz and c3 are obtained, and the abnormality countermeasure signal C- obtained from the OR gate circuit 76 is obtained.
x will continue to be at a low level.

The abnormality countermeasure signal Cx that takes this low level is transmitted to the output sending unit 3.
0 is supplied to the frequency multiplier circuit 36 in the output selection section 30B.

In this case, the switch circuit 35 of the output sending section 30
Since the high-level abnormality detection signal Pe obtained from the abnormality detection section 40 is supplied to the control terminal of the switch circuit 35, the movable contact 35C of the switch circuit 35 is connected to the fixed contact 35a, and , an output signal Pn having a frequency three times higher than each of the detection pulse train signals Pa, Pb, and Pc obtained from the detection output forming section 30A is sent out as a rotation detection output.

The output signal Pn sent from this output sending unit 30 is transmitted to the output terminal 2 of the logic circuit block 28 as shown in FIG.
The output signal Pn is distributed and supplied from 8b through the wire Ws to a plurality of control units that require the output signal Pn as control information, such as a meter control unit, an anti-lock brake control unit, a power seat control unit, and an auto cruise control unit. As a result, when appropriate detection pulse train signals Pa, Pb, and Pc are obtained from the detectors 24A, 24B, and 24C supported by the detector support member, each control unit controls the rotational speed of the output shaft of the transmission, and therefore, This means that highly accurate control will be performed depending on the vehicle speed.

On the other hand, in a state where the detection pulse train signal Pa cannot be properly obtained due to an accident such as a break in the detector 24A itself or its output side, the signals of each part will be At a time t, following a period T0 of
As shown in the period T from 1 to t2. That is, the detected pulse train signals pb and Pc from the detectors 24B and 24C are normally obtained during the period T in FIGS. 6B and C, but the detected pulse train signal Pa from the detector 24A is Period T in Figure 6 A
As shown in No. 1, the level becomes continuously low. As a result, in the detection output forming section 30A of the output sending section 30, the AND gate circuits 31 and 3
The signals P1 and P3 obtained from the AND gate circuit 32 continuously take a low level, and only the signal P2 obtained from the AND gate circuit 32 becomes a pulse train signal synchronized with the detection pulse train signal Pc.

As a result, the output signal Pn from the OR gate circuit 34 is
As shown in the period T in the sixth diagram, the signal becomes the same as the output signal P2 of the AND gate circuit 32.

At this time, the signal Pr from the OR gate circuit 41 in the abnormality detection unit 40 is transmitted during the period T on the sixth same day.
As shown in FIG.
As shown in period T1 in , the low level l is assumed. As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 is
1, it has a low level portion in synchronization with the falling portion of the detection pulse train signal Pc, which is the same as the signal Pr from the OR gate circuit 41.

This abnormality detection signal Pe, which periodically takes a low level, is transmitted to the switch circuit 35 in the output selection section 30B of the output sending section 30.
The light is supplied to the control end of the controller, and also to a lamp control unit that controls blinking of the warning lamp. When the abnormality detection signal Pe periodically takes a low level, the lamp control unit turns on the warning lamp and outputs the detection pulse train signal Pa.

Warns that either pb or Pc has become abnormal.

As described above, in a state where the detected pulse train signal Pa becomes abnormal and continuously takes a low level, the abnormality countermeasure signal forming section 50 outputs the RS flip-flops 51 .
6A and B to each set terminal S of 52 and 53.
Detection pulse train signal Pa taking a low level and normal detection pulse train signals pb and Pc as shown in period TI at Signals Pa', Pb', and PC'' obtained by inverting the levels of the above-mentioned detection pulse train signals Pa, Pb, and Pc by inverters 67, 68, and 69 are supplied.

At this time, the RS flip-flops 51, 52 and 53
A signal P as shown in the period T on the sixth same day from the abnormality detection unit 40 is applied to each reset terminal R
Detection pulse train signal Pc obtained by inverting the level of r
A signal P having a high level portion in synchronization with the falling portion of
r' is supplied. The signals Sl, , S2 and S3 obtained from the output terminals Q of the RS flip-flops 51, 52 and 53 are transmitted to delay circuits 51a and 52a, respectively.
and 53a, the signals S,',S as shown in periods TI in FIG. 6H, I and J.
2” and s, l are D-flip-flops 54.55
and 56 data terminals. A signal Pr as shown in period T in FIG. At the respective output terminals Q of .55 and 56, signals S, , SS and S6 are obtained, as shown in FIG.
These are supplied to one input terminal of OR gate circuits 58, 59 and 60, respectively.

At this time, the signals Pa', Pb'' and Pc' are supplied to the reset terminal S of the RS flip-flops 61, 62 and 63, respectively, and are supplied to the reset terminals R of the RS flip-flops 61, 62 and 63, respectively. , as shown in period T in FIG.
and 63, the signals s7. and 63 continuously have a high level h at their respective output terminals s7. s11 and S9 are obtained, and the clock terminals C of the D-flip-flops 64, 65 and 66 are also supplied with a signal Pd taking a low level l,
At the output terminals Q of the D-flip-flops 64, 65 and 66, there is a signal S1°+S which continuously assumes a low level l.
11 and S12 are obtained, which are supplied to the other input terminals of OR gate circuits 58, 59 and 60, respectively.

Therefore, from the OR gate circuits 58, 59 and 60,
In FIG. 6, signals Sa, Ss and S6 as shown in period T1 in L and M are obtained as they are. The AND gate circuit 71 receives a signal S4 as shown in period T in FIG. 6K and a signal S6 as shown in period T1 in FIG. signal and a detection pulse train signal Pa that continuously takes a low level, and the signal C1 obtained from the AND gate circuit 71 takes a low level 2 as shown in period T1 in FIG. 6N. The AND gate circuit 72 also receives a signal S5 as shown in period T in FIG. 6 and a signal S4 as shown in period T in FIG. The normal detection pulse train signal Pb is supplied from the AND gate circuit 72, and the normal detection pulse train signal pb is obtained as the signal C2 from the AND gate circuit 72, as shown in period T in FIG.

Further, the AND gate circuit 73 receives a signal obtained by inverting the levels of the signal S6 as shown in period T in FIG. 6M and the signal S5 as shown in period T+ in FIG. 6 by an inverter 78. and a normal detection pulse train signal PC are supplied, and the signal C3 obtained from the AND gate circuit 73 takes a low level 1 as shown in period T1 in FIG. 6P.

Therefore, at this time, the OR gate circuit 76 obtains the signal Cz obtained from the AND gate circuit 72, that is, the normal detection pulse train signal pb, as the abnormality countermeasure signal Cx. Detection pulse train signal p as this abnormality countermeasure signal Cx
b is supplied to the frequency multiplier circuit 36 in the output selection section 30B of the output sending section 30, and is supplied to the fixed contact 35b of the switch circuit 35 as a signal Cx'' whose frequency has been multiplied by three.

In this case, the switch circuit 35 of the output sending section 30
An abnormality detection signal Pe obtained from the abnormality detection section 40 that periodically takes a low level is supplied to the control terminal of the switch circuit 35, and the switch circuit 35 receives the abnormality detection signal P that periodically takes a low level.
When e is supplied, the movable contact 35C is connected to the fixed contact 35b. As a result, the signal Cx' obtained by multiplying the frequency of the detection pulse train signal pb from the frequency multiplier circuit 36 by three times is transmitted from the movable contact 35c of the switch circuit 35 to the detection output forming section 30A.
It is sent out as a detection output in place of the output signal Pn from.

The signal Cx' sent from the output sending section 30 is supplied to each control unit, namely, the meter control unit, the unlock brake control unit, the power seat control unit, the auto cruise control unit, etc., in place of the output signal Pn. . As a result, if the detection pulse train signal Pa from the detector 24A arranged in the internal disk part 1O becomes abnormal and continuously takes a low level, the frequency of the normal detection pulse train signal pb becomes A state is automatically established in which the tripled signal Cx'' is used as an emergency rotation detection output for each control unit.

In addition, in a state where the detection pulse train signal pb or Pc cannot be properly obtained due to an accident such as a disconnection in the detector 24B or 24C itself or its output side, the signals of each part will be Period T2 from time t2 to t3 following period T, or period T
The detection pulse train signals Pa and Pc from the detectors 24A and 24C are properly obtained as shown in the period T2 in FIGS. 6A and 6C. The detected pulse train signal Pb from the device 24B is detected during the period T on the sixth same day.
2, or the detected pulse train signals Pa and Pb from the detectors 24A and 24B are properly obtained as shown in period T3 in FIGS. 6A and 6C. However, the detected pulse train signal Pc from the detector 24C becomes a low level continuously as shown in period T3 in FIG. If a disconnection occurs in the detection pulse train signal P
a is not obtained properly (the situation is the same as in the situation where a is not obtained properly).

That is, the output signal Pn of the OR gate circuit 34 of the detection output forming section 30A is the same as the signal P3 obtained from the AND gate circuit 33, as shown in the period T2 in the sixth diagram, or the period T2 in the sixth diagram. As shown in T, the signal P1 obtained from the AND gate circuit 31
At this time, the abnormality detection signal Pe obtained from the abnormality detection section 40 is the same as the signal Pr obtained from the OR gate circuit 4I, as shown in period T2 or T3 in FIG. 6G. , which periodically takes a low level. This abnormality detection signal Pe, which periodically takes a low level, is also transmitted to the output selection section 3 of the output sending section 30.
The signal is supplied to the control end of the switch circuit 35 at 0B, and is also supplied to a lamp control unit that controls blinking of the warning lamp, and the lamp control unit turns on the warning lamp.

Further, based on the same operation as when the detection pulse train signal Pa continuously takes a low level, the OR gate circuits 58, 59 and 60 of the abnormality countermeasure signal forming section 50 generate the following signals as shown in FIG. Period T2 or T3 in L and M
The signals S, , S5 and S6 as shown in are obtained as they are, so that from the OR gate circuit 76,
As the abnormality countermeasure signal Cx, the signal C8 obtained from the AND gate circuit 73, that is, the normal detection pulse train signal Pc,
Alternatively, the signal CI obtained from the AND gate circuit 71
That is, a normal detection pulse train signal Pa is obtained. The detected pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is supplied to the frequency multiplier circuit 36 in the output selection section 30B of the output sending section 30, and is sent to the fixed contact 35 of the switch circuit 35 as a signal CX' whose frequency is multiplied by 3.
b.

Even in such a case, the control terminal of the switch circuit 35 of the output sending section 30 is supplied with the abnormality detection signal Pe obtained from the abnormality detecting section 40 and periodically taking a low level. The movable contact 35c is the fixed contact 35b
from the movable contact 35c to the frequency multiplier circuit 36.
The signal Cx' obtained by multiplying the frequency of the detection pulse train signal Pc or Pa from the detection output forming section 3
It is sent out as a detection output in place of the output signal Pn from 0A, and is used as an emergency rotation detection output for each control unit 45-48.

On the other hand, for example, in a state where a short-circuit accident occurs in the detector 24A and the detection pulse train signal Pa cannot be obtained properly, the signals of each part are
4, the period T from time t to t is as shown.

That is, the detected pulse train signals Pb and Pc from the detectors 24B and 24C are normally obtained as shown in period T5 in FIGS. 7B and 7C, but the detected pulse train signal P& from the detector 24A is Period T in A,
As shown in Figure 2, the level continues to be high. As a result, in the detection output forming section 30A of the output sending section 30, the AND gate circuits 31 and 33
The signals P and P3 obtained from the AND gate circuit 32 continuously take a high level, and only the signal P2 obtained from the AND gate circuit 32 becomes a pulse train signal synchronized with the detection pulse train signal Pc.

As a result, the output signal Pn from the OR gate circuit 34 is
Period T in the seventh diagram.

As shown in FIG. 2, the detection pulse train signal Pc has a low level portion in synchronization with the falling portion of the detected pulse train signal Pc.

At this time, the signal Pr from the OR gate circuit 41 in the abnormality detection section 40 is
As shown in FIG. 7, the signal Pd from the AND gate circuit 42 takes a high level.
As shown in period T, the detection pulse train signal Pc has a high level portion in synchronization with the rising portion of the detection pulse train signal Pc. As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 is
As shown in FIG. 2, the signal Pd from the OR gate circuit 42 has a low level portion in synchronization with the rising portion of the detection pulse train signal Pc, which corresponds to the level-inverted signal Pd.

This abnormality detection signal pe, which periodically takes a low level, is also applied to the switch circuit 3 in the output selection section 30B of the output sending section 30.
The light is supplied to the control end of No. 5 and also to a lamp control unit that controls blinking of the warning lamp, and the lamp control unit lights the warning lamp.

In this manner, in a state where the detection pulse train signal Pa continuously takes a high level, the abnormality countermeasure signal forming section 50 sets a high level to the set terminals S of each of the RS flip-flops 51, 52 and 53. The normal detection pulse train signal Pa and the normal detection pulse train signals pb and Pc are supplied to the RS flip-flop 61.6.
Signals Pal, which are obtained by inverting the levels of the above-mentioned detection pulse train signals Pa, Pb and pc by inverters 67, 68 and 69, are applied to the set terminals S of 2 and 63, respectively.
p b l and Pc' are supplied.

At this time, the RS flip-flops 51, 52 and 53
The reset terminals R of
A signal P that takes a low level and is obtained by inverting the level of r.
r′ is supplied and the RS flip-flop 51.52
At the respective output terminals Q of D-flip-flops 54, 52 and S3, a continuously high level signal s, 52 and S3 is obtained, and also at the respective clock terminal C of the D-flip-flops 54, 55 and 56, a low level is obtained. A signal Pr゛ that takes the level is supplied, and D
- a signal S4. at the output terminal Q of each of the flip-flops 54, 55 and 56 which is continuously at a low level; SS and S6 are obtained, which are OR gate circuits 58 and 59 respectively.
and 60 are supplied to one input terminal.

Also, at this time, the signals Pa'', pb' and Pc'' are supplied to the set terminal S of the RS flip-flop 6.
1. The reset terminals R of 62 and 63 are supplied with a high level in synchronization with the rising edge of the detection pulse train signal Pc, as shown by the period T in FIG. A signal Pd having a section is supplied. and the signals Sff, S obtained at the output terminals Q of the RS flip-flops 61, 62 and 63, respectively.

and S, ゛ are obtained through delay circuits 61a, 62a and 63a, respectively, periods T in FIG. 7H, I and J,
The signal S, ゛ as shown in .

S8° and Sq' are D-flip-flops 6436
5 and 66, respectively. A signal Pd having a high level portion is supplied to the clock terminal C of each of the D-flip-flops 64, 65 and 66 in synchronization with the rising portion of the detection pulse train signal Pc.
- At the output terminals Q of the flip-flops 64, 65 and 66, in FIG.
The signals SIO+ Sl+ and S as shown in
I□ are obtained, and these are OR gate circuits 58 and 59, respectively.
and the other input terminal of 60.

Therefore, from the OR gate circuits 58, 59 and 60,
The signals Slo+sll and Sl□ as shown in FIG. 7 during the period T in L and M are obtained as they are. Then, in the AND gate circuit 71,
A signal S, as shown in period T5 in . , a signal obtained by inverting the level of the signal S1□ as shown in period T5 in FIG. 7M, and a detection pulse train signal Pa that continuously takes a high level.
The signal C1 obtained from the AND gate circuit 71 takes a low level β as shown in period T in FIG. 7N. Further, the AND gate circuit 72 receives a signal Sl+ as shown in the period Ts in the seventh figure and a signal S1° as shown in the period T in FIG. signal and a normal detection pulse train signal pb are supplied, and a normal detection pulse train signal Pb is obtained from the AND gate circuit 72 as a signal C2, as shown in period T in FIG. 7O.

Further, the AND gate circuit 73 receives a signal SI2 as shown in a period T in FIG. 7M, and a signal SI+ as shown in a period T5 in FIG.
A signal obtained by inverting the level at the inverter 78,
A normal detection pulse train signal PC is supplied, and the signal C3 obtained from the AND gate circuit 73 takes a low level 1 as shown in period T in FIG. 7P.

Therefore, at this time, the OR gate circuit 76 obtains the signal C2+ obtained from the AND gate circuit 72 as the abnormality countermeasure signal Cx, that is, the normal detection pulse train signal Pb, and the output selector 30B of the output sending section 30 multiplies the frequency. The signal is supplied to the circuit 36 and then supplied to the fixed contact 35b of the switch circuit 35 as a signal Cx' whose frequency is tripled.

In this case, the switch circuit 35 of the output sending section 30
Since the control terminal of is supplied with the abnormality detection signal Pe obtained from the abnormality detection section 40 and which periodically takes a low level,
A movable contact 35c of the switch circuit 35 is connected to a fixed contact 35b. Thereby, from the movable contact 35c of the switch circuit 35, the signal Cx' obtained by multiplying the frequency of the detection pulse train signal Pb from the frequency multiplier circuit 36 is output as a detection output in place of the output signal Pn of the detection output forming section 30A. Sent as .

Therefore, even if the detection pulse train signal Pa from the detector 24A disposed in the disc built-in part 10 becomes abnormal and continuously takes a high level, the frequency of the normal detection pulse train signal Pb is 3. The signal Cx゛ obtained by multiplying is
A state is automatically taken as an emergency rotation detection output for each control unit.

In addition, in a state where a short-circuit accident occurs in the detector 24B or 24C and the detection pulse train signal pb or Pc cannot be obtained properly, the signals of each part will continue after the above-mentioned period T in FIG. During the period T1 from time t to t6, or following the period T6 (as shown in the period T after time t6), the detectors 24A and 2
Detection pulse train signals Pa and Pc from 4C are shown in FIG. 7A.
However, the detection pulse train signal pb from the detector 24B becomes a high level continuously as shown in the period T6 in FIG. 7B. Or the detector 24
The detection pulse train signals Pa and pb from A and 24B are
Although the detection pulse train signal pc from the detector 24C is properly obtained as shown in the period T in FIGS. 7A and C, the detection pulse train signal pc continuously takes a high level as shown in the period T in FIG. It was supposed to become a thing,
This is similar to the situation in which the detection pulse train signal Pa cannot be properly obtained due to a short-circuit accident occurring in the detector 24A described above.

That is, the output signal Pn of the OR gate circuit 34 of the detection output forming section 30A has a low level portion in synchronization with the falling portion of the detection pulse train signal Pa, as shown in period T6 in the seventh diagram, or has a low level portion in synchronization with the falling portion of the detection pulse train signal Pa. As shown in period T7 in Fig. 7, the detection pulse train signal pb has a low level portion in synchronization with the falling portion, and at this time, the abnormality detection signal Pe obtained from the abnormality detection section 40 is as follows. Period T6 or T in Figure 7G
As shown at 7, the signal Pd obtained from the OR gate circuit 42 corresponds to an inverted level, and periodically takes a low level. This abnormality detection signal Pe, which periodically takes a low level, is also supplied to the control end of the switch circuit 35 in the output selection section 30B of the output sending section 30, and is also supplied to the lamp control unit that controls blinking of the warning lamp. The lamp control unit 7 turns on the warning lamp.

Furthermore, under the same operation as when the detection pulse train signal Pa continuously takes a high level, the OR gate circuits 58, 59 and 60 of the abnormality countermeasure signal forming section 50 generate the following signals as shown in FIG. Period T6 or T in L and M
The signals S1°, sl+ and S1 as shown in ,
□ is obtained as is, and therefore the OR gate circuit 76
, the AND gate circuit 7 is used as the abnormality countermeasure signal Cx.
3, that is, the normal detection pulse train signal Pc, or the signal CI obtained from the AND gate circuit 71, that is, the normal detection pulse train signal Pa. The detection pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is transmitted to the output selection section 30 of the output sending section 30.
B is supplied to the frequency multiplier circuit 36, and the frequency is 3.
The multiplied signal CX' is supplied to the fixed contact 35b of the switch circuit 35.

Also in this case, the control terminal of the switch circuit 35 of the output sending section 30 is supplied with the abnormality detection signal Pe obtained from the abnormality detecting section 40 and periodically taking a low level.
The movable contact 35c of the switch circuit 35 is connected to the fixed contact 35b, and the frequency of the detection pulse train signal Pc or Pa from the frequency multiplier circuit 36 is 3.
The multiplied signal Cx' is output to the detection output forming section 30.
It is sent out as a detection output in place of the output signal Pn from A, and is used as an emergency rotation detection output for each control unit.

As described above, the output sending section 30. provided in the logic circuit block 28. The abnormality detecting section 40 and the abnormality countermeasure signal forming section 50 provide a rotation detection output that can improve detection accuracy, and furthermore, the detection pulse train signals Pa, P
If either b or Pc becomes abnormal, other detection pulse train signals that are not abnormal are effectively used to automatically take appropriate measures. In addition, a forward/reverse motion determining section 80 provided in the logic circuit block 28 provides a signal for determining whether the vehicle is moving forward, backward, or stopped.

That is, as shown in FIG.
D-flip-flops 81, 82° 83.84.
85 and 86 and 6 AND gate circuits 91.92.9
3.94, 95 and 96, and two OR gate circuits 97 and 98.

Then, the detected pulse train signal Pa is directly applied to the data terminals of the D-flip-flops 81 and 82 and the clock terminal C of the D-flip-flop 85, and the level is inverted to the clock terminal C of the D-flip-flop 86. The detected pulse train signal pb is supplied to the data terminals of the D-flip-flops 83 and 84, ! = D- directly to the clock terminal C of the flip-flop 81, and D-
The level of the detection pulse train signal Pc is inverted and supplied to the clock terminal C of the flip-flop 82.
- Data terminals of flip-flops 85 and 86 and D
- directly to the clock terminal C of the flip-flop 83;
Further, the level is inverted and supplied to the clock terminal C of the D-flip-flop 84.

The signals Fa, Fb and Fc obtained at the respective output terminals Q of the D-flip-flops 81.83 and 85 are applied to one input terminal of each of the AND gate circuits 91.93 and 95. Signals Ra, Rb and Rc obtained at output terminals Q of 82.84 and 86, respectively, are supplied to input terminals of AND gate circuits 92.94 and 96, respectively, and D-flip-flops 81. The signals Fa', Fb' and Fc' obtained at the inverting output terminal σ of each of 83 and 85 are input to the other input terminal of each of AND gate circuits 92, 94 and 96, and
The signals Ra', Rb'' and Rc available at the inverting output terminals Q of the D-flip-flops 82, 84 and 86, respectively.
l is supplied to the other input terminal of each of the AND gate circuits 91.93 and 95, and output signals Fl, F2 and F3 obtained from the AND gate circuits 91.93 and 95, respectively, are supplied to the OR gate circuit 97. Circuit 92.
Output signals R2, Rz and R3 obtained from 94 and 96, respectively, are supplied to an OR gate circuit 98.

When the vehicle is moving forward, the forward/backward motion determining section 80 having such a configuration is used for the period T in FIGS. 6A, B, and C described above.

, and period T in FIGS. 7A, B, and C, detection pulse train signals Pa, Pb, and Pc having a phase difference of 2π/3 are sequentially supplied.

At this time, D-flip-flops 81, 83 and 85
The signals Fa, Fb and F obtained from the respective output terminals Q of
c, and D-flip-flops 82.84 and 86
The signals Ra'', Rb obtained from the respective inverting output terminals of
' and Rc'' take a high level, and signals F1, F2 and F3 that take a high level are obtained from AND gate circuits 91, 93 and 95, respectively. On the other hand, D-flip-flops 81, 83 and 85 each inverted output terminal σ
Fa', Fb' and Fc' obtained from
- Ra, Rb and Rc obtained from the output terminals Q of flip-flops 82, 84 and 86, respectively, take a low level, and R+, Rt and R3, which take a low level from AND gate circuits 92, 94 and 96, respectively; is obtained.

As a result, the signal Ma that continuously takes a high level is obtained from the OR gate circuit 97, and the OR gate circuit 9
8, a signal Mb that continuously takes a low level is obtained.

On the other hand, when the vehicle is reversing, the rotating disk 14
rotates in the opposite direction to the forward movement, and the detection pulse train signals Pa,
Pb and Pc have a mutual phase advance/delay relationship that is opposite to that during forward movement. Therefore, P c
−* P b −+ P a sequentially in the order of 2π/3
Detection pulse train signals Pa, Pb, and Pc having a phase delay of 1 are supplied.

For this reason, the D-flip-flops 81, 83 and 85
The signals Fa, Fb and F obtained from the respective output terminals Q of
c, and D-flip-flops 82.84 and 86
The signals Ra'', Rb obtained from the respective inverting output terminals σ
' and Rc' take a low level, and signals F1, F2, and F3 that take a low level are obtained from the AND gate circuits 91, 93, and 95, respectively, and the D-flip
Signals Fa', Fb'' and Fc'' obtained from the inverting output terminals Q of flops 81, 83 and 85, respectively, and D
- The signals Ra, Rb and Rc obtained from the output terminals Q of the flip-flops 82, 84 and 86 take a high level, and the signal R1 takes a high level from the AND gate circuits 92, 94 and 96, respectively. , R2 and R3 are obtained. As a result, a signal Ma that continuously takes a low level is obtained from the OR gate circuit 97, and a signal Mb that continuously takes a high level is obtained from the OR gate circuit 98.

Furthermore, when the vehicle is stopped, the detection pulse train signal P
a, Pb, and Pc are all continuously at low levels, or one or two of them are continuously at high levels and the others are at continuously low levels, so Signals Ma and Mb obtained from OR gate circuits 97 and 98, respectively, are both continuously at a low level.

In this way, the signals Ma and Mb, which have a reverse level relationship between high and low levels when the vehicle is moving forward and backward, and which both take a low level when the vehicle is stopped, are used to determine whether the vehicle is moving forward or backward. As a signal, output terminals 28c and 28d of the logic circuit block 28, as shown in FIG.
A control unit that requires a forward/reverse motion determination signal, such as an electric brake (parking brake) control unit.

It is distributed and supplied to the 4WS (four-wheel steering) control unit, etc. This allows the electric brake control unit.

In the 4WS control unit, etc., the supplied signal Ma
and the advancement of the vehicle depending on the level of Mb.

Operation control corresponding to the backward and stopped states is performed.

As described above, the forward/reverse motion determining section 80 is adapted to send signals Ma and Mb as vehicle forward/reverse motion determination signals.
In this case, as mentioned above, detection pulse train signals Pa, Pb, and Pc are all obtained properly, not only during normal times (
Even in an abnormal situation where any one of the detection pulse train signals Pa, Pb, and Pc cannot be properly obtained, the forward, backward, and stopped states of the vehicle are determined.

For example, if the detected pulse train signal Pa continuously takes a high level or a low level when the vehicle moves forward or backwards, the signals F1 and Ro obtained from the AND gate circuits 91 and 92 both take a low level. However, the signals F2. Since R1, R3, and R3 take the same level as in the normal state, the signals Ma and Mb obtained from the blue gate circuits 97 and 98, respectively, take the same level as in the normal state.

In addition, when the vehicle moves forward or backward, the detection pulse train signal p
Even when b or pc continuously takes a high level or a low level, the OR gate circuits 97 and 98 The signals Ma and Mb obtained from the above are respectively at the same level as in normal times.

Therefore, the detection pulse train signal P
Even if an abnormality occurs in any of a, Pb, and Pc, as in normal conditions, the signal Ma takes a high level when the vehicle is moving forward, and takes a low level when reversing and stopping, and the signal Ma takes a high level when the vehicle is moving forward and when it is stopped. A signal Mb is obtained which takes a low level when the vehicle is stopped and takes a high level when the vehicle is reversing, thereby determining whether the vehicle is moving forward, backward, or stopped.

In addition, in the above-mentioned example, the rotating disk 14 has the first. Second and third through holes 16a.

16b and 16C are arranged in an array, and photoelectric detectors 24A, 24B, and 24C are used in the detection signal generation section that obtains a detection pulse train signal according to the arrangement of the detected parts. The device is not limited to one having a combination of a detection portion provided as a through hole in the rotary disk 14 and a photoelectric type detector, and a light reflecting portion may be provided in the rotary disk 14 instead of the through hole. It may also have a combination of this light reflecting section and a photoelectric detector that irradiates the light and receives the reflected light. Even if various other detected parts such as magnetic parts are arranged and formed, and the detection signal generating part is equipped with various detectors other than the photoelectric type detector, such as an electromagnetic type detector, for example, good.

Furthermore, in the above example, the detection signal generation section includes three photoelectric detectors 24A, 24B, and 24C, but the detection signal generation section in the rotation detection device according to the present invention includes three photoelectric detectors 24A, 24B, and 24C. including but not limited to detectors of
It may be equipped with three or more detectors,
Generally, it is equipped with n detectors (n is a positive integer of 3 or more), and the n detectors have first and second detection obtained from two adjacent ones of them. The pulse train signals are arranged so as to have a mutual phase difference of substantially 2π/n.

(Effects of the Invention) As is clear from the above description, according to the rotation detection device according to the present invention, a plurality of detection units are arranged close to a rotating member that rotates depending on the rotating body whose rotational state is to be detected. A plurality of detection pulse train signals are obtained from each of the parts according to the arrangement of the parts to be detected arranged on the rotating member and have a predetermined mutual phase difference. a rotation detection output signal corresponding to the rotational speed of the rotating body to be detected;
A signal corresponding to the rotational direction of the rotating body to be detected or a signal indicating an abnormality in each detection pulse train signal is formed based on a plurality of detection pulse train signals, and these signals are distributed and supplied to a plurality of control units. Therefore, the rotation of the rotating body to be detected can be detected with high precision, and various signals can be obtained based on multiple detection pulse train signals that enable such high precision rotation detection. The logic circuit section of the present invention can be used efficiently, the duplication of the logic circuit section can be avoided, and the wiring of each section related to the logic circuit section can be simplified.
This makes it possible to reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a schematic perspective view showing the entirety of an example of a rotation detection device according to the present invention, and FIG. 2 is a partial side view for explaining a photoelectric detector used in the example shown in FIG. 1. 3 is a block diagram showing an example of a logic circuit block used in the example shown in FIG. 1, FIG. 4 is a block diagram showing a specific configuration example of the output sending section shown in FIG. 3, and FIG. are block diagrams showing specific configuration examples of the abnormality detecting section and the abnormality countermeasure signal forming section shown in FIG. 3, and FIGS. 6A-P and 7A-P.
3 is a waveform diagram used to explain the operation of the logic circuit block shown in FIG. 3, and FIG. 8 is a block diagram showing a specific example of the configuration of the forward/reverse motion determination section shown in FIG. 3. In the figure, 10 is a built-in disc part, 14 is a rotating disc, 16a, 1
6b and 16C are the 1st. second and third through holes, 20
2 is a detector fixing part, 21 is a detector support member, 23 is a circuit accommodating part, 24A, 24B and 24C are detectors, 28 is a logic circuit block, 30 is an output sending part, 30A is a detection output forming part, and 30B is an output 40 is an abnormality detecting section, 50 is an abnormality countermeasure signal forming section, and 80 is a forward/reverse motion determining section. Figure 2

Claims (1)

[Claims] A plurality of detected parts are arranged in an array surrounding the center of rotation,
A rotating member that rotates in accordance with the rotating body whose rotational state is to be detected, and n pieces (n is 3
or more positive integer) are arranged so that the first and second detection pulse train signals obtained from two adjacent detectors have a mutual phase difference of substantially 2π/n, and a detection signal generating section formed by partially overlapping each detection pulse forming the first detection pulse train signal and each detection pulse forming the second detection pulse train signal; a logic circuit section that forms a signal corresponding to the rotational speed or direction of rotation of the rotating body or a signal representing an abnormality in the detection pulse train signal based on the detection pulse train signal obtained from the detection signal generating section; A rotation detection device comprising a detector support member that supports a generator and the logic circuit unit so as to be integrated with each other.