JPH0833406B2 - Information signal forming and supplying device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention obtains an information signal corresponding to a vehicle speed based on a rotating body placed in a rotating state according to a vehicle speed in a vehicle, and provides the information signal to the vehicle. The present invention relates to an information signal forming / supplying device for supplying to a control unit.

(Prior Art) In a vehicle, various rotation detection devices for detecting a rotation state of an output shaft of a transmission and the like are put into practical use for measuring a vehicle speed and the like. The general type of such rotation detection device is
A rotating disk that rotates with or in conjunction with the rotating body whose rotational state is to be detected is provided, and the rotating disk has a large number of light-reflecting parts, light-transmitting parts, or light-receiving parts along the circumferential direction. It is assumed that the detected parts such as magnetic parts are arranged in an annular shape, and the detector that optically or magnetically detects the detected parts and generates a detection signal according to the arrangement of the detected parts rotates. It is installed and configured on a disc so that the frequency or phase of the detection signal obtained from the detector will correspond to the rotating state of the rotating body when the rotating body whose rotation state is to be detected rotates. To be done.

In the rotation detection device provided with such a rotating disc, the detection accuracy depends on the fine density of the detected portions arranged in a ring on the rotating disc.
When each detected part is a light-reflecting part or a light-transmitting part such as a through hole, there is a processing limit when forming a large number of light-reflecting parts or light-transmitting parts on the rotating disk, and the fine density of the parts should be limited. It becomes difficult to raise it sufficiently. Further, if each light reflecting portion or light transmitting portion is made narrow in order to increase the fine density, there is a disadvantage that the S / N ratio of the detection signal obtained from the detector is lowered.

For this reason, some measures have been proposed for improving the detection accuracy while keeping the fine density of the light reflecting portions or light transmitting portions arranged on the rotating disk within a predetermined range. As described in Japanese Laid-Open Patent Publication No. 55-172856, a rotating disc is provided with a circular array of light reflecting portions or light transmitting portions in the radial direction of the rotating disc so that the light reflecting inside and outside of the rotating disc is doubled. The two optical detectors corresponding to each of the circular sections of the light-transmitting section or the light-transmitting section, and combining the detection signals obtained from the respective optical detectors, as a result, the detection accuracy is substantially improved. It is known to obtain different detection outputs.

However, as described above, in the case where the rotation detecting device including the rotating disc is configured such that the annular array of the inner and outer light reflecting portions or the light transmitting portions is doubly formed in the rotating disc. In addition, the manufacturing process of the rotating disk becomes complicated and it becomes difficult to obtain the rotating disk, and the rotating disk tends to increase in size. As a result, the manufacturing cost of the device increases and The size of the entire device will increase.

Therefore, a plurality of detected parts are formed in an annular array surrounding the center of rotation, and a rotating disk that rotates with or in association with the rotating body whose rotational state is to be detected, and a proximity to this rotating disk. And a plurality of detectors that generate a detection pulse train signal according to the arrangement of the detected parts, and the detection pulse train signals obtained from each of the plurality of detectors have a predetermined mutual phase difference. The rotation detection output signal, which is arranged so that the detection pulse train signals are combined with each other, improves the detection accuracy. A rotation detection signal generator designed to be obtained under the circumstances is considered.

Then, each detection pulse train signal from the rotation detection signal generator provided with such a rotating disk and a plurality of detectors from which a plurality of detection pulse train signals having a predetermined mutual phase difference is obtained, requires them in common. Is supplied to a plurality of control units such as a meter control unit, an anti-lock brake control unit, an auto cruise control unit, etc., and each control unit rotates on the basis of a plurality of detection pulse train signals. A rotation detection output signal indicating the rotation speed of the body and a signal indicating the rotation direction of the rotating body whose rotation state is to be detected are obtained, and the required control is performed for each.

(Problems to be Solved by the Invention) As described above, a predetermined detection output signal is supplied to each of the plurality of control units, and in each control unit, a necessary signal based on the supplied detection output signal is generated. In the formed control system, each of the plurality of control units incorporates a signal processing unit for forming a necessary signal, for example, a signal corresponding to the vehicle speed, based on the detection output signal. To be taken. That is, a plurality of control units, which are configured to perform respective control operations by commonly using the detection output signal, are individually provided with signal processing units for obtaining the same signal from the commonly supplied detection output signals. Therefore, the signal processing units are redundantly installed. Such overlapping installation of the signal processing units is not only unreasonable in that the number of signal processing units more than the truly required number is installed, and each is inefficiently used, and each signal processing The wiring for supplying signals to the parts is complicated, and the amount of wiring is increased, which is inconvenient.

In view of such a point, the present invention includes a detection unit that generates a detection output signal regarding the rotation state of the rotating body placed in the rotation state according to the vehicle speed in the vehicle, and based on the detection output signal from the detection unit. A signal processing unit for forming an information signal corresponding to a vehicle speed required in a control unit installed in the vehicle, and a signal supply unit supplying the information signal formed by the signal processing unit to the control unit, It is an object of the present invention to provide an information signal forming / supplying device that can be used in a highly efficient state and that simplifies wiring for supplying a signal to a control unit.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the information signal forming / supplying device according to the present invention is an electronic meter control circuit unit in an electronic meter device installed to display the state of a vehicle. And a detection unit that detects a rotation state of a rotating body placed in a rotation state according to a vehicle speed in the vehicle to generate a detection output signal, and an electronic meter control circuit unit in the electronic meter device is provided from the detection unit. A signal processing unit that performs a predetermined signal processing on the obtained detection output signal to form an information signal corresponding to the vehicle speed of the vehicle, and a signal that supplies the information signal obtained from the signal processing unit to a control unit installed in the vehicle It is configured to include a supply unit.

(Operation) In the information signal forming / supplying device according to the present invention configured as described above, the detection output signal from the detection unit is supplied to the signal processing unit included in the electronic meter control circuit unit to perform signal processing. In the section, an information signal corresponding to the vehicle speed is formed based on the detection output signal from the detection section. Then, an information signal corresponding to the vehicle speed from the signal processing unit is supplied to the control unit by the signal supply unit included in the electronic meter control circuit unit.

As a result, based on the detection output signal from the detection unit, the signal processing unit that forms an information signal corresponding to the vehicle speed required in the control unit, and the signal supply unit that supplies the information signal to the control unit, The internal circuit of the electronic meter control circuit unit in the electronic meter device that is installed to display the state of the vehicle is used and configured without being installed as a separate additional circuit unit. Installation is avoided and it can be used efficiently. Moreover, as a result, the wiring of each part is simplified.

(Example) Hereinafter, the Example of this invention is described with reference to drawings.

FIG. 1 shows an example of an information signal forming / supplying device according to the present invention together with an electronic meter device for a vehicle to which it is applied. This example is a rotating body placed in a rotating state according to the vehicle speed in the vehicle, for example, to form a rotation detecting device for detecting the rotating state of the output shaft of the transmission, the disk built-in portion 10, and A logic circuit block 28 incorporated in a CPU (central control unit) 104 included in an electronic meter control circuit unit 100 in an electronic meter device of a vehicle.

The disk built-in section 10 detects the rotary disk 14 and the detected parts provided in relation to the rotary disk 14 and provided on the rotary disk 14, and three detectors 20A, 20B and 20C and is specifically configured as shown in FIG. 2, for example.

An example of the disc built-in portion 10 shown in FIG. 2 is provided with a case 11 represented by a chain line.
For example, a shaft 13 to which a cable 12 for transmitting the rotation of the output shaft of the transmission is connected, and a rotating disc 14 fixed to the shaft 13 are arranged. In this rotating disk 14,
A large number of substantially rectangular through holes 16 of the same size are arranged in an annular shape so as to surround the center of rotation of the rotating disk 14 at intervals equal to the width of each through hole 16. Each of the through holes 16 serves as a light transmitting portion as a detected portion, and a light blocking portion 18 is provided between two adjacent through holes 16.

Three photoelectric type detectors 20A, 20B and 20C are arranged around the center of rotation of the rotating disk 14 and are at equal intervals, that is, rotation of the rotating disk 14 About the center 12
The detectors 20A, 20B, and 20C are arranged at an angle of 0 °, and are fixed to the inner surface of the case 11.

Each of the detectors 20A, 20B, and 20C has the same configuration. For example, as shown in FIG. 3 as the detector 20A, it is formed in a U shape as a whole, and its upper side portion 21a and lower side portion 21a are formed. It is said that the rotary disc 14 is sandwiched by 21b. Rotating disc 1
A light emitting element 22 such as a light emitting diode is provided inside the upper side portion 21a that is located above 4, and inside the lower side portion 21b that is located below the rotating disk 14, A light receiving element 24 such as a phototransistor is provided, and the light emitting element 22 and the light receiving element 24 face each other via an annular array portion of the through holes 16 provided in the rotating disk 14. Therefore, in a state where the light blocking portion 18 is located between the light emitting element 22 and the light receiving element 24, the light from the light emitting element 22 is blocked by the light blocking portion 18 and does not reach the light receiving element 24, and the light emitting element 22 and With the through hole 16 positioned between the light receiving element 24 and the light receiving element 24, the light from the light emitting element 22 reaches the light receiving element 24 through the through hole 16.

The light-receiving element 24 generates a signal in response to the arrival of light from the light-emitting element 22, whereby the light-receiving element 24 generates a detection pulse corresponding to each through hole 16 when the rotating disc 14 rotates. From the light receiving element 24, a detection pulse train signal corresponding to the arrangement of the through holes 16 is obtained as a detection output signal for the detected portion.

In this case, the annular array of the through holes 16 provided in the rotating disk 14, each of the detectors 20A, 20B and 20C arranged at an angle of 120 ° with respect to the center of rotation of the rotating disk 14, respectively,
When the rotary disk 14 is rotated, two adjacent ones of them, that is, the detectors 20A and 20B, the detectors 20B and 20C, or
The two detection pulse train signals obtained from the respective light receiving elements 24 of the detectors 20C and 20A are arranged at positions where they have a mutual phase difference of substantially 2π / 3, and these 2 It is set such that each detection pulse forming one of the two detection pulse train signals and each detection pulse forming the other one have portions where they overlap each other.

Each of the detectors 20A, 20B, and 20C is connected with three wires W in a wire harness arranged on the vehicle body, and the detector 20 is connected to the detector 20 through the wires W.
Power is supplied to the light emitting element 22 in each of A, 20B and 20C, and power is supplied from the battery to the light receiving element 24 in each of the detectors 20A, 20B and 20C and the light receiving element 24 thereof.
The detection pulse train signal is derived from. In this way, the detectors 20A, 20B and 2 which generate the respective detection pulse train signals are
The detection portion is formed by 0C.

The rotating disk 14 is housed in the case 11 as described above, and the three detectors 20A, 20B and 2 are provided on the inner surface of the case 11.
In the disk built-in portion 10 formed by fixing 0C, each of the detectors 20A, 20B and 20C forming the detection portion is connected to the electronic meter control circuit portion 100.

The electronic meter control circuit unit 100 is configured using a microcomputer, for example, the detection signal Sn from the engine speed sensor 106, the detection signal Sf from the fuel gauge 108, the detection signal Ss from the water temperature sensor 110, etc. Detection signals, or signals from various switches (not shown) are supplied.

Then, for example, if the detection signal Sn is the interface unit 11
The detection signals Sf and Ss are supplied to the CPU 104 via 1 and via the A / D converter 113. In the CPU 104, for example, an engine speed signal C _N representing the engine speed, a fuel signal C _F representing the remaining fuel amount, and a water temperature signal C _S representing the engine cooling water temperature are formed based on the supplied input signals. To be done. Then, the engine speed signal C _N , the fuel signal C _F, and the water temperature signal C _S obtained from the CPU 104 are supplied to the drive unit 115, and the drive unit 115 outputs the engine speed signal C _N , the fuel signal C _F, and the water temperature signal C _S. Display signals C _N ′, C _F ′ and C _S ′ based on
Is supplied to. The display unit 120 is configured to perform digital display using, for example, a light emitting diode, and according to the supplied display signals C _N ′, C _F ′ and C _S ′, the engine speed, the remaining fuel amount, and Displays engine cooling water temperature.

In addition, the CPU 104 has 3
The detection pulse train signals Pa, Pb and Pc respectively obtained from the individual detectors 20A, 20B and 20C are also supplied, and in the logic circuit block 28 constituting the signal processing unit incorporated in the CPU 104,
Based on the detected pulse train signals Pa, Pb and Pc, it indicates the abnormality of each of the rotational speed of the output shaft of the transmission, that is, the signal Pn or Cx 'which is an information signal corresponding to the vehicle speed, and the detected pulse train signals Pa, Pb and Pc. An abnormality detection signal Pe, which is an information signal,
In addition, signals Ma and Mb which are information signals for discriminating the forward, backward and stop states of the vehicle are formed. Then, the signal Pn or Cx ′ obtained from the logic circuit block 28 is applied to the driving unit 11
5, the driving unit 115 also obtains the display signal C _P ′ based on the signal Pn or Cx ′ and supplies it to the display unit 120, and the vehicle speed corresponding to the display signal C _P ′ is displayed on the display unit 120. Is displayed.

Furthermore, the signal Pn or Cx ′ obtained from the logic circuit block 28 is the same as the other signals obtained from the logic circuit block 28, that is, the abnormality detection signal Pe and the signals Ma and Mb. The signal Pn or Cx ′ sent from the output terminal is sent to the antilock brake control unit etc., the abnormality detection signal Pe is sent to the lamp control unit etc. which controls the blinking of the warning lamp, and the signals Ma and Mb are the electric brakes. It is supplied to the (parking brake) control unit and the 4WS (four-wheel steering) control unit.

In this way, the detection pulse train signals Pa, Pb and Pc are formed in the CPU 104 of the electronic meter control circuit unit 100 installed to display the engine speed, the remaining fuel amount, the cooling water temperature of the engine, the vehicle speed and the like. On the basis of the above, a signal Pn or Cx ′ corresponding to the vehicle speed, an anomaly detection signal Pe representing the anomaly of each of the detection pulse train signals Pa, Pb and Pc, and signals Ma and Mb for discriminating the forward, backward and stop states of the vehicle are formed. The logic circuit block 28 has a configuration as shown in FIG. 4, for example.

The specific configuration example of the logic circuit block 28 shown in FIG. 4 includes a detection output forming unit and an output selection unit to which the detection pulse train signals Pa, Pb and Pc obtained from the detectors 20A, 20B and 20C are supplied, respectively. The output transmission unit 30, the abnormality detection unit 40, the abnormality countermeasure signal formation unit 50, and the forward / backward movement determination unit 80 are included. Then, the output sending unit 30 is also supplied with the abnormality detection signal Pe from the abnormality detection unit 40 and the abnormality countermeasure signal Cx from the abnormality countermeasure signal forming unit 50, and the signals Pr and Pd from the abnormality detection unit 40 are abnormal. It is supplied to the countermeasure signal forming unit 50.

As shown in FIG.
The first AND gate circuit 31, to which the detection pulse train signal Pa from A and the detection pulse train signal Pb from the detector 20B are supplied,
The second AND gate circuit 32 to which the detection pulse train signal Pb from the detector 20B and the detection pulse train signal Pc from the detector 20C are supplied, the detection pulse train signal Pc from the detector 20C and the detector 20
A third AND gate circuit 33 to which the detection pulse train signal Pa from A is supplied, and each AND gate circuit 31, 32 and 3
The signal Pn obtained from the OR gate circuit 34 is composed of an OR gate circuit 34 to which the signals P ₁ , P ₂ and P ₃ obtained from ₃ are supplied.
A detection output forming unit 30A that forms a rotation detection output is formed. Further, the abnormality countermeasure signal Cx from the abnormality countermeasure signal forming section 50 is supplied, and the frequency multiplying circuit 36 for multiplying the input signal frequency by 3 and the signal Pn obtained from the OR gate circuit 34 of the detection output forming section 30A are supplied. Fixed contact 35a,
The fixed contact 35b to which the signal Cx 'obtained by multiplying the frequency of the abnormality countermeasure signal Cx by the frequency multiplication circuit 36 by 3 is supplied,
Further, the output selection unit 30B is formed, which is controlled by the abnormality detection signal Pe obtained from the abnormality detection unit 40 and includes the switch circuit 35 having the movable contact 35c selectively connected to one of the fixed contacts 35a and 35b. There is.

As shown in FIG. 6, the abnormality detecting section 40 includes detectors 20A,
An OR gate circuit 41 and an AND gate circuit 42 to which the detected pulse train signals Pa, Pb, and Pc from 20B and 20C, respectively, are supplied.
And the signal Pr obtained from the OR gate circuit 41 is directly supplied, and the signal Pd obtained from the AND gate circuit 42 is supplied.
Is supplied through the inverter 43 to the AND gate circuit 44
And the output signal of the AND gate circuit 44 is used as the abnormality detection signal Pe.

In the abnormality countermeasure signal forming section 50, as shown in FIG. 6, the detection pulse train signals Pa, Pb and Pc are respectively supplied to the set terminal S and the signal Pr obtained from the OR gate circuit 41 of the abnormality detecting section 40 is supplied. The signal Pr 'obtained by the level inversion by the inverter 57 is supplied to the RS flip-flops 51, 52 and 53 supplied to each reset terminal R and the output terminals Q of these RS flip-flops 51, 52 and 53. The signals S ₁ , S ₂ and S ₃ to be obtained are delayed by the delay circuits 51a, 52a and 53a for a minute time to obtain signals S ₁ ′, S ₂ ′ and
S ₃ ′ is supplied to the data terminal D and the signal Pr
Is supplied to each clock terminal C and the detection pulse train signals Pa, Pb and Pc are level-inverted by inverters 67, 68 and 69, respectively, and signals Pa 'and Pb' are obtained. RS flip-flops 61, 62 and 63, to which the signal Pd obtained from the AND gate circuit 42 of the abnormality detecting section 40 is supplied to each reset terminal R as well as the RS flip-flops 61, 62 and 63. The signal S obtained at the output terminals Q of the flip-flops 61, 62 and 63, respectively.
Signals S ₇ ′, S ₈ ′ and S ₉ ′ obtained by delaying ₇ , S ₈ and S ₉ by delay circuits 61 a, 62 b and 63 c are supplied to the data terminal D and a signal Pd is supplied. D-flip-flops 64, 65 and 6 supplied to each clock terminal C
6 and the signals S ₄ and S ₁₀ obtained from the D-flip-flops 54 and 64, respectively, are supplied to the OR gate circuit 58 by D
The signal obtained from each of the flip-flops 55 and 65
S ₅ and S ₁₁ are provided to the OR gate circuit 59 and signals S ₆ and S ₁₂ are obtained from D-flip-flops 56 and 66, respectively.
Are supplied to the OR gate circuit 60, respectively.

In addition, the signal S ₄ or S ₁₀ from the OR gate circuit 58
Is directly supplied to the AND gate circuit 71, level-inverted by the inverter 77 and supplied to the AND gate circuit 72, and the signal S ₅ or S ₁₁ from the OR gate circuit 59 is directly supplied to the AND gate circuit 72 and the inverter 78. Level is inverted by the signal and supplied to the AND gate circuit 73, and the signal S ₆ or S from the OR gate circuit 60 is supplied.
₁₂ is directly supplied to the AND gate circuit 73, the level thereof is inverted by the inverter 79, and the result is supplied to the AND gate circuit 71. Further, the AND gate circuits 71, 72 and 73 are supplied with the detection pulse train signals Pa, Pb and Pc, respectively.

Then, the signals C ₁ , C ₂ and C ₃ obtained from the AND gate circuits 71, 72 and 73, respectively, are supplied to the OR gate circuit 76, and the output signal of the OR gate circuit 76 is used as the abnormality countermeasure signal Cx.

Under the combination of the disk built-in section 10 and the logic circuit block 28 configured as described above, the rotating disk 14 is rotated according to the vehicle speed when the vehicle is running, and the detector 20A, In the state where both 20B and 20C are operating normally, from the detectors 20A, 20B and 20C, respectively,
7A, B, and C, the period T ₀ before the time point t ₁ , and
As shown in Figure 8 A, the time t ₄ the previous period T ₄ in the B and C, sequentially 2 [pi / 3, i.e., the detection pulse train signal Pa which is assumed to have a phase difference of each 120 °, Pb and Pc
Is obtained. These detection pulse train signals Pa, Pb and Pc
Are two of them with a mutual phase difference of 120 °,
That is, the detection pulse train signals Pa and Pb, Pb and Pc, or each detection pulse forming one of Pc and Pa and each detection pulse forming the other, the overlapping portion, that is, at the same time high. It is supposed to have a part that takes a level.

The detection pulse train signals Pa, Pb and Pc are respectively supplied to the first, second and third AND gate circuits 31, 32 and 3 in the detection output forming section 30A of the output transmitting section 30 in the manner as described above.
Supplied to 3. Then, the signal P ₁ formed from the first AND gate circuit 31 is a train of pulses corresponding to the overlapping portion of each detection pulse forming the detection pulse train signal Pa and each detection pulse forming the detection pulse train signal Pb.
From the second AND gate circuit 32, each detection pulse forming the detection pulse train signal Pb and the detection pulse train signal Pc are obtained.
A signal P ₂ formed by a train of pulses corresponding to the overlapping portion with each of the detection pulses forming the detection pulse train signal is obtained from the third AND gate circuit 33.
A signal P ₃ is obtained which is formed by a train of pulses corresponding to the overlapping portion of each detection pulse forming Pc and each detection pulse forming the detection pulse train signal Pa. These signals
P ₁ , P ₂ and P ₃ are supplied to the OR gate circuit 34, and the signals P ₁ , P ₂ and P ₃ are synthesized from the OR gate circuit 34, and are obtained during the period T ₀ in FIG. A signal Pn which is a pulse train signal as shown in the period T ₄ in FIG. 8D is obtained. The pulse train signal forming this signal Pn is 3 times the frequency of each of the detection pulse train signals Pa, Pb and Pc.
The frequency is doubled, and this is the rotation detection output.

Therefore, by this rotation detection output, as compared with the case where the detection pulse train signal Pa, Pb or Pc obtained according to the annular arrangement of the through holes 16 provided in the rotating disk 14 is directly used as the rotation detection output, The rotation detection is performed under the increased detection accuracy.

As described above, in the state where each of the detection pulse train signals Pa, Pb, and Pc is normally obtained from the detection output forming unit 30A and the signal Pn having a frequency three times that frequency is obtained, Also in the OR gate circuit 41 and the AND gate circuit 42 in the abnormality detection unit 40 of the circuit block 28, the period T ₀ in FIGS. 7A, 7B and 7C described above, and FIGS.
The detection pulse train signals Pa, Pb and Pc shown in the period T ₄ in C and C are supplied. As a result, the OR gate circuit 41 and the AND gate circuit 42 take the high level h as shown in the period T ₀ in FIGS. 7E and F and the period T ₄ in FIGS. 8E and 8F, respectively. Signal Pr
And a signal Pd taking a low level 1 is obtained. The signal Pr having the high level h is unchanged, and the signal Pd having the low level 1 is converted into a signal having the high level h by the inverter 43 and supplied to the AND gate circuit 44. From the AND gate circuit 44, Period T ₀ in FIG. 7G and FIG. 8G
The abnormality detection signal Pe having the high level h is obtained as shown in the period T ₄ in.

In this way, in the state where any of the detection pulse train signals Pa, Pb and Pc from the detectors 20A, 20B and 20C are properly obtained, from the OR gate circuit 41 and the AND gate circuit 42 in the abnormality detection unit 40. Obtained signals Pr and Pd
, Respectively, take the high level h and the low level 1, and as a result, the abnormality detection signal Pe takes the high level h.

Then, while the abnormality detection signal Pe having this high level is supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30, the blinking control of the warning lamp is controlled from the output terminal of the electronic meter control circuit unit 100. The lamp control unit is supplied to the performing lamp control unit, and the lamp control unit holds the warning lamp in the off state when the abnormality detection signal Pe has a high level.

As described above, when the detection pulse train signals Pa, Pb, and Pc are normally obtained, in the abnormality countermeasure signal forming unit 50, the set terminals S of the RS flip-flops 51, 52, and 53 are connected to the set terminals S of FIG. The detection pulse train signals Pa, Pb and Pc shown in the period T ₀ in A, B and C and the period T ₄ in FIGS.
The set terminal S of each of the flip-flops 61, 62 and 63
The signals Pa ', Pb' and Pc 'obtained from the inverters 67, 68 and 69 based on the above-mentioned detected pulse train signals Pa, Pb and Pc.
Is supplied.

At this time, the reset terminal R of each of the RS flip-flops 51, 52 and 53 is supplied with the high level signal Pr from the abnormality detection section 40 after being inverted to a low level by the inverter 57, and the RS flip-flops 51, 52 and 53 are supplied. From the respective output terminals Q of the flops 51, 52 and 53, the signals S ₁ , S which continuously take the high level h
₂ and S ₃ are obtained and these signals S ₁ , S ₂ and S ₃ are continuously passed through the delay circuits 51a, 52a and 53a, respectively, as shown in the period T ₀ in FIGS. 7H, I and J. signals S ₁ taking high-level ', S _2' is supplied to the data terminal D of each of the and S ₃ 'as D- flip-flops 54, 55 and 56. D
A signal Pr having a high level h is supplied to the respective clock terminals C of the flip-flops 54, 55 and 56 as a signal having a low level 1 continuously by level inversion, and the D-flip-flops 54, 55 And 56 at the respective output terminals Q,
Signals S ₄ , S ₅ and S ₆ having a low level 1 are obtained, as shown in the period T ₀ in FIGS. 7K, L and M, which are respectively in one of the OR gate circuits 58, 59 and 60. It is supplied to the input terminal.

At this time, the RS flip-flops 61, 62 and 6 whose signals Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
A signal, which is obtained from the abnormality detection unit 40 and continuously takes the low level 1 as shown in the period T _{0 in} FIG. 7F and the period T ₄ in FIG. Pd is supplied, RS to the output terminal Q of each of flip-flops 61, 62 and 63 continuously signal S ₇ taking high level h, S ₈ and S ₉ are obtained, these signals S _7, S ₈ and S ₉ pass through delay circuits 61a, 62a and 63a, respectively, and are shown in FIG.
Are applied to the respective data terminals D of D-flip-flops 64, 65 and 66 as signals S ₇ ′, S ₈ ′ and S ₉ ′ which are continuously high, as shown in the period T ₄ in FIG. . A signal Pd having a low level 1 is continuously supplied to the clock terminals C of the D-flip-flops 64, 65 and 66, and the signals Pd of the D-flip-flops 64, 65 and 66 are supplied to the respective output terminals Q of the D-flip-flops 64, 65 and 66. , Signals S ₁₀ , S ₁₁ and S ₁₂ having a low level 1 are obtained as shown in period T ₄ in FIGS. 8 K, L and M, which are the other of OR gate circuits 58, 59 and 60, respectively. Is supplied to the input terminal of.

Therefore, the output signals of the OR gate circuits 58, 59, and 60 are all at the low level 1, and therefore, the AND gate circuits 71, 72, and 73 output the signals shown in FIG.
Signals C ₁ , C ₂ and C ₃ having a low level 1 as shown in the period T ₀ in N, O and P and the period T ₄ in N, O and P in FIG. 8 are obtained, and the OR gate circuit is obtained. The abnormality countermeasure signal Cx obtained from 76 is continuously low level.

The abnormality countermeasure signal Cx that takes this low level is output by the output transmission unit 30.
Is supplied to the frequency multiplication circuit 36 in the output selection unit 30B.

In this case, the control terminal of the switch circuit 35 of the output transmission unit 30 is supplied with the high level abnormality detection signal Pe obtained from the abnormality detection unit 40, so that the movable contact 35c of the switch circuit 35 is fixed. A signal Pn having a frequency three times higher than that of each of the detection pulse train signals Pa, Pb, and Pc, which is connected to 35a and is obtained from the detection output forming unit 30A, is sent from the movable contact 35c of the switch circuit 35 as a rotation detection output. It

The signal Pn sent from the output sending unit 30 is supplied to the drive unit 115 of the electronic meter control circuit unit 100 to be used for the vehicle speed display on the display unit 120, and a plurality of output terminals of the electronic meter control circuit unit 100 can be used. It is distributed and supplied to the control unit. As a result, the detector 20 placed in the disc built-in section 10
When appropriate detection pulse train signals Pa, Pb, and Pc are obtained from A, 20B, and 20C, respectively, each control unit is supposed to perform highly accurate control according to the rotation speed of the output shaft of the transmission and therefore the vehicle speed. Will be.

On the other hand, for example, in a state in which the detection pulse train signal Pa cannot be obtained properly due to an accident such as a wire break at the detector 20A itself or its output side, the signals of the respective parts are the same as those described above in FIGS. From time t ₁ following the period T ₀ of
As shown in the period T ₁ until t ₂ . That is, the detection pulse train signals Pb and Pc from the detectors 20B and 20C are normally obtained as shown in the period T ₁ in FIGS. 7B and C, but the detection pulse train signal Pa from the detector 20A is obtained.
Becomes low level continuously as shown in the period T ₁ in FIG. 7A. As a result, in the detection output forming unit 30A of the output sending unit 30, the signals P ₁ and P ₃ obtained from the AND gate circuits 31 and 33 continuously take the low level, and only the signal P ₂ obtained from the AND gate circuit 32 is obtained. Becomes a pulse train signal synchronized with the detected pulse train signal Pc. As a result, the output signal from the OR gate circuit 34
Pn is as shown in period T ₁ in FIG. 7D,
It becomes the same as the output signal P ₂ of the AND gate circuit 32.

Then, at this time, the signal Pr from the OR gate circuit 41 in the abnormality detection unit 40 has a low level portion in synchronization with the falling portion of the detection pulse train signal Pc, as shown in the period T ₁ in FIG. 7E. In addition, the signal Pd from the AND gate circuit 42 remains in the period in FIG. 7F.
It will take a low level ₁ as shown at T ₁ . As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 is synchronized with the trailing edge of the detection pulse train signal Pc, which is the same as the signal Pr from the OR gate circuit 41, as shown in the period T ₁ in FIG. 7G. Then, it has a low level part.

The abnormality detection signal Pe, which takes a low level periodically, is supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and also to the lamp control unit that controls the blinking of the warning lamp. When the abnormality detection signal Pe takes a low level periodically, the lamp control unit turns on the warning lamp and detects the detection pulse train signals Pa and P.
It warns that either b or Pc has become abnormal.

As described above, in the state where the detection pulse train signal Pa becomes abnormal and continuously takes the low level, in the abnormality countermeasure signal forming unit 50, the RS flip-flops 51, 52 and 5 are provided.
The period in each of the set terminals S of 3 in FIGS. 7A, 7B and 7C.
The detection pulse train signal Pa having a low level and the normal detection pulse train signals Pb and Pc as shown at T ₁ are supplied to the RS flip-flops 61, 62 and 63, respectively.
To the respective set terminals S of the above-mentioned detection pulse train signals Pa, Pb
And Pc are level-inverted by inverters 67, 68 and 69 to provide signals Pa ', Pb' and Pc '.

At this time, the reset terminal R of each of the RS flip-flops 51, 52 and 53 is obtained by level-reversing the signal Pr from the abnormality detecting section 40 as shown in the period T ₁ in FIG. 7E. A signal Pr 'having a high level portion is supplied in synchronization with the trailing edge portion of the detection pulse train signal Pc. The signals S ₁ , S ₂ and S ₃ obtained from the output terminals Q of the RS flip-flops 51, 52 and 53, respectively, are obtained through the delay circuits 51a, 52a and 53a, respectively. Signal S ₁ ′, as shown in period T ₁ at
S ₂ ′ and S ₃ ′ are D-flip flops 54, 55 and 56.
Are supplied to the respective data terminals D. The clock terminal C of each of the D-flip-flops 54, 55 and 56 has a seventh
The signal Pr as shown in the period T ₁ in FIG. E is level-inverted and supplied to the D-flip-flops 54,5.
At the respective output terminals Q of 5 and 56, the signals S ₄ , S ₅ and S ₆ are obtained as shown in the period T ₁ in FIGS. It is supplied to one of the input terminals of 59 and 60.

At this time, the RS flip-flops 61, 62 and 6 whose signals Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
Each reset terminal R of 3 is supplied with a signal Pd obtained from the abnormality detecting section 40 which continuously has a low level ₁ as shown in a period T ₁ in FIG.
At the respective output terminals Q of the flip-flops 61, 62 and 63, the signals S ₇ , S ₈ and S ₉ which continuously take the high level h are obtained, and also the signals of the D-flip-flops 64, 65 and 66 are obtained. A signal Pd having a low level 1 is also supplied to each clock terminal C, and a signal S ₁₀ having a low level 1 is continuously supplied to the output terminals Q of the D-flip-flops 64, 65 and 66. S ₁₁
And S ₁₂ are obtained and these are supplied to the other input terminals of the OR gate circuits 58, 59 and 60, respectively.

Therefore, from the OR gate circuits 58, 59 and 60,
The signals S ₄ , S ₅ and S ₆ are obtained as they are in the period T ₁ in the diagrams K, L and M. Then, the AND gate circuit 71, the signal S ₄ of the as shown in the period T ₁ in FIG. 7 K, the signal S ₆ of as shown in the period T ₁ in Figure 7 M is level inverted by the inverter 79 a signal obtained Te, continuously and detection pulse train signal Pa taking low level is supplied, the signal C ₁ which is obtained from the aND gate circuit 71, a low level l as shown in the period T ₁ in Fig. 7 N Will be taken. Further, the AND gate circuit 72, a signal S ₅ of as shown in the period T ₁ in Fig. 7 L, signal S ₄ of the as shown in the period T ₁ in Fig. 7 K is level inverted by the inverter 77 The signal thus obtained and the normal detection pulse train signal Pd are supplied, and the normal detection pulse train signal Pb is obtained from the AND gate circuit 72 as the signal C ₂ as shown in the period T ₁ in FIG. To be In addition, the AND gate circuit 73
A signal S ₆ as shown in the period T ₁ in FIG. 7M, a signal S ₅ as shown in the period T ₁ in FIG. The normal detection pulse train signal Pc is supplied, and the signal C ₃ obtained from the AND gate circuit 73 has a low level ₁ as shown in the period T ₁ in FIG. 7P.

Therefore, at this time, the signal obtained from the AND gate circuit 72 is output from the OR gate circuit 76 as the abnormality countermeasure signal Cx.
C ₂ , that is, a normal detection pulse train signal Pb is obtained. The detection pulse train signal Pb as the abnormality countermeasure signal Cx is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and is supplied to the fixed contact 35b of the switch circuit 35 as the signal Cx ′ whose frequency is tripled. To be done.

Then, in this case, the control end of the switch circuit 35 of the output sending unit 30 is supplied with the abnormality detection signal Pe which is periodically low level obtained from the abnormality detection unit 40, and the switch circuit 35 periodically When the abnormality detection signal Pe having a low level is supplied, the movable contact 35c is connected to the fixed contact 35b. As a result, the switch circuit 35
A signal Cx ′ obtained by multiplying the frequency of the detection pulse train signal Pb from the frequency multiplication circuit 36 by 3 from the movable contact 35c of
Is transmitted as a detection output instead of the signal Pn from the detection output forming unit 30A.

The signal Cx ′ sent from the output sending unit 30 is the signal Pn
Instead, it is supplied to the drive unit 115 of the electronic meter control circuit unit 100 and each control unit. Thereby, when the detection pulse train signal Pa from the detector 20A arranged in the disc built-in unit 10 becomes abnormal and continuously takes a low level,
The signal Cx 'obtained by multiplying the frequency of the normal detection pulse train signal Pb by 3 is automatically taken as the emergency rotation detection output to each control unit.

In addition, the detection pulse train signal Pb or Pc due to an accident such as disconnection at the detector 20B or 20C itself or its output side.
Point in a state that no longer obtained properly, the various parts of the signal in FIG. 7 A-P, the period T ₂ of the from the time t ₂ subsequent to the period T ₁ of the above to t _3, or, following the period T ₂ It becomes as shown in t ₃ subsequent period T _3, the detector 20A and 2
The detection pulse train signals Pa and Pc from 0C are shown in FIGS.
Although properly obtained as shown in the period T ₂ in FIG. 7, the detection pulse train signal Pb from the detector 20B is
Continually be something that takes low-level as shown in the period T ₂ in, or detection pulse train signal Pa and Pb from the detectors 20A and 20B, as shown in the period T ₃ in FIG. 7 A and B Properly obtained, but detector
The detection pulse train signal Pc from 20C will be continuously at a low level as shown in the period T ₃ in FIG. 7C, and the above-mentioned detector 20A itself or its output side will be disconnected. The situation is similar to the state in which the detection pulse train signal Pa is not obtained properly.

That is, the signal P of the OR gate circuit 34 of the detection output forming unit 30A
n is the same as the signal P ₃ obtained from the AND gate circuit 33 as shown in the period T ₂ in FIG. 7D, or n is the same as the signal P ₃ in the period T ₃ in FIG. 7D. Will be the same as the signal P ₁ obtained from the OR gate circuit. At this time, the abnormality detection signal Pe obtained from the abnormality detection unit 40 will be the OR gate circuit as shown in the period T ₂ or T ₃ in FIG. 7G. It is the same as the signal Pr obtained from 41 and takes a low level periodically. The abnormality detection signal Pe that periodically takes a low level is also supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and is also supplied to the lamp control unit that controls the blinking of the warning lamp, The lamp control unit turns on the warning lamp.

Further, under the same operation as when the detection pulse train signal Pa continuously takes the low level, the OR gate circuits 58, 59 and 60 of the abnormality countermeasure signal forming unit 50 output the
The signals S ₄ , S ₅ and S ₆ as shown in the period T ₂ or T ₃ in the diagrams K, L and M are obtained as they are, and as a result, from the OR gate circuit 76, as the abnormality countermeasure signal Cx,
A signal C ₃ obtained from the AND gate circuit 73, that is, a normal detection pulse train signal Pc, or a signal C ₁ obtained from the AND gate circuit 71, that is, a normal detection pulse train signal Pa is obtained. The detection pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and the fixed contact 35b of the switch circuit 35 as the signal Cx ′ whose frequency is tripled. Is supplied to.

Then, also in such a case, the control terminal of the switch circuit 35 of the output transmission unit 30 is supplied with the abnormality detection signal Pe which is periodically low level and is obtained from the abnormality detection unit 40. The movable contact 35c is connected to the fixed contact 35b, and a signal Cx ′ obtained by multiplying the frequency of the detection pulse train signal Pc or Pa from the frequency multiplication circuit 36 by 3 from the movable contact 35c is output from the detection output forming unit 30A. It is sent as a detection output instead of the signal Pn, and is used as an emergency rotation detection output for the drive unit 115 of the electronic meter control circuit unit 100 and each control unit.

On the other hand, for example, when a short circuit accident occurs in the detector 20A and the detection pulse train signal Pa is not properly obtained, the signals of the respective parts are the above-mentioned period T ₄ in FIGS.
It followed, the as shown in the period T ₅ from time t ₄ to t _5. That is, the detection pulse train signals Pb and Pc from the detectors 20B and 20C are normally obtained as shown in the period T ₅ in FIGS. 8B and 8C, but the detection pulse train signal Pa from the detector 20A is As shown in the period T ₅ in FIG. A, the level continuously becomes high. Thereby, the detection output forming unit 30A of the output sending unit 30
Signal obtained from AND gate circuits 31 and 33 at
P ₁ and P ₃ takes a continuous high level, the AND gate circuit
Only the signal P ₂ obtained from 32 becomes a pulse train signal synchronized with the detection pulse train signal Pc. As a result, the OR gate circuit 34
The signal Pn from P has a low level portion in synchronization with the falling portion of the detection pulse train signal Pc, as shown in the period T ₅ in FIG. 8D.

Then, at this time, the signal Pr from the OR gate circuit 41 in the abnormality detecting section 40 becomes high level as shown in the period T ₅ in FIG. 8E, and the signal Pd from the AND gate circuit 42 is As shown in the period T ₅ in FIG. 8F, the high level portion is provided in synchronization with the rising portion of the detection pulse train signal Pc.
As a result, the abnormality detection signal Pe obtained from the AND gate circuit 44 corresponds to the detection pulse train signal Pc corresponding to the level-inverted signal Pd from the OR gate circuit 42, as shown in the period T ₅ in FIG. 8G. It has a low-level part in synchronization with the rising part in.

The abnormality detection signal Pe that periodically takes a low level is also supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and is also supplied to the lamp control unit that controls the blinking of the warning lamp, The lamp control unit turns on the warning lamp.

As described above, in the state in which the detection pulse train signal Pa continuously takes the high level, the abnormality countermeasure signal forming section 50 sets the high level to the set terminals S of the RS flip-flops 51, 52 and 53. The detection pulse train signal Pa and the normal detection pulse train signals Pb and Pc are supplied respectively, and the above-mentioned detection pulse train signals Pa, Pb and Pc are fed to the set terminals S of the RS flip-flops 61, 62 and 63 respectively by an inverter. Signal P obtained by level inversion by 67, 68 and 69
a ', Pb' and Pc 'are supplied.

At this time, at the reset terminals R of the RS flip-flops 51, 52 and 53, the signal Pr from the abnormality detecting section 40 as shown in the period T ₅ in FIG. A low level signal Pr 'is supplied to continuously output high level signals S ₁ , S ₂ and S _{3 at} the output terminals Q of the RS flip-flops 51, 52 and 53, respectively. , D-flip-flops 54, 55 and 56 are also supplied with a low level signal Pr 'to the respective output terminals Q of the D-flip-flops 54, 55 and 56, Signals S ₄ , S ₅ and S ₆ that continuously take a low level are obtained, and these are OR gate circuits 58, 59 and 6 respectively.
0 is supplied to one input terminal.

At this time, the RS flip-flops 61, 62 and 6 whose signals Pa ', Pb' and Pc 'are supplied to the set terminal S respectively.
Each reset terminal R of 3 has a signal Pd which has a high level portion in synchronization with the rising portion of the detection pulse train signal Pc, which is obtained from the abnormality detecting portion 40, as shown in the period T ₅ in FIG. 8F. Is supplied. The signals S ₇ , S ₈ and S ₉ obtained at the output terminals Q of the RS flip-flops 61, 62 and 63, respectively, are obtained through the delay circuits 61a, 62a and 63a, respectively. Signals S ₇ ′, S ₈ ′ and S ₉ ′ as shown in period T ₅ at are supplied to the respective data terminals D of D-flip-flops 64, 65 and 66. A signal Pd having a high level portion is supplied to the clock terminals C of the D-flip-flops 64, 65 and 66 in synchronization with the rising portion of the detection pulse train signal Pc, and the D-flip-flops 64, 65 are supplied. And 66, at the respective output terminals Q, signals S ₁₀ , S ₁₁ and S ₁₂ are obtained as shown in the period T ₅ in FIGS. 8K, L and M, which are respectively OR gate circuits 58, 59 and It is supplied to the other input terminal of 60.

Therefore, from the OR gate circuits 58, 59 and 60,
The signals S ₁₀ , S ₁₁ and S _{12 as they} are shown in the period T ₅ in the diagrams K, L and M are obtained as they are. Then, the AND gate circuit 71, the signal S ₁₀ of the as shown in the period T ₅ in FIG. 8 K, the signal S ₁₂ of the as shown in the period T ₅ in FIG. 8 M is level inverted by the inverter 79 The signal C ₁ obtained from the AND gate circuit 71 is supplied with the detection pulse train signal Pa that continuously has a high level, and the signal C ₁ obtained from the AND gate circuit 71 has a low level 1 as shown in the period T ₅ in FIG. 8N. Will be taken. Further, the AND gate circuit 72, the signal S ₁₁ of the as shown in the period T ₅ in FIG. 8 L, signal S ₁₀ of the as shown in the period T ₅ in FIG. 8 K is level inverted by the inverter 77 Signal and the normal detection pulse train signal Pb
And the normal detection pulse train signal Pb is obtained from the AND gate circuit 72 as the signal C ₂ as shown in the period T ₅ in FIG. Further, the AND gate circuit 73, the signal S ₁₂ of the as shown in the period T ₅ in FIG. 8 M, the signal S ₁₁ of the as shown in the period T ₅ in FIG. 8 L is level inverted by the inverter 78 The signal obtained as a result and the normal detection pulse train signal Pc are supplied, and the signal C ₃ obtained from the AND gate circuit 73 is
As shown in the period T ₅ in FIG. 8P, the low level 1 is obtained.

Therefore, at this time, the signal obtained from the AND gate circuit 72 is output from the OR gate circuit 76 as the abnormality countermeasure signal Cx.
C ₂ , that is, a normal detection pulse train signal Pb is obtained and supplied to the frequency multiplication circuit 36 in the output selection unit 30B of the output transmission unit 30, and the fixed contact of the switch circuit 35 is provided as the signal Cx ′ whose frequency is tripled. Supplied to 35b.

Then, in this case, the control terminal of the switch circuit 35 of the output sending unit 30 is supplied with the abnormality detection signal Pe which is periodically low level and which is obtained from the abnormality detection unit 40. 35c is connected to the fixed contact 35b. As a result, a signal Cx ′ obtained by multiplying the frequency of the detection pulse train signal Pb from the frequency multiplication circuit 36 by 3 from the movable contact 35c of the switch circuit 35 is used as a detection output instead of the signal Pn of the detection output forming unit 30A. Sent out.

Therefore, even when the detection pulse train signal Pa from the detector 20A arranged in the disk built-in unit 10 becomes abnormal and continuously takes a high level, the frequency of the normal detection pulse train signal Pb is 3 The signal Cx 'obtained by the multiplication is automatically taken as the emergency rotation detection output to each control unit.

In the state where the detector 20B or 20C is short-circuited and the detection pulse train signal Pb or Pc cannot be obtained properly, the signals of the respective parts are at the time points following the period T ₅ in FIGS. 8A to 8P. As shown in the period T ₆ from t ₅ to t ₆ , or the period T ₇ after the time t ₆ following the period T ₆ , the detection pulse train signals from the detectors 20A and 20C are displayed.
Pa and Pc are properly obtained as shown in the period T ₆ in FIGS. 8A and 8C, but the detection pulse train signal Pb from the detector 20B is continuously obtained as shown in the period T ₆ in FIG. 8B. To a high level, or the detection pulse train signals Pa and Pb from the detectors 20A and 20B.
Is properly obtained as shown in the period T ₇ in FIGS. 8A and 8B, the detection pulse train signal Pc from the detector 20C is continuously high level as shown in the period T ₇ in FIG. 8C. This is the same as the state where the detection pulse train signal Pa cannot be obtained properly due to the short-circuit accident in the detector 20A described above.

That is, the signal P of the OR gate circuit 34 of the detection output forming unit 30A
n has a low level portion in synchronization with the falling portion of the detection pulse train signal Pa, as shown in the period T ₆ in FIG. 8D, or as shown in the period T ₇ in FIG. 8D, The detection pulse train signal Pb has a low level portion in synchronization with the falling portion, and at this time, the abnormality detection signal Pe obtained from the abnormality detection unit 40 is
As shown in period T ₆ or T ₇ in FIG. G,
The signal Pd obtained from the OR gate circuit 42 has a periodically low level, which corresponds to the level-inverted signal Pd. The abnormality detection signal Pe that periodically takes a low level is also supplied to the control end of the switch circuit 35 in the output selection unit 30B of the output transmission unit 30 and is also supplied to the lamp control unit that controls the blinking of the warning lamp, The lamp control unit turns on the warning lamp.

Furthermore, under the same operation as when the detection pulse train signal Pa continuously takes the high level, the OR gate circuits 58, 59 and 60 of the abnormality countermeasure signal forming section 50 output
The signals S ₁₀ , S ₁₁ and S ₁₂ as shown in the periods T ₆ or T ₇ in the diagrams K, L and M are obtained as they are, whereby the AND gate circuit 76 outputs the abnormality countermeasure signal Cx from the AND gate circuit 76. The signal C ₃ obtained from 73, that is, the normal detection pulse train signal Pc, or the AND gate circuit
Signal C ₁ obtained from 71, that is, a normal detection pulse train signal
Pa is obtained. The detection pulse train signal Pc or Pa as the abnormality countermeasure signal Cx is output by the output selection unit 30B of the output transmission unit 30.
Is supplied to the fixed contact 35b of the switch circuit 35 as a signal Cx 'whose frequency has been tripled.

Also in this case, the switch circuit of the output sending unit 30
Since the abnormality detection signal Pe obtained from the abnormality detection unit 40 and having a periodically low level is supplied to the control end of 35, the movable contact 35c of the switch circuit 35 is connected to the fixed contact 35b, and the movable contact 35c , A signal obtained by multiplying the frequency of the detection pulse train signal Pc or Pa from the frequency multiplication circuit 36 by 3
Cx ′ is sent as a detection output in place of the signal Pn from the detection output forming unit 30A, and is used as an emergency rotation detection output for each control unit.

As described above, the output sending section 30, the abnormality detecting section 40, and the abnormality countermeasure signal forming section 50 provided in the logic circuit block 28.
As a result, a rotation detection output capable of improving detection accuracy is obtained, and if any of the detection pulse train signals Pa, Pb, and Pc becomes abnormal, no abnormality occurs. Appropriate measures are taken automatically by effectively using other detection pulse train signals. In addition to this, in addition to this, the forward / backward movement discriminating unit 80 provided in the logic circuit block 28 is used.
Thus, a signal for determining whether the vehicle is moving forward, backward, or stopped is obtained.

That is, the forward / backward movement determining unit 80, as shown in FIG.
D-flip-flops 81, 82, 83, 84, 85 and 86 and 6
It has AND gate circuits 91, 92, 93, 94, 95 and 96 and two OR gate circuits 97 and 98. Then, the detection pulse train signal Pa is level-inverted directly to the data terminal D of the D-flip-flops 81 and 82 and the clock terminal C of the D-flip-flop 85, and to the clock terminal C of the D-flip-flop 86. The detection pulse train signal Pb is supplied to the data terminals D of the D-flip-flops 83 and 84 and the clock terminal C of the D-flip-flop 81, and the clock terminal C of the D-flip-flop 82.
Is supplied to the data terminal D of the D-flip-flops 85 and 86 and the clock terminal C of the D-flip-flop 83, and also to the D-flip-flop 83. Clock terminal C of 84
Is supplied after being inverted in level.

The signals Fa, Fb and Fc obtained at the output terminals Q of the D-flip-flops 81, 83 and 85 are the AND gate circuits 91,
The signals Ra, Rb and Rc obtained at the respective input terminals of the respective 93 and 95 and at the respective output terminals Q of the D-flip-flops 82, 84 and 86 are applied to the AND gate circuits 92, 94 and 96, respectively. The signals Fa ', Fb' and Fc ', which are supplied to one of the input terminals of the D-flip-flops 81, 83 and 85, are supplied to the AND gate circuits 92, 94.
And 96, respectively, and the signals Ra ', Rb' and Rc 'available at the respective inverting output terminals of the D-flip-flops 82, 84 and 86 are applied to the AND gate circuits 91, 93 and 95. Of the output signals F ₁ , F ₂ and F ₃ supplied to the other input terminals of the AND gate circuits 91, 93 and 95, respectively.
To the OR gate circuit 97, and AND gate circuits 92 and 94
Output signals R ₁ , R ₂ and R _{3 respectively} obtained from the output signals 96 and 96 are supplied to an OR gate circuit 98.

When the vehicle is moving forward, the forward / backward traveling determination unit 80 having such a configuration is shown in the period T ₀ in FIGS. 7A, 7B and 7C described above and the period T ₄ in FIGS. 8A, 8B and 8C. As described above, the detection pulse train signals Pa, Pb, and Pc sequentially having a phase difference of 2π / 3 are supplied.

At this time, signals Fa, Fb and Fc obtained from the output terminals Q of the D-flip-flops 81, 83 and 85, respectively, and
The signals Ra ', Rb' and Rc 'obtained from the inverting output terminals of the D-flip-flops 82, 84 and 86 respectively take the high level, and the AND gate circuits 91, 93 and 95 respectively output the high level signals. The signals F ₁ , F ₂ and F ₃ are obtained. On the other hand, Fa ', Fb' and Fc 'obtained from the inverting output terminals of D-flip-flops 81, 83 and 85, respectively, and D
The output terminal Q of each of the flip-flops 82, 84 and 86
Ra, Rb and Rc obtained from the low level take low levels, and the low levels R ₁ , R ₂ and R ₃ are obtained from the AND gate circuits 92, 94 and 96, respectively. As a result, the OR gate circuit 97 obtains the signal Ma that continuously has the high level, and the OR gate circuit 98 obtains the signal Mb that continuously has the low level.

On the other hand, when the vehicle retreats, the rotating disc 14
Rotates in the direction opposite to that when moving forward, and the detected pulse train signals Pa and Pb
And Pc have a mutual phase advance / retard relationship opposite to that in the forward phase. Therefore, the forward / rearward traveling determination unit 80 is sequentially supplied with the detection pulse train signals Pa, Pb, and Pc having a phase delay of 2π / 3 each in the order of Pc → Pb → Pa.

Therefore, the signals Fa, Fb and Fc obtained from the output terminals Q of the D-flip-flops 81, 83 and 85, respectively, and
The signals Ra ', Rb' and Rc 'obtained from the respective inverting output terminals of the D-flip-flops 82, 84 and 86 take the low level, and the AND gate circuits 91, 93 and 95 respectively give the low level. Signals F ₁ , F ₂ and F ₃ are obtained, and signals Fa ′, Fb ′ and Fc ′ and D− obtained from the inverting output terminals of the D-flip-flops 81, 83 and 85, respectively. The signals Ra, Rb, and Rc obtained from the output terminals Q of the flip-flops 82, 84, and 86 become high levels, and the signals R ₁ that take high levels from the AND gate circuits 92, 94, and 96, respectively. , R ₂ and R ₃ are obtained. As a result, a signal that continuously goes low from the OR gate circuit 97
While Ma is obtained, the signal Mb that continuously has a high level is obtained from the OR gate circuit 98.

Furthermore, when the vehicle is stopped, the detected pulse train signal
Since all of Pa, Pb and Pc are continuously low level, or one or two of them are continuously high level and the other is continuously low level, Signals obtained from OR gate circuits 97 and 98, respectively
Both Ma and Mb are continuously low.

In this way, the signal relationship between the high level and the low level is reversed when the vehicle is moving forward and backward, and the signal Ma and the low level are both low when the vehicle is stopped.
Mb is the electronic meter control circuit unit 10 as the forward / backward movement determination signal.
Each control unit, for example, an electric brake (parking brake) control unit is supplied from an output terminal of 0. As a result, in the electric brake control unit, operation control corresponding to the forward, backward, and stopped states of the vehicle is performed according to the levels of the supplied signals Ma and Mb.

As described above, in the forward / rearward traveling determination unit 80 that is configured to output the signals Ma and Mb as the forward / rearward traveling determination signals of the vehicle, any of the detection pulse train signals Pa, Pb, and Pc are appropriate as described above. Not only in the obtained normal state, but also in an abnormal state in which any of the detection pulse train signals Pa, Pb, and Pc cannot be properly obtained, the forward, backward, and stopped states of the vehicle are determined.

For example, when the detection pulse train signal Pa continuously becomes high level or low level when the vehicle moves forward or backward, the signal F ₁ obtained from the AND gate circuits 91 and 92
And R ₁ both take a low level, but the signals F ₂ , R ₂ , F ₃ and R _{3 respectively} obtained from the other AND gate circuits 93 to 96 take the same level as in the normal state. Therefore,
Signals Ma and Mb obtained from OR gate circuits 97 and 98, respectively
Will take the same level as in normal times.

In addition, when the vehicle moves forward or backward, the detected pulse train signal
Even when Pb or Pc is continuously high level or low level, the OR gate circuits 97 and 98 are operated in the same manner as when the detection pulse train signal Pa is continuously high level or low level. The signals Ma and Mb obtained from the respective signals have the same level as in the normal state.

Therefore, from the forward / rearward traveling determination unit 80,
Even if an abnormality occurs in a, Pb, or Pc, the signal Ma that takes a high level when the vehicle moves forward and has a low level when the vehicle moves backward and stops, as well as during normal operation, and when the vehicle moves forward and stops A signal that takes a low level and a high level when retreating
Mb is obtained, and the forward / backward / stopped state of the vehicle is determined by this.

In the above example, the through holes 16 as the detection target are arrayed in the rotating disk 14, and the photoelectric detector 20A is provided in the detection unit to obtain the detection pulse train signal according to the alignment of the detection target.
Although 20B and 20C are used, the detection unit used in the information signal forming and supplying device according to the present invention is such a rotating disk 14
Not limited to those having a combination of a detected portion provided as a through hole and a photoelectric type detector, a light reflecting portion is formed in the rotating disk 14 instead of the through hole, and the light reflecting portion is formed. It may have a combination with a photoelectric detector that irradiates this with light and receives the reflected light.Furthermore, the rotating disk 14 is provided with various other components such as a magnetizing unit. The detected parts may be arranged in an array, and the detection part may include various detectors other than the photoelectric detector, such as an electromagnetic detector.

(Effects of the Invention) As is apparent from the above description, according to the information signal forming / supplying device of the present invention, the detection output of the rotation state of the rotating body, which is obtained from the detection unit and is in the rotation state according to the vehicle speed, is obtained. A signal processing unit that forms an information signal corresponding to a vehicle speed required in a plurality of control units installed in the vehicle based on the signal, and an information signal corresponding to the vehicle speed in the control unit The internal circuit of the electronic meter control circuit unit in the electronic meter device installed to display the state of the vehicle is used as the signal supply unit to be provided to the configuration, without being installed as a separate additional circuit unit. Therefore, the signal processing unit and the signal supply unit can be efficiently used by avoiding the redundant installation of the signal processing unit and the signal processing unit. It is possible to simplify the wiring of each section related to the section and the signal supply section.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an example of an information signal forming / supplying device according to the present invention together with an electronic meter device to which it is applied,
FIG. 2 is a perspective view showing a specific configuration example of the disk built-in portion used in the example shown in FIG. 1, and FIG. 3 is used for explaining the photoelectric detector used in the example shown in FIG. Side view,
4 is a block diagram showing an example of a logic circuit block used in the example shown in FIG. 1, and FIG. 5 is a block diagram showing a specific configuration example of an output sending unit in the logic circuit block shown in FIG. 4, FIG. 6 is a block diagram showing a specific configuration example of an abnormality detection unit and an abnormality countermeasure signal formation unit in the logic circuit block shown in FIG. 4, FIGS. 7A to P and FIG. 8A.
P are waveform charts provided for explaining the operation of the logic circuit block shown in FIG. 4, and FIG. 9 is a block diagram showing a specific configuration example of the forward / backward movement determination unit in the logic circuit block shown in FIG. . In the figure, 10 is a disc built-in portion, 14 is a rotating disc, 16 is a through hole, 20A,
20B and 20C are detectors, 28 is a logic circuit block, 30 is an output sending unit, 40 is an abnormality detection unit, 50 is an abnormality countermeasure signal forming unit, and 80
Is a forward / backward movement discriminating unit, 100 is an electronic meter control circuit unit, 104 is a CP
U.

Claims (1)

[Claims] 1. An electronic meter control circuit section in an electronic meter device installed to display the state of a vehicle, and detects the rotational state of a rotating body placed in a rotational state according to the vehicle speed in the vehicle. And a detection unit for generating a detection output signal, the electronic meter control circuit unit in the electronic meter device,
A signal processing unit that performs predetermined signal processing on the detection output signal obtained from the detection unit to form an information signal corresponding to the vehicle speed of the vehicle, and the information signal obtained from the signal processing unit is installed in the vehicle. An information signal forming / supplying device comprising a signal supply section for supplying the control unit.