JP2517726B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JP2517726B2 JP2517726B2 JP18302787A JP18302787A JP2517726B2 JP 2517726 B2 JP2517726 B2 JP 2517726B2 JP 18302787 A JP18302787 A JP 18302787A JP 18302787 A JP18302787 A JP 18302787A JP 2517726 B2 JP2517726 B2 JP 2517726B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring board
- paste
- resistor
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線基板の製造方法に関する。The present invention relates to a method for manufacturing a multilayer wiring board.
本発明は多層配線基板の製造方法において、複数枚の
絶縁基板上に融点の異なる抵抗体層、導体層及び絶縁体
層を各ペーストの印刷、焼成により形成し、得られた複
数枚の配線基板を積層し、熱圧着することにより、 高精度に調整されかつ変動の極めて小さい抵抗値を有
する抵抗体層を備えた多層配線基板を得ることができる
ようにしたものである。The present invention relates to a method for manufacturing a multilayer wiring board, wherein a plurality of insulating boards obtained by forming a resistor layer, a conductor layer and an insulator layer having different melting points on each of a plurality of insulating boards by printing and firing each paste. It is possible to obtain a multilayer wiring board including a resistor layer having a resistance value that is adjusted with high precision and has an extremely small variation by stacking and thermocompressing.
従来、多層配線基板の製造方法としてグリーンシート
法及び厚膜印刷法が行われてきた。Conventionally, a green sheet method and a thick film printing method have been performed as a method for manufacturing a multilayer wiring board.
しかし、グリーンシート法ではグリーンシートを積層
して仮焼成又は乾燥した後、本焼成を行うため、内部の
印刷抵抗体層の抵抗値を修正することができずかつ抵抗
値が変動するという問題点がある。一方、厚膜印刷法で
は、必要層数の各層毎に印刷、焼成がくり返されるため
にやはり抵抗体層の抵抗値が大きく変動する。このよう
な従来の方法では抵抗値の精度は±20％程度であり、目
標とする抵抗値を変動を少なく（数％以下）高精度で得
ることは極めて困難であった。However, in the green sheet method, since the green sheets are stacked, pre-baked or dried, and then the main baking is performed, the resistance value of the internal printed resistor layer cannot be corrected and the resistance value fluctuates. There is. On the other hand, in the thick film printing method, since the printing and firing are repeated for each required number of layers, the resistance value of the resistor layer also largely changes. With such a conventional method, the accuracy of the resistance value is about ± 20%, and it is extremely difficult to obtain the target resistance value with a small variation (several% or less) and with high accuracy.
したがって、本発明の目的は、多層配線基板層内に目
標とする抵抗値を有する抵抗体層を高い精度で密閉形成
させる多層配線基板の製造方法を提供することである。Therefore, an object of the present invention is to provide a method for manufacturing a multilayer wiring board in which a resistor layer having a target resistance value is hermetically formed in a multilayer wiring board layer with high accuracy.
前記の目標は、本発明により、複数枚の絶縁基板を準
備し、各絶縁基板の上面に抵抗ペースト、導体ペースト
及び絶縁ペーストを所定パターンに印刷、焼成してそれ
ぞれ抵抗体層、導体層及び絶縁体層を形成し、前記各絶
縁基板の下面に導体ペースト及び絶縁ペーストを所定パ
ターンに印刷、焼成してそれぞれ導体層及び絶縁体層を
形成し、得られた複数枚の配線基板を一方の絶縁基板の
上面側と他方の絶縁基板の下面側とが接するように積層
し、熱圧着させることからなり、抵抗体層、導体層及び
絶縁体層の順にこれらの層の融点が低くなるように各前
記ペーストが選択され、熱圧着時の加熱温度が、抵抗体
層及び導体層の融点より低くかつ絶縁体層の融点と同じ
かそれより高いことを特徴とする多層配線基板の製造方
法により達成される。According to the present invention, a plurality of insulating substrates are prepared, and a resistor paste, a conductor paste and an insulating paste are printed on a predetermined pattern on the upper surface of each insulating substrate and fired to form a resistor layer, a conductor layer and an insulating layer, respectively. A body layer is formed, and a conductor paste and an insulation paste are printed on a lower surface of each insulating substrate in a predetermined pattern and fired to form a conductor layer and an insulator layer, respectively. The upper surface of the substrate and the lower surface of the other insulating substrate are laminated so that they are in contact with each other, and thermocompression bonding is performed. Each of the resistor layer, the conductor layer, and the insulating layer is arranged in this order so that the melting points of these layers become lower. The paste is selected, and the heating temperature at the time of thermocompression bonding is lower than the melting points of the resistor layer and the conductor layer and is the same as or higher than the melting point of the insulating layer, which is achieved by a method for manufacturing a multilayer wiring board. Ru
本発明の好ましい態様によれば、絶縁体層の融点が抵
抗体層の融点より少なくとも100℃低い。これにより、
抵抗体層の抵抗値の変動を一層確実に小さくすることが
できる。According to a preferred aspect of the present invention, the melting point of the insulator layer is at least 100 ° C. lower than the melting point of the resistor layer. This allows
It is possible to more reliably reduce the variation in the resistance value of the resistor layer.
本発明の別の好ましい態様によれば、複数枚の配線基
板を積層したとき各配線基板の互いに接する側におい
て、一方の配線基板の抵抗体層にオーバーコート層を設
け、このオーバーコート層に対応する他方の配線基板の
部分には絶縁体層を形成しない。According to another preferred aspect of the present invention, when a plurality of wiring boards are stacked, an overcoat layer is provided on the resistor layer of one wiring board on the side where the wiring boards are in contact with each other. The insulating layer is not formed on the other wiring board portion.
配線基板を積層する前に、各配線基板に形成された抵
抗体層の抵抗値を必要に応じて調整することができ、こ
の調整は従来のトリミング法によって行われる。この調
整によって抵抗値を目標値に関して一層高い精度で得る
ことができる。Before laminating the wiring boards, the resistance value of the resistor layer formed on each wiring board can be adjusted as necessary, and this adjustment is performed by the conventional trimming method. By this adjustment, the resistance value can be obtained with higher accuracy with respect to the target value.
なお、積層される配線基板の最上部の、特に抵抗体層
上に、ガラスコーティング、樹脂コーティングなどによ
る保護層を設けることが望ましい。It is desirable to provide a protective layer such as glass coating or resin coating on the uppermost part of the wiring boards to be laminated, especially on the resistor layer.
以下本発明の実施例を説明する。 Examples of the present invention will be described below.
実施例１ 第１図において、マイカからなる複数枚の絶縁基板１
の上面に導体ペースト（Agペースト、例えば北陸塗料社
製のSR1915、焼成温度550℃±10℃）、抵抗体ペースト
（RuO2系ペースト、例えばESL社の＃3111、焼成温度600
℃＃10℃）及びSiO2‐B2O3‐PbOガラス絶縁ペースト、
例えばDupont社製8185、焼成温度495℃±10℃）をこの
順に用いて所定パターンに印刷、焼成し（第１段階）そ
れぞれ導体層３、抵抗体層２及び絶縁体層４を形成し
た。なお、第２図に示す通り、第２層目以降の絶縁基板
１の上面側に抵抗体層９を形成し、次いで導体層10を形
成してもよい。Example 1 In FIG. 1, a plurality of insulating substrates 1 made of mica
Conductor paste (Ag paste, for example, SR1915 manufactured by Hokuriku Paint Co., Ltd., firing temperature 550 ° C ± 10 ° C), resistor paste (RuO 2 type paste, for example, ESL # 3111, firing temperature 600
℃ # 10 ℃) and SiO 2 -B 2 O 3 -PbO glass insulation paste,
For example, 8185 manufactured by Dupont, firing temperature 495 ° C. ± 10 ° C.) was used in this order to print in a predetermined pattern and fired (first step) to form the conductor layer 3, the resistor layer 2, and the insulator layer 4, respectively. Note that, as shown in FIG. 2, the resistor layer 9 may be formed on the upper surface side of the second and subsequent insulating substrates 1, and then the conductor layer 10 may be formed.
次いで、各絶縁板１の下面に前記と同じ導体ペースト
及びガラス絶縁ペーストを用いて所定パターンに印刷、
焼成して（第２段階）それぞれ導体層５及び絶縁体層６
を形成した。導体層３と５の導通のため絶縁基板１に設
けたスルーホール７を介して導体層８を形成した。Next, the same conductive paste and glass insulating paste as described above are used to print a predetermined pattern on the lower surface of each insulating plate 1,
After firing (second step), the conductor layer 5 and the insulator layer 6 are respectively formed.
Was formed. A conductor layer 8 was formed through a through hole 7 provided in the insulating substrate 1 for conducting the conductor layers 3 and 5.
なお、前記第１段階後に抵抗体層２をレーザトリミン
グ装置でトリミングを行って目標抵抗値を有するように
した。このトリミングは前記第２段階後に行ってもよ
い。After the first step, the resistor layer 2 was trimmed by a laser trimming device so as to have a target resistance value. This trimming may be performed after the second step.
こうして得られた各配線基板を第１図に示す方向で積
層し、540℃、4.5kg/cm2で２〜３分間熱圧着を行った。
その際、主として絶縁体層４、６が軟化し、互いに接着
した。各導体層３と５は互いに対向密着して導通を得
る。得られた多層配線基板の抵抗体層の抵抗値は目標値
に対する変動が±５％以内であった。また、第２図に示
した抵抗体層９と導体層10の場合、熱圧着時に導体層10
がスペーサーの役目をするので、抵抗体層９に不必要な
力が加わらず、その抵抗値を一層高い精度で得ることが
できる。The wiring boards thus obtained were stacked in the direction shown in FIG. 1 and thermocompression bonded at 540 ° C. and 4.5 kg / cm 2 for 2 to 3 minutes.
At that time, mainly the insulating layers 4 and 6 were softened and adhered to each other. The conductor layers 3 and 5 are in close contact with each other to obtain conduction. The variation of the resistance value of the resistor layer of the obtained multilayer wiring board with respect to the target value was within ± 5%. Moreover, in the case of the resistor layer 9 and the conductor layer 10 shown in FIG.
Serves as a spacer, so that unnecessary force is not applied to the resistor layer 9 and the resistance value can be obtained with higher accuracy.
実施例２ 第３図において、絶縁基板15の上面側に実施例１と同
様にして抵抗体層２、導体層３及び絶縁体層４を形成し
た。抵抗体層２をトリミングして所定抵抗値となるよう
にした。第２層目以降の各絶縁基板15の上面側に形成し
た抵抗体層２上に、SiO2‐B2O3‐PbO系ガラスペースト
（例えば日本電気硝子社製PLS3120、焼成温度535℃±10
℃）を用いてオーバーコートガラス11を形成した。Example 2 In FIG. 3, the resistor layer 2, the conductor layer 3 and the insulator layer 4 were formed on the upper surface side of the insulating substrate 15 in the same manner as in Example 1. The resistor layer 2 was trimmed to have a predetermined resistance value. SiO 2 -B 2 O 3 -PbO glass paste (eg, PLS3120 manufactured by Nippon Electric Glass Co., Ltd., firing temperature 535 ° C. ± 10
C) was used to form overcoat glass 11.
絶縁基板15の下面側に実施例１と同様のペーストを用
いて導体層３、13と絶縁体層４を形成した。ただし、積
層時にオーバーコートガラス11に対応する絶縁基板15の
下面側の部分12には第１図とは異なって絶縁体層を設け
なかった。また、抵抗電極となる導体層13はその幅W2が
対向する絶縁基板15の下面側の導体層３の幅W1より大き
くなるように形成した。The conductor layers 3 and 13 and the insulator layer 4 were formed on the lower surface side of the insulating substrate 15 using the same paste as in Example 1. However, unlike the case of FIG. 1, no insulating layer was provided on the lower surface side portion 12 of the insulating substrate 15 corresponding to the overcoat glass 11 at the time of stacking. In addition, the conductor layer 13 serving as the resistance electrode is formed so that its width W 2 is larger than the width W 1 of the conductor layer 3 on the lower surface side of the insulating substrate 15 which is opposed thereto.
こうして得られた各配線基板を実施例１と同様にして
熱圧着して多層配線基板とした。Each wiring board thus obtained was thermocompression bonded in the same manner as in Example 1 to obtain a multilayer wiring board.
なお、オーバーコートガラス11の形成は絶縁体層４の
形成前に行ってもよい。The overcoat glass 11 may be formed before the insulator layer 4 is formed.
この実施例によれば、熱圧着の際に導体層３、13がス
ペーサーとしての役目をはたし、また、部分12の空隙の
存在によって、熱圧着時に第２層目以降の抵抗体層２に
圧力が加わるのが避けられる。さらに、導体層３の幅W1
が導体層（抵抗電極）13の幅W2より小さいので、抵抗体
層２の熱拡散を良くすることにより、抵抗体層２の抵抗
値の変動を防ぐことができる。According to this embodiment, the conductor layers 3 and 13 function as spacers during thermocompression bonding, and due to the presence of the voids in the portion 12, the second and subsequent resistor layers 2 during thermocompression bonding. It is possible to avoid applying pressure to. Furthermore, the width W 1 of the conductor layer 3
Is smaller than the width W 2 of the conductor layer (resistive electrode) 13, it is possible to prevent the resistance value of the resistor layer 2 from fluctuating by improving the thermal diffusion of the resistor layer 2.
この実施例で得られた多層配線基板の抵抗体層の抵抗
値は目標値に対する変動が±２％以下であった。The variation of the resistance value of the resistor layer of the multilayer wiring board obtained in this example with respect to the target value was ± 2% or less.
以上述べた通り、本発明の方法によれば、抵抗体層に
対する熱及び圧力の悪影響を回避することができるの
で、高い精度でかつ変動が少なく所定の抵抗値を有する
抵抗体層が形成される。また、積層前の各印刷基板上の
抵抗体層はトリミングによりその抵抗値を高精度に調整
できるので、多層配線基板の抵抗体層の抵抗値を一層高
精度に制御することができる。As described above, according to the method of the present invention, it is possible to avoid the adverse effects of heat and pressure on the resistor layer, so that a resistor layer having a predetermined resistance value with high accuracy and little fluctuation is formed. . Further, since the resistance value of the resistor layer on each printed board before lamination can be adjusted with high precision by trimming, the resistance value of the resistor layer of the multilayer wiring board can be controlled with higher precision.
第１図は本発明の一実施例により得られる多層配線基板
の断面図、第２図は第１図の変更部分の拡大断面図、第
３図は本発明の別の実施例により得られる多層配線基板
の断面図である。 なお図面に用いた符号において、 １……絶縁基板 ２……抵抗体層 3,5,8……導体層 4,6……絶縁体層 である。FIG. 1 is a sectional view of a multilayer wiring board obtained by an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a modified portion of FIG. 1, and FIG. 3 is a multilayer obtained by another embodiment of the present invention. It is sectional drawing of a wiring board. In the reference numerals used in the drawings, 1 ... Insulating substrate 2 ... Resistor layer 3, 5, 8 ... Conductor layer 4, 6 ... Insulator layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 伝田 実 東京都大田区中馬込１丁目18番18号 双 信電機株式会社内 (72)発明者 小平 一男 東京都大田区中馬込１丁目18番18号 双 信電機株式会社内 (72)発明者 常間地 功 東京都大田区中馬込１丁目18番18号 双 信電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minor Denden, 18-18 Nakamagome, 18-18 Nakamagome, Ota-ku, Tokyo Soshin Electric Co., Ltd. (72) Kazuo Kodaira 1-1-18, Nakamagome, Ota-ku, Tokyo No. Soshin Electric Co., Ltd. (72) Inventor Isao Tonema 18-18 Nakamagome, Ota-ku, Tokyo Soshin Electric Co., Ltd.
Claims (3)
上面に抵抗ペースト、導体ペースト及び絶縁ペーストを
所定パターンに印刷、焼成してそれぞれ抵抗体層、導体
層及び絶縁体層を形成し、前記各絶縁基板の下面に導体
ペースト及び絶縁ペーストを所定パターンに印刷、焼成
してそれぞれ導体層及び絶縁体層を形成し、得られた複
数枚の配線基板を一方の絶縁基板の上面側と他方の絶縁
基板の下面側とが接するように積層し、熱圧着させるこ
とからなり、抵抗体層、導体層及び絶縁体層の順にこれ
らの層の融点が低くなるように各前記ペーストが選択さ
れ、熱圧着時の加熱温度が、抵抗体層及び導体層の融点
より低くかつ絶縁体層の融点と同じかそれより高いこと
を特徴とする多層配線基板の製造方法。1. A plurality of insulating substrates are prepared, and a resistor layer, a conductor layer and an insulator layer are respectively formed by printing a resistor paste, a conductor paste and an insulator paste in a predetermined pattern on the upper surface of each insulator substrate and firing them. Then, a conductor paste and an insulating paste are printed on a lower surface of each insulating substrate in a predetermined pattern and fired to form a conductor layer and an insulator layer, respectively, and the obtained wiring boards are formed on the upper surface side of one insulating substrate. And the lower surface of the other insulating substrate are laminated so that they are in contact with each other, and thermocompression bonding is performed. Each paste is selected so that the melting point of these layers becomes lower in the order of the resistor layer, the conductor layer and the insulator layer. The method for producing a multilayer wiring board is characterized in that the heating temperature during thermocompression bonding is lower than the melting points of the resistor layer and the conductor layer and higher than or equal to the melting point of the insulating layer.
くとも100℃低い特許請求の範囲第１項記載の多層配線
基板の製造方法。2. The method for manufacturing a multilayer wiring board according to claim 1, wherein the melting point of the insulator layer is at least 100 ° C. lower than the melting point of the resistor layer.
板の互いに接する側において、一方の配線基板の抵抗体
層にオーバーコート層を設け、このオーバーコート層に
対応する他方の配線基板の部分には絶縁体層を形成しな
い特許請求の範囲第１項記載の多層配線基板の製造方
法。3. When a plurality of wiring boards are laminated, an overcoat layer is provided on the resistor layer of one wiring board on the side where the wiring boards contact each other, and the other wiring board corresponding to this overcoat layer is formed. The method for manufacturing a multilayer wiring board according to claim 1, wherein an insulating layer is not formed on the portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18302787A JP2517726B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18302787A JP2517726B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6425597A JPS6425597A (en) | 1989-01-27 |
| JP2517726B2 true JP2517726B2 (en) | 1996-07-24 |
Family
ID=16128460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18302787A Expired - Fee Related JP2517726B2 (en) | 1987-07-22 | 1987-07-22 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2517726B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE510487C2 (en) | 1997-09-17 | 1999-05-31 | Ericsson Telefon Ab L M | Multilayer PCB |
| JP4771873B2 (en) * | 2006-06-27 | 2011-09-14 | 未来工業株式会社 | Soundproof sheet body |
| DE112021004492T5 (en) | 2020-08-27 | 2023-07-06 | Denso Corporation | VEHICLE DISPLAY DEVICE |
-
1987
- 1987-07-22 JP JP18302787A patent/JP2517726B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6425597A (en) | 1989-01-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |