JP2517118B2 - Data flow device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow apparatus using a processor having an arithmetic unit for performing product-sum operation at high speed and an associative memory connecting the processors, and more particularly It is strongly related to neural network devices, which have great potential.

2. Description of the Related Art As a data flow device related to a conventional neural network device and configured as an analog,
For example, USP 4,719,591 (Jan, 12,1988) is typical.
This relates to a hopfield type neural network device, and FIG. 9 is a configuration diagram thereof. Operational amplifier 62
The output 63 of the above is added in an analog manner at the node 60 in the connection matrix 61, and is input to the operational amplifier 62 again. In this device, the connection is fixed by hardware.

Further, there is no data flow device related to the conventional neural network device that is digitally configured by using an associative memory. Further, regarding the hierarchical neural network device, there is no example of effective hardware, which is limited to software simulation on a computer.

Subsequently, an example of a conventional processor is shown in FIG. This device is a device for obtaining the sum of products of two inputs 10a and 10b continuously given. According to the programmed procedure, the control unit 16 instructs the product-sum operation, and the adder 12 adds the output of the multiplier 11 and the output of the previous one which is fed back via the output latch 13 to perform the product-sum operation. Get the sum of products 17

Next, an example of a conventional associative memory is shown in FIG. The associative comparison memory unit (CAM) 24 is a CAM word line (C) from the address decoder (ADEC) 25 according to the address (A) 41.
AMWL) 43. The random access memory unit (RAM) 23 is CAM WWL43 from ADE C25 or CAM.
It is accessed by the CAM sense line (CAMSL) 44 which is asserted when the data of the CD 40 and the CAM 24 match by 24. That is, the operation modes are normal read (NR) 34, normal write (NW) 32, associative read (ASR) 35, and associative write (A
It has four modes, SW) 33, and is controlled by the control unit (CTRL) 28. CTRL28 switches selector (SEL) 27,
CAMWL43 for normal access, CAMSL44 for associative access
To the RAM word line (RAMWL) 42. The valid bit (Vb) 65 indicates whether or not the word is valid. The CAM data (CD) 40 is the input / output of the CAM 24 and the RAM data (R
D) 39 indicates the input / output of the RAM 23.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, as a data flow device related to a neural network device, since it is a fixed analog device in the above-mentioned hopield model, flexibility is applied,
It also has a problem of low accuracy. Further, regarding the hierarchical model, there is a problem that the processing time becomes long in software simulation. In addition, all models are desired to be realized by digital circuits in terms of accuracy and flexibility, but they require enormous amount of hardware mainly in networks and currently have no parts to realize them efficiently. Here, the flexibility means that the connection state can be easily changed. For example, it can be dynamically changed by software.

Further, when the product-sum calculation is continuously performed by the above-mentioned processor, the program shown in FIG. 3 is required to terminate the processing when a predetermined condition is satisfied. There are two possible end conditions: (1) number of loops and (2) sum of products result. FIG. 3 (a) is an example of ending only by the number of loops, and even if the sum of products result satisfies the end condition on the way, the processing is continued until the loop ends, and the processing time becomes long. There is. Further, FIG. 3B is an example of ending with the number of loops or the sum of products result, and there is a problem that the program itself becomes long and the processing time eventually becomes long because two condition judgment statements are required.

In the associative memory as described above, the address A40 or the input CD40 to the associative comparison memory unit is required at the time of reading. Therefore, in order to sequentially read from the data written in the associative memory, for example, the procedure of notifying the device that writes to the associative memory and the address to the device that reads the associative memory and then starting the read for the first time become. That is, there is a problem that processing other than read is required, control becomes complicated, and processing time becomes long.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a data flow device that is flexible, highly accurate, high speed, and has a small amount of hardware by using a high speed processor and a high speed and easily controlled associative memory.

Means for Solving the Problems In order to solve the above problems, the present invention (1) connects the outputs of a plurality of processors in common to a bus, and the buses are accessed by a plurality of associative memories. Is a data flow device in which one layer is configured by connecting to the input of the above, and the output of the associative memory in the Nth layer (N is a natural number) is input to the processor of the (N + 1) th layer.

According to the present invention, in addition to the above configuration (1), (2) the processor is a multiplier, and the output of the multiplier and its own 1
An adder that adds the previous output, a condition determiner that monitors the output of the adder and generates an interrupt when a preset condition is satisfied, and a control device that ends the calculation by the interrupt It has an arithmetic unit consisting of.

Further, according to the present invention, in addition to the above configuration (1) or (2), (3) the associative memory can be read by an address decoder, an additional bit indicating a data attribute for each word, and the additional bit. , A priority assigned decoder for selecting one address of the indicated words, an associative comparison memory unit for storing a first identification number which is accessed by the address indicated by the address decoder, and an address indicated by the address decoder. , Or a second identification number input from the outside and the first identification number stored in the associative comparison memory unit are compared in the associative comparison memory unit, and a match is detected, or the priority is added. A random access memory part in which part or all of the word is accessed by the address indicated by the decoder.

With the configuration (1), the data flow device of the present invention simultaneously compares the identification numbers of the processors in a plurality of associative memories and fetches the data when they match, so that the hardware required for the connection is small and the associative memory is used. The connection can be easily changed by rewriting.

Further, in the processor, according to the configuration (2) described above, the condition determiner constantly monitors the sum of products result, and when a predetermined condition is satisfied, an interrupt is generated and the process ends. Therefore, since it is not necessary to determine the sum of products result by the program, the program becomes short and the processing speed can be increased. Further, since the result can be monitored during the next product-sum operation, the monitor overhead does not occur.

Further, the associative memory, by the configuration (3) described above, monitors the field of the identification number in the output of the processor, compares it with the identification number stored in the associative comparison memory unit, and fetches the data if they match. Since this means the connection between the processor and the associative memory, the connection relation can be dynamically changed by software by rewriting the associative comparison memory unit, which increases flexibility. Also, since this connection can be realized by one bus, the amount of hardware required for the network is small. Further, since the processor sequentially reads the valid data in the associative memory without any address and without wasteful cycles, the processing speed can be increased.

Embodiment FIG. 1 is a block diagram of a data flow device in an embodiment of the present invention. Here, 1a to 1d are processors, and 2a and 2b
Is an associative memory, 3 is a bus, 23 is a random access memory unit (RAM), 24 is an associative comparison memory unit (CAM), 50 is data, and 51 is an identification number.

The processors 1a and 1b output the data 50 and the identification number 51 to the bus 3. Here, the identification number 51 is a unique number of the processor. The associative memories 2a and 2b compare the identification number 51 with the stored identification number in the CAM 24 and fetch the data 50 in the RAM 23 when they match. This means one layer of the data flow device. Then, the associative memories 2a and 2b output the data to the processors 1c and 1d in the next layer, respectively. These are processor 1
It means the connection between a and the processors 1c and 1d, and the connection between the processor 1b and the processors 1c and 1d.

Next, FIG. 2 shows a block diagram of a processor in one embodiment of the present invention. In FIG. 2, 10a and 10b are inputs, 11 is a multiplier, 12 is an adder, 13 is an output latch, 14 is a condition determiner, 15 is an interrupt signal, 16 is a controller, and 17 is a sum of products.

The operation of the processor configured as above will be described below. Multiplier 11 has inputs 10a and 1
Multiplies with 0b. The adder 12 adds the output of the multiplier 11 and the product sum 17 which is the previous addition result stored in the output latch 13. The condition determiner 14 monitors the sum of products 17 and generates an interrupt signal 15 when it satisfies a predetermined condition. The control device 16 controls the execution of the program and the end control by interruption.

The effect of speeding up according to this embodiment will be described with reference to a program example for performing the product-sum calculation shown in FIG. Note that this is an example written similar to Motorola's MC68000 assembler code, and will be similar for other microprocessors. In FIG. 3A, the number of steps is smaller, but the end determination condition is only the number of loops, and the conventional processor continues processing until the loop ends even when the product-sum result satisfies the end condition. Processing time becomes long. Further, FIG. 3 (b) is an example of ending with the number of loops or the sum of products result. Since this requires two condition determination statements, the number of steps in the program increases, and the processing time eventually increases. In the present embodiment, the condition determiner 14 constantly monitors the sum of products 17 to check the end condition, so it is not necessary to describe the end condition determination by the product sum in the program. After all, the program equivalent to that shown in FIG. 3B can be realized at high speed with the program shown in FIG.

When a neuro element is realized by the processor of this embodiment, it is very effective in terms of high speed.
This is because, in the neuro element, the product-sum operation of the two data of the preceding stage output and the weight is performed, and then the output is determined by the function of the product-sum and the output shown in FIG.
FIG. 4 (a) shows a threshold function, which outputs 0 when (sum of products <x) and 1 when (x = <sum of products). Fig. 4 (b)
Is a piecewise linear function (0 when sum of products = <y), (y <
A linear value corresponding to the product sum is output when the product sum <z), and 1 is output when (z = << product sum). Here, the output of the preceding stage and the weight are both 0 or more. Therefore, the sum of products increases monotonically, so that the sum of products is greater than or equal to x in FIG.
When the above is reached, the process may be terminated.

Next, FIGS. 5 (a) to 5 (c) are configuration diagrams of the associative memory in the embodiment of the present invention, and FIG. 6 is a list of operation modes of the present embodiment. FIG. 5 (a) is an overall configuration diagram,
(B) is a state output signal generation circuit diagram in the control unit (CTRL) 28, and (c) is a circuit diagram of a priority-added decoder (PDEC) 26 that generates an address or an address at the time of reading. In FIG. 5, 20 is a write bit (Wb), 21 is a read bit (Rb), 22 is a used bit (Ub) (the above 3 bits are additional bits), and 23 is a random access memory section (RA).
M), 24 is an associative comparison memory unit (CAM), 25 is an address decoder (ADEC), 26 is a priority decoder (PDEC), 27 is a selector (SEL), 28 is a control unit (CTRL), and 29 is a write end. Signal (WEND), 30 is a read end signal (REND), 31 is a read request signal (RREQ), 32 is a normal write signal (NW), 33
Is an associative write signal (ASW), 34 is a normal read signal (NSW)
R), 35 is associative read signal (ASR), 36 is addressless read signal (NAR), 37 is all reset (ARST), 38 is partial reset (PRST), 39 is RAM data (RD), 40 is CAM
Data (CD), 41 is address (A), 42 is RAM word line (RAMWL), 43 is CAM word line (CAMWL), 44 is C
AM sense line (CAMSL), 45 is an addressless read word line (NARWL), 46a to 46c are gates, and 47 is a latch.

The operation of the embodiment of the associative memory configured as described above will be described with reference to FIGS. 5 and 6. The following description is premised on the use as a connection mechanism between processors in the data flow device.

First assert all reset 37 (ARST = 1),
Purge all words. This is the first operation using the associative memory, for example, an operation performed immediately after the power is turned on. Specifically, all of Wb20 that means written, Rb21 that means read, and Ub22 that means the area used by the user are set to 0. For normal initialization, partial reset
Assert 38 (PRST = 1) to purge the word for user use. This is associative memory RAM23 and CAM24
This is an operation performed before updating all the used areas of. Specifically, Wb20, which means written, and Rb21, which means read, are all set to 0.

Subsequently, the identification number is set in the CAM 24 from the CD 40 prior to the data transfer using the associative memory. Normal light 32
(NW = 1) is asserted, A41 is decoded by ADEC25, CAMWL43 is asserted, and CD40 is written to CAM24. Also, CTRL28 transmits CAMWL43 to RAMWL42 via SEL27,
Write RD39 to some or all of 23. At this time, Ub22 indicating the area used by the user is set at the same time. This completes the setting prior to transfer.

Subsequently, the data is transferred from the processor to the associative memory. Assert the associative light 33 (ASW = 1) to drive CD40 to C
Assert the matching CAMSL44 by associative comparison in AM24. C
TRL28 transmits CAMSL44 to RAMWL42 via SEL27, and writes RD39 to a part or all of RAM23. However, this is limited to the area used by the user, that is, the word with Ub = 1. At the same time, Wb20, which means the end of writing, is set. Then, when the data transfer from the processor to the associative memory is completed, that is, when the associative memory receives all the data, the associative memory asserts WEND29. This is when all writing to the user-used area has finished, so Ub =
It is asserted when Wb20 of 1 is all 1. Actually, Ub ＝
In the word of 0 (area not used by the user), Wb = 0, so it is necessary to show this area as already written. As shown in (i) of FIG. 5 (b), the OR of the inverted signal of Wb20 and Ub22 is displayed. And all and get WEND29.

Finally, the processor in the next layer reads the associative memory. Assert Addressless Read 36 (NAR = 1), determine which word the RDEC 26 should read and assert NARWL 45. CTRL28 is NRWWL45 via SEL27 to RAMWL42
And read part or all of RAM23 to RD39.
At this time, Rb21 is set at the same time. Here, the associative memory asserts RREQ31 when transferring data to the processor of the next layer, that is, when there is valid data to be read in the associative memory. This is when there is a word that has been written but not read in the user use area, so that Wb = 1 and Rb in the area of Ub = 1.
Asserted when there is a = 0 word. Actually, Ub ＝
Since Wb = 0 in the word of 0, it is not necessary to consider this area, and as shown in (ii) of FIG. 5 (b), the inversion of Rb21 and Wb21
OR all 20 AND's and get RREQ 31.

Further, the associative memory asserts REND30 when the data transfer to the processor in the next layer is completed, that is, when all the valid data in the associative memory are read. Since this is the time when all are written in the user use area and then all are read, it is asserted when Wb and Rb of the area of Ub = 1 are all 1. Actually, it is necessary to show that the writing and reading are both completed in the area of Ub = 0. As shown in (iii) of FIG. 5B, the inverted signal of Ub22 and Rb2
And RAND30 is obtained by ANDing all the ANDs of 1, Wb20 and Ub22.

For address generation during addressless read, one of the read candidate words may be selected, and the circuit is as shown in FIG. 5 (c). In the present embodiment, the word with Wb = 1 and Rb = 0 is a read candidate, and the AND of the inversion of Wb20 and Rb21 corresponds to the bit indicating the read candidate. NARWL45 can be obtained by taking the AND of these and NAR36. Here, when at least one NARWL45 is asserted, the gates 46a and 46 will be set so that the others do not become 1.
Selection of only one word is realized by suppressing the transmission of candidates sequentially with b and 46c. After read, NARWL45 is transmitted to Rb21 via latch 47 and set.

When asserting the normal read 34 (NR = 1), set A41 to A
Decode with DEC25, assert CAMWL43, and CAM24 to CD4
Lead to 0. In addition, CTRL28 is CAMWL43 via SEL27
Inform AMWL42 and read part or all of RAM23 to RD39.

Further, when the associative read 35 (ASR = 1), the CD 40 is associatively compared with the CAM 24 and the matching CAM SL 44 is asserted. CTRL28
Transmits CAMSL44 to RAMWL42 via SEL27 and reads part or all of RAM23 to RD39. The two modes of NR and ASR are not used in the data flow device of the present invention, but are necessary for memory testing.

As described above, according to the present embodiment, the prioritized decoder 26 sequentially designates valid data words so that consecutive valid data is sequentially read without the value of the address 41 or the associative comparison memory unit 24. can do.
The next level of processors can read from the available ones and use them to start processing. Since no unnecessary waiting time is generated, the processing can be speeded up. Further, the connection relation between the processors can be flexibly realized by rewriting the connection information of the associative comparison memory unit.

Due to the above characteristics, a high-speed and flexible data transmission mechanism can be realized especially in a neural network device. Next, these will be described in detail. In addition,
Regarding neural networks, detailed explanations are given in neural network information processing (Hideki Aso, Industrial Books).

7 (a) and 7 (b) are configuration diagrams of an embodiment of a hopfield type neural network device using the data flow device of the present invention, and FIGS. 8 (a) and 8 (b) are hierarchical types using the same. It is a block diagram of the Example of a neural network apparatus. 1a-1d, 1o-1 in these figures
r, 1x to 1w are processors, 2a to 2d, 2i to 2l are associative memories, 3,3a and 3b are buses, 22 is used bits (Ub), 23, 23a and 23
b is a random access memory unit (RAM), 24 is an associative comparison unit (CAM), 50a and 50b are data, 51 is an identification number, 54 is a weight,
55a to 55d are external inputs, and 56a to 56d are external outputs.

First, FIGS. 7A and 7B will be described. This corresponds to the hopfield type model in which four neuro elements are connected to each other.

Each of the processors 1a to 1d incorporates the arithmetic unit of the present invention, which corresponds to a neuro element.

The associative memories 2a to 2d correspond to connections between processors, and CA
The identification numbers of all the processors are stored in M24 (for example, 1a, 1b, 1c, 1d are stored in the CAM 24 of the associative memory 2a in FIG. 7A) to realize the connection between all the processors.

The neuro element determines the output by two numerical values, that is, the sum of products of the output data of the preceding processor and the weight of the coupling between the neuro elements. Associative memory to achieve this
RAM of 2a to 2d is divided into two, data 50 in 23a and weight 5 in 23b
Store 4 and feed them to the processor. The weight 54 is set in advance before starting the transfer operation.

The operation is as follows. The associative memories 2a to 2d have an identification number 51.
Are compared by the CAM 24 and the data 50 is taken into the RAM 23a when they match. The data 50 corresponds to the data output from the neuro element. The processors 1a to 1d extract the data 50 from the RAM 23a and the weight 54 from the RAM 23b by the above-mentioned addressless read, perform the sum of products operation, and determine the next output. Next, the processors 1a to 1d look at the vacancy of the bus 3 and output the data 50 which is the operation result together with the identification number 51 and writes it in the associative memories 2a to 2d. By repeating this until the processor output converges, a given proposition, for example, the solution of the traveling salesman problem can be obtained.

As described above, in this method, only one bus 3 is required as a network, and it can be realized with a small amount of hardware.

Next, two embodiments of the hierarchical model will be described with reference to FIG. The area around the associative memory is the same as in FIG. 7 (b). This means that four inputs are connected to all four neuro elements in the input layer, four neuro elements in the input layer are connected to all four neuro elements in the intermediate layer, and finally four outputs in the intermediate layer are output. It is a model of three connected layers.

First, FIG. 8 (a) will be described. Associative memory 2a ~
Connections between the external inputs 55a to 55d and the processors 1a to 1d are described in 2d, and connections between the processors 1a to 1d and the processors 1o to 1r are described in the associative memories 2e to 2h. External inputs 55a to 55d consisting of the data 50 and the identification number 51 are input to the bus 3a, and the data 50 is fetched in the word in which the identification numbers of the CAMs 24 of the associative memories 2a to 2d match. At the same time, processor 1a ~
1d sequentially reads from the words written in the associative memories 2a to 2d. Efficient read can be realized by the addressless read using the above-mentioned priority-added decoder. The processors 1a to 1d carry out a product-sum operation of the data 50 read from the associative memories 2a to 2d and the weight 54, and when the determined function value is obtained, output it to the bus 3b.

Then, the same operation is repeated from the bus 3b to the external outputs 56a to 56d. This time, the data output to the bus 3b is captured by the associative memories 2e to 2h. At the same time processor 1o ~ 1r
Reads sequentially from the word written in the associative memories 2e to 2h. The processors 1o to 1r perform a product-sum operation of the data 50 read from the associative memory and the weight 54, and output to the external outputs 56a to 56d as soon as the determined function value is obtained. With the above, one inference process is completed. Learning is realized by rewriting the weight of the associative memory. this is,
For example, it is realized by transferring data in the reverse direction of the inference process. Teacher input (correct answer in pattern recognition) is input from external outputs 56a to 56d and transmitted in the opposite direction of inference. Each processor updates the weight of the associative memory by calculating the weight according to an algorithm such as backpropagation. Since each processor can operate in parallel, high speed processing is possible.

Next, FIG. 8 (b) will be described. This is an example in which FIG. 8 (a) is used in a time division manner, and the amount of hardware is small. The associative memories 2i to 2l are connected to the external inputs 55a to 55d and the processors 1a to 1d shown in FIG.
The connections between 1a-1d and processors 1o-1r are stored together. For example, the associative memories 2a and 2e in FIG.
For i, the processors 1a and 1o correspond to 1x.

External inputs 55a to 55d composed of the data 50 and the identification number 51 are input to the bus 3, and the data 50 is fetched into the word in which the identification numbers of the CAMs 24 of the associative memories 2i to 2l match. At the same time, the processors 1x to 1w sequentially read from the words (55a to 55d) written in the associative memories 2i to 2l. Efficient read can be realized by the addressless read using the above-mentioned priority-added decoder. Processor 1x-1w
Is the data 50 read from the associative memories 2i to 2l and the weight 54.
The sum of products is calculated according to the function as the input layer, and the value is output to the bus 3 again together with its own identification number.

Then, the same operation is repeated for this intermediate data. The associative memories 2i to 2l are identified by the identification number 51 on the bus 3.
The CAM24 match is determined and the data 50 is loaded. At the same time, the processors 1x to 1w sequentially read from the words (1a to 1d) written in the associative memories 2i to 2l. Processors 1x to 1w use data 50 read from the associative memories 2i to 2l.
And the weight 54 are summed, and a value is obtained according to a function as an output layer and output to external outputs 56a to 56d. As described above, one inference process (pattern matching in pattern recognition) is completed. At the time of learning, it is realized by rewriting the weight of the associative memory as in the case of FIG.

In the above hopfield type and hierarchical type embodiments, considering that the input / output relationship in the neuro element is as shown in FIG. It is very effective in terms of speeding up. Further, since the connection relation and the weight can be realized by rewriting the associative comparison memory unit and the random access memory unit of the associative memory, respectively, they can be easily changed by software and a very flexible system can be constructed. In addition, by using the associative memory that stores this connection relation, it is possible to realize a network between neuros with a small amount of hardware. Further, since this is easily realized by a digital circuit, high accuracy can be expected.

EFFECTS OF THE INVENTION As described above, in the data flow device according to the present invention, it is possible to dynamically change the connection relationship between the processors by software by rewriting the associative memory unit, so that an extremely flexible system can be realized. . Also, since this connection can be realized by one bus, the amount of hardware required for the network is small. In addition, since the valid data of the associative memory device can be sequentially read sequentially,
The processing speed can be increased. By using the arithmetic unit and the associative memory device, it can be realized by a digital circuit, and both accuracy and flexibility are improved. Further, the processor of the present invention can terminate the processing by generating an interrupt when a predetermined condition is satisfied. Therefore, since it is not necessary to determine the sum of products result by the program, the program becomes short and the processing speed can be increased.

Further, the associative memory according to the present invention can sequentially read from valid data without any address or the value of the associative comparison memory unit, and the processing speed can be increased. And, the data flow device using these processors and associative memory is very easily and naturally applicable to both hopfield type and hierarchical type neural network devices,
Realize a system that is fast, highly accurate, flexible, and has a small amount of hardware. With great expectations for the future potential of neural network devices, research has been actively conducted,
The present invention is extremely useful in both research and product development.

[Brief description of drawings]

FIG. 1 is a block diagram of a data flow device in one embodiment of the present invention, FIG. 2 is a block diagram of a processor in one embodiment of the present invention, and FIG. FIG. 4 is a relational diagram of sum of products and output in the neuro element, FIGS. 5A to 5C are configuration diagrams of the associative memory in one embodiment of the present invention, and FIG. 6 is an operation of the associative memory in the same embodiment. Mode list diagram, FIGS. 7 (a) and 7 (b) are configuration diagrams of an embodiment of a hopfield neural network device using the data flow device of the present invention, FIG. 8 (a),
(B) is a configuration diagram of an embodiment of a hierarchical neural network device using the data flow device of the present invention, FIG. 9 is a configuration diagram of a conventional hopfield type neural network device, and FIG. 10 is a configuration diagram of a conventional processor. FIG. 11 is a block diagram of a conventional associative memory. 1 ... Processor, 2 ... Associative memory, 3 ... Bus, 10
...... Input, 11 …… Multiplier, 12 …… Adder, 13 …… Output latch, 14 …… Condition judge, 15 …… Interrupt signal, 16 ……
Controller, 17 ... Sum of products, 20 ... Light bit (Wb), 21
…… Read bit (Rb), 22 …… Used bit (Ub), 23
...... Random access memory (RAM), 24 ...... Associative comparison memory (CAM), 25 ...... Address decoder (ADE)
C), 26 ... Decoder with priority (PDEC), 27 ... Selector (SEL), 28 ... Control section (CTRL), 29 ... Write end signal (WEND), 30 ... Read end signal (REND) , 31 ...
… Read request signal (RREQ), 32 …… Normal write signal (N
W), 33 ... Associative write signal (ASW), 34 ... Normal read signal (NR), 35 ... Associative read signal (ASR), 36 ... Addressless read signal (NAR), 37 ... All reset ( ARST), 38 ... Partial reset (PRST), 39 ... RAM data (RD), 40 ... CAM data (CD), 41 ... Address (A), 42 ... RAM wordline (RAMWL), 43 ... … CAM
Word line (CAMWL), 44 …… CAM sense line (CAMS
L), 45 ... Read word line without address (NARW
L), 46 ... Gate, 47 ... Latch, 50 ... Data, 51
…… Identification number, 54 …… Weight, 55 …… External input, 56 …… External output.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location G11C 15/00 G11C 15/00 D (72) Inventor Minoru Kagawa 1006 Kadoma, Kadoma-shi, Osaka Matsushita (72) Inventor Masaaki Kano 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

(57) [Claims] 1. By connecting the outputs of a plurality of processors to a bus in common and connecting the bus to the inputs of a plurality of associative memories accessed by the identification numbers of the processors,
A data flow device that configures a hierarchy and uses an output of an associative memory of an Nth hierarchy (N is a natural number) as an input to a processor of an N + 1th hierarchy. 2. The processor includes a multiplier, and an adder that adds the output of the multiplier and the output of the previous one of itself.
Patents characterized by having an arithmetic unit consisting of a condition determiner that monitors the output of the adder and generates an interrupt when a preset condition is satisfied, and a controller that terminates the arithmetic operation by the interrupt. The data flow device according to claim 1. 3. The associative memory has priority to select an address decoder, an additional bit indicating a data attribute for each word, and an address of one of the words indicated by the additional bit as readable. Associated decoder, an associative comparison memory unit that is accessed by the address indicated by the address decoder and stores a first identification number, and an address indicated by the address decoder or a second identification number input from the outside and the associative comparison Part or all of the word is accessed by an address which is detected as a match by comparing the first identification number stored in the memory unit with the associative comparison memory unit or an address indicated by the decoder with priority. The random access memory unit according to claim 1 or 2, characterized in that Tafuro apparatus.