JPH0370053A - Memory access control system - Google Patents

Abstract

PURPOSE:To develop a software with high efficiency by fractionalizing the range within a bank window by the size of the bank window shown by an address space multiplied by an optional exponent of '2'. CONSTITUTION:An address data recognition means 7 is provided to recognize the value of an address data stored at address data storing means 30, 31, and an address controlling means 8 is provided to switch the output of an address data changeover controlling means 6 to a part of an address outputted by a memory accessing means as a part of the address of a memory and to output it. That is, the address data storing means are provided has enough for fractionalizing the bank window, and the address data recognizing means is provided to recognize the address data stored in the address data storing means. Thus, the best number and size for the bank window can be selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory for a computer system, and more particularly to a memory access control method suitable for accessing a memory composed of a plurality of storage banks.

[Conventional technology]

Generally, a central processing unit (CPU) with X bits of directly accessible address information can access 28 address spaces.

However, out of the 28 address spaces that the CPU has, only a limited portion is allowed to be used, and accessing a memory capacity larger than the address space is limited to this limited address space. There are cases where this is desired.

Conventionally, as a method for accessing a memory capacity larger than the address space that can be directly accessed by the CPU, as described in Japanese Patent Application Laid-open No. 129854/1982, information corresponding to an upper address of the memory is sent to address data recognition means. When the CPU accesses the memory, the data of the address data recognition means is used as the upper address of the memory, and the lower address is given as the address output by the CPU. By giving addresses to memory in this way, the CPU can access memory capacity that exceeds the address space that can be accessed directly, so the user cannot use memory that exceeds the limited address space as described above. I can do it.

The operation of the above-mentioned prior art will be explained by way of example.

The CPU has 16-bit address information and 8-bit data, and also has an address that the user is permitted to use, that is, an address that is output when accessing memory that exceeds the address space that the CPU can directly access. A111M (note is undefined, A4) *ga means any address from AOOOH to AFFFII) (The address area corresponding to the address output when the CPU accesses the memory is called the bank window) .

The memory capacity that such a CPU accesses using the bank window is assumed to be 16 bytes.

FIG. 2 shows a block diagram of an example of the configuration of a circuit that implements the above-mentioned prior art.

In FIG. 2, 1 is a CPU, 2 is a memory whose capacity exceeds the address space that can be directly accessed by the CPU 1, 5 is an address data recognition means for storing an address corresponding to the upper address of the memory 2, and 4 is a bank window for the CPU 1. 5 is a memory selection signal generating means for outputting a signal indicating that the memory 2 is to be accessed when the address A4 is outputted; 5 is an address data write signal for generating a signal to be written to the address data recognition means 3, which is address data; In the generation means, a is an address bus, b is a data bus, 0 is a memory selection signal, d is a write signal for writing address data, and . is address data corresponding to the upper address of the memory 2.

Referring to FIG. 2, an explanation will be given of the operation when accessing a portion of the bytes in the memory 2016 that corresponds to ζ at the address of the memory 2.

To perform such an operation, the address data recognition means 3 requires two picts, and the lower address 12 of the memory 2
The lower 12 bits of address bus a are connected to the bit.

First, the CPU 1 writes address data @21, which is an upper address, to the address data recognition means 3. In other words, the CPU 1 outputs 12" to the data bus b, and the address data write signal generation means 5 receives the write signal d. By outputting, @I2# is stored in the address data recognition means 3 as address data.

Next, when the CPUI outputs 〇 〇 〇 H to the address, the memory selection signal generation means 4 activates the selection signal O of the memory 2. Therefore, for the address of memory 2, the upper 2 bits are the output @2'' of the address data recognition means 3, and the lower 12 bits are the lower 12 bits (y) of the directly connected CPU1. The operation of accessing A-B actually costs 20 yen of memory 2.

can be accessed.

The above operation can be expressed as a memory map as shown in FIG.

The left side of Figure 5 is the memory map of CPU 1, A0
This shows that φ8 is a bank wind.

The right side shows the contents of the memory 2, and according to the value written to the address data recognition means 5, O=)+◆8ヲha//O
s 1+11 to bank 1, 2*+ cost, all banks 2
．． 3 plasters + *! Let i be bank 3. In FIG. 5, as described above, the address data recognition means 5 receives @2.
By writing ', it is shown that the CPU 1 can access the memory 202141B corresponding to the A threat OH by accessing the bank window A04#. Similarly, if the value to be written to the address data recognition means 3 is @0"@""3",
When the CPU 1 accesses the bank window, bank 0, bank 1, . Punk 5 has access.

Furthermore, when there are a plurality of bank windows, in the conventional technology, the address data recognition means has as many as the number of bank windows, and the value of the address data storage means is switched for the bank window accessed by the CPU 1, and the memory is giving to Furthermore, when changing the size of the bank window, the number of addresses directly connected to the CPU among the addresses given to the memory is changed.

However, in the prior art, addresses to which bank windows are assigned are determined based on the concept of the computer system, and the size of each bank window is also fixed.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the fact that there are many types of memory usage patterns such as application cage software, and the memory is primarily allocated to the bank window of the CPU. Therefore, in a computer system where the bank wind is subdivided, when accessing continuous large data or programs, it is necessary to write data to the address data recognition means for the number of subdivisions, and it is necessary to change the puncture. When executing software with a large number of data, there is a problem in that the number of steps for writing to the address data recognition means increases and it takes time.

In addition, if the size of the bank window is increased and there is only one bank window, when data is transferred between punctures, it takes time and effort to do so via another area, and furthermore, if the bank window is divided into Since the switching range of memory selection is larger than in the past, there was a problem in that data and programs spanned between banks, necessitating extra bank switching.

An object of the present invention is to reduce the number of bankwinds within the bankwind area determined by the computer system so that an appropriate bankwind can be obtained when an application exploiter accesses the memory. subdivide or
It is an object of the present invention to provide a memory access control method that allows switching to one bank window.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a memory access means for outputting and accessing an address to a memory, an address data recognition means for storing a plurality of address data, and an address data recognition means for storing a plurality of address data. address data switching control means for switching and outputting address data stored in the address data recognition means; address data recognition means for recognizing the value of the address data stored in the address data recognition means; and address control means for switching and outputting the output of the address data switching control means and a part of the address output by the memory access means as part of the address of the memory, based on the recognition result output by the address data switching control means. ing.

In other words, the address data recognition means is provided with address data recognition means sufficient to subdivide the bank window, and address data recognition means stored in the address data recognition means. Also, Ia! of the address data recognition means! An address control means is provided for switching between the address accessed by the c'pu and the address data stored in the address data recognition means based on the recognition result, and the address data outputted from the address control means is given to the memory. There is.

The address data recognition means obtains a recognition result by, for example, comparing the value of the address data stored in the address data recognition means with a predetermined value.

Further, the present invention provides memory access means for outputting and accessing addresses to memory, address data recognition means for storing a plurality of address data, and switching between the address data stored in the address data recognition means. In a memory access control device having address data switching control means for outputting, a predetermined value is added to the value of the address data stored in the address data recognition means based on the address output by the memory access means. addition means; and address switching signal generation means for generating a switching signal for the address data switching control means based on the address output by the memory accessing means and the value of address data stored in the address data recognition means. It may be provided.

The value added by the addition means is determined based on the address output by the memory access means.

Further, the present invention provides memory access means for outputting and accessing addresses to memory, address data recognition means for storing a plurality of address data, and switching between address data stored in the address data recognition means. Memory access system g4i! which has address data switching control means to output. a calculation means for calculating address data to be stored in the address data recognition means; and a write control means for independently writing address data into the address data recognition means or simultaneously writing calculation results of the calculation means. may also be provided.

Further, the present invention provides a plurality of bank windows in an address area that is permitted to be used in an address space owned by a CPU, and provides a plurality of banks on a memory, at least a part of which can be accessed in common from each bank window, An information processing system configured to perform memory access, comprising a plurality of setting means for setting data specifying a bank to be accessed, and any one of the data specifying the bank set by these setting means. There is also provided a device comprising a selection means for selecting a valid bank, and a bank address generation means for generating an address of a bank to be accessed based on data specifying the bank selected by the selection means.

[Effect]

The operation of the present invention will be explained using FIG.

In Figure 1, 1 is the CPU, 2 is the memory, 30.31
4 is a memory selection signal generating means for outputting a selection signal indicating that the memory 2 has been accessed; 5 is a signal for writing data into the address data recognition means 50 and 51; This is address data write signal generation means that outputs the address data write signal. 6 is an address data switching control means for switching the address data of each address data storage means 30.31, 7 is an address data switching control means for recognizing the contents of the address data recognition means 30.31, and 8 is an address data switching control means 6. Address control means switches between the address data from and the address from the CPU 1 based on the recognition result of the address data recognition means 7. a is an address bus and connects the lower m bits to the memory 2. Further, b is a data bus, 0 is a memory selection signal dO indicating selection of memory 2 when CPU 1 accesses the bank window.

dl is a write signal for writing address data into the address data storage means 50.31.

In FIG. 1, when subdividing the bank window, for example, a predetermined value indicating that the bank window is to be subdivided is written into the address data recognition means B51, and the CPU 1 subdivides the bank window. Based on the address of CPIJ 1, the address data switching control means 6 appropriately switches the address data of the address data recognition means A50 and B51, and the address data recognition means 7 changes the value of the address data recognition means B31. By comparing the above-mentioned predetermined value indicating that the bank wind is to be subdivided, it is recognized that the bank wind is to be subdivided, and based on this recognition result, the address data control means 8 The data of the data switching control means 6 is applied to the memory 2. As a result, the upper n bits of the address in memory 2 are changed to the address data la! It is given from address means Al5o or address data recognition means B31, and the lower m bits are CP.
Since it is given from U1, the bank window is an area indicated by the address space of 211.

Next, when doubling the bank window size, a value indicating that the bank window size is to be increased is written into the address data recognition means B31. And C
When PtJl accesses the bank window, the address data switching control means 6 selects the address data recognition means Al5oO value regardless of the address accessed by %CPUI.

Then, in order to double the size of the bank window, the address control means 8 transfers the lowest one bit of the n-bit data of the address data recognition means A30 to the CPU 1.
(the m1001th bit from the lower order) and supplies it to the memory 2.

As a result, the upper (n-1) bits of the address of the memory 2 are given from the address data recognition means A30, and the lower (m+1) bits are given from the CPU 1, so the bank window is an area indicated by the address space of 2'1. Therefore, the size is twice as large as when it is subdivided as described above.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, in a CPU that supports a 16-bit address bus and an 8-bit data bus, each
It is assumed that there are only two consecutive bank windows of bytes on the CPU's memory mag at address A**133++4)H, and that the memory Q capacity that can be accessed by the two bank windows is 16 bytes. Furthermore, when the address data corresponding to the bank wind of B10) is 10", the bank wind of B10) is A++
It is assumed that a part of the byte is switched from a bank window of 1 to a continuous bank window of 8.

FIG. 4 shows a block diagram of a circuit that implements the memory access control method of this embodiment.

In the figure, 1 is a CPU, and 2 is a memory with a capacity of 16 bytes (14 address lines).

30.31 is a means for storing address data, and 5
0 is a puncture register A that stores the upper 2-bit address given to memory 2 when CPU 1 outputs address A12, and 31 is a puncture register that stores the address of the upper 2 bits given to memory 2 when CPU 1 outputs address B. Top 2 given to
There is a bank register J''e that stores bit addresses.

A decoder 4 generates a signal indicating that the memory 2 has been selected when the CPU 1 outputs the bank window address A++*H or B+1+1. 5ticPU
This is an xio control unit that generates a signal for writing address data to bank register A30 or bank register B31 by writing to I10 of 1.

60.61 is a selector that switches and outputs the data of bank register A50 and bank register B31, and 60 is the highest address of memory 2, A13 (
From now on, the address of memory 2 will be prefixed with "M" to distinguish it from the address of CPU 1. For example, MA
15), 61 is MA12
Perform switching to .

Furthermore, 7 is a comparator that compares the value of bank register A301 with +0'' to determine whether the bank window is 8 and 1 byte or 4 and 2 bytes.
is a selector that controls the address given to the memory 2 based on the result of the comparator 7.

a is an address bus, which connects CPU1 to memory 2.
Addresses A11 to AO are connected to MA11 to MAO. +12 is CPU address A12, b is data bus, C is chip select signal indicating memory selection,
do, l are bank register A30, bank register B3
A write signal for writing address data to 1; 0 is an address connected to MA15 of memory 2; el is an address connected to MA12 of memory 2;

If the value of the bank register B31 is +01 as a result of the comparison by the comparator 7, the selector 8 gives the address A12 (+12) of the CPU 1 to the memory 2, and if it is not @o#, the selector 8 gives the f direct address from the selector 61 is controlled to be given to memory 2.

Next, let's define memory 2. Since the capacity of memory 2 is 16 bytes, the address of memory 2 is
Shown in the range of ooooII to 3FFFH, 00 buds bank 0.1*++M bank 1.2 axis bone, bank 2
．． 5+*bone, is set as bank 3.

Next, the operation of this embodiment will be explained.

For example, as shown in Figure 5, CPU1 is at address A*+
The case where memory bank 0 is accessed by outputting *lI and memory bank 2 is accessed by outputting address B0 will be explained.

First, CPU 1 writes "0" to bank register A50 and +21 to bank register B31. Then, when CPU 1 outputs address A*++1, decoder 4 activates step select signal 0 of memory 2. , selectors 60 and 61 are bank register A30
The f-direction is switched so that the f-direction is output. Furthermore, the comparator 7 recognizes that the value of the bank register B51 is not ``0''. The selector 8 receives the w@ data from the comparator 7 and outputs the value from the selector 61. as a result,
+0", which is the value of address A4 and A30 of memory 2, is given. As mentioned above, MA11 to MAO of memory 2 are given the value of address A30 of memory 2.
Since 11 to AO are directly connected, the CPU 1 outputs B to address A4 and accesses the bank wind, so + is added to Q4 corresponding to bank 0 of memory 2.
4 can be accessed by 11 people.

Next, when CPIJl outputs address B0, decode 4 activates chip select signal 0 of memory 2, and selector +60.61 outputs the value of bank register B31, contrary to the above. Switch to . The operations of comparator 7 and selector 8 are the same as described above, and the output of selector 8 becomes the value of selector 61. as a result,
MA i 3 in memory 2.

MA12 contains @2”, which is the value of bank register B51.
is given, so by the operation of CPU 1 outputting address B4*★ and accessing puncture window B,
In this embodiment, banks O, i, and 2.3 can be accessed from both puncture window A and bank window B, respectively.

Next, a case where the bank wind size is set to 8 bytes will be explained.

First, as mentioned above, 10" is stored in bank register B31.
By writing , the bank window becomes 8 bytes, so write @Oj' to bank register B151.
Then, when the CPU 1 outputs the address A1+1, the selectors 60 and 61 are switched so that the value of the bank register A30 is output.

Furthermore, the comparator 7 detects that the value of the bank register B51 is 101.
Recognizing this, the selector 8 switches to output the address A12 (B12) of the CPU 1. 7doV
becomes @0# of the upper bit of bank register A30.

Therefore, CPU t is address human bone 4h.

By outputting , and accessing bank wind person, Q bone + ★ irises corresponding to bank O of memory 2 can be accessed.

Next, when the CPU 1 outputs 4B to the address B address 4 and accesses the bank window B, the selector 60°61
receives the value of comparator 7 and switches to output the value of bank register A30. And selector 8 is A12
will be switched to output. Address B + * Bone B A
12 is @1”, so MA1 given to memory 2
2 becomes @1'', and MA13 becomes @Om of the upper bit of bank register A30.Therefore, by the operation of CPtJl outputting address 73****H and accessing bank window B, bank 1 of memory 2 is accessed. corresponding 10
φ3 can be accessed.

Furthermore, if @21 is written to bank register A30 from this state, CPU 1 writes address A*++H,
Output 84 to 4 and bank wind A.

The operations of selectors 60, 61 and selector 8 when accessing B are the same as those described above, so memory 2
The upper bit of bank register A30 given as MA15 changes from 101 to @1#, and the remaining MA12
For MAO, the operation is the same as described above. Therefore, by the operation of CPtJl outputting address A12 and accessing bank window A, bank 2 of memory 2 is
24-Threat, corresponding to , can be accessed at address 73
By outputting 4* threat H and accessing bank window B, 3*+1 corresponding to bank 3 of memory 2 can be accessed.

As mentioned above, 10' was determined as the value for switching the size of the reserved ab bank quindo in bank register B31.
By writing the value, address A+41φH,B
What used to be two bank winds A and B with cost n can be made into one continuous bank wind that combines the two bank winds A and B, and the banks that can be accessed from one core bank wind are , it is a combination of two banks that can be accessed from two bank windows.

The concept of bank wind size conversion is shown in FIG. 6 from the memory 2.

In (a) of Fig. 6, the bank wind is set to 4, and each byte is
, H. By writing the bank number to bank register A50 or bank register B51, 4 can be accessed from bank window A or B for each byte. Figure 6(b) shows the bank wind A
, B are combined into 8 bytes, and if the value written to the bank register is the bank number, by writing the bank number 10'' or @2'' to the bank register A30, 8 bytes are written. It can be accessed from Bank Wind A or B.

Next, an example will be described in which the bank number is continuous even if the bank window size is changed from 4 bytes to 8 bytes, and the value written to the bank register does not become discontinuous such as @Ojj @21J. do.

FIG. 7 shows a block diagram of only a portion related to address switching control to be applied to the memory 2. In FIG.

In Fig. 7, 2 is memory, 3o, 31 is bank register A1 bank register B, 60.6j is a selector that switches puncture register A, BC) ([), 7 is a comparison between the value of bank register B and @0''. comparator, 80.81
is a selector that switches and controls the address given to memory 2,
a12 is the CPU address A12.

First, when the bank window size is 4 bytes (bank register A30 is other than @0"), selector 60.6
The operation of No. 1 is the same as that of the previous embodiment, and selectors 80 and 81 store the upper bits of the values of bank register A50 and bank register B31 in memory 20MA13,
The lower bits are switched to be given to MA12 of memory 2, respectively. Thereby, bank register A
When 0# is written to 50 and 12'' is written to bank register B31, CPU 1 outputs address A *44kHz and accesses bank window^, as in the previous embodiment, and bank 0 can be accessed. 3
Bank 2 can be accessed by outputting 3+++H and accessing bank window B.

Then, when the bank window size is set to 8 bytes (1 shift of bank register B31 is @0''), the comparator 7 recognizes 10''. As a result, selector 60.61 is
Regardless of the address accessed by the CPU 1, the value of the bank register A30 is switched to be output. Then, the selector 80 is switched so that the lower bits of the bank register A30 are given to the memory 20MA13, and the selector 81 is switched so that the address A12 of the CPU 1 is given to MA12 of the memory 2.

As a result, when @0'' is written to bank register A30, when CPU1 outputs address A04) and accesses bank window A, @0'' of the lower bit of bank register A30 is given as MA13, and CPU
Since A12 of 1 @0” is given as MA12,
Q*+*N of bank 0 of memory 2 is accessed. Then, when CPU1 outputs address B buds and accesses bank window B, MA13 becomes "0" as in the +H access to address A44 mentioned above, and cpt
Since '1' of A12 of yt is given as MA12, 144M1 of bank 1 of memory 2 is accessed.

Next, if 1# is written to bank register A30, CP
UI is 46 to address A 64! When bank window A is accessed by outputting +, 1" of the lower bit of bank register A30 is given as MA15, and the CPU
Since 10'' of Al1 of 1 is given as MA12,
2φ0B of bank 2 of memory 2 is accessed. Then, when CPU 1 outputs address B *bone and accesses bank window B, MA13 becomes 1', which is the same as the access with AO, and 11 of A12 of CPU 1.
' is given as MA15, 1 is accessed to 34#44 of bank 3 of memory 2.

As described above, in this embodiment, when the size of the bank window is set to 8 bytes, by setting the input value to be written to bank register A30 as "0"1#, it is possible to access 16 bytes of memory 2. .

The concept of the above operation is shown in FIG. 8 from the memory. In (a) of Fig. 8, the bank wind is set to 4, and each byte is A.
, B, and (b) shows the case where bank winds A and B are combined into 8 bytes.

In this embodiment, as shown in FIG. 8, the bank window is 4 and bank 0. Bank 1 corresponds to bank 0 when the bank window is 8, and bank 0 when the byte is set to 4, and bank 2 when the bank window is 4. Bank 5 and 8 are bank 1 during bite.
correspond, and even if the bank window is changed from 4 bytes to 8 bytes, the bank numbers are continuous.

In the above embodiment, the output of the bank register is first
Switching is performed at the address of H, and after the switching, switching control between the value of the bank register and the address of CPtJ is performed, but the order of the two may be changed. The effects of the present invention can be obtained by having means for switching the value of each bank register with respect to a memory address, and means for switching between the value of the bank register and the address of the CPU.

Furthermore, as information for switching the bank window size, it was assumed that "@0" was written in bank register B for convenience, but the value of bank register A and the value of bank register B are compared, and if the values are equal, the bank Changing the size of the window, or changing the size of the bank window when the straightness of bank register B is smaller than the puncture register Ao value.Additionally, 1 or more bits of data is added in addition to the address data written to the bank register. However, there is also a method of changing the size of the bank window depending on the value of the added data.

Next, an example will be shown in which when the bank window size is set to 8 bytes, the accessible range of memory can be set by shifting the range to 4 bytes.

FIG. 9 shows a block diagram of the address switching control portion given to the memory when the conditions such as the bank window size and the memory capacity are the same as in the previous embodiment.

2 in Figure 9 is memory! 50.51 is bank register A
, bank register B, 80.81 is bank register A5
0. The selector for switching the address data of bank register 3331, 9 is the 1 shift and CP of bank register A30.
The adder 10 adds the address of U1 to A12, and the adder 10 compares the value of bank register B31 with 10", and selector 8
This is an address switching signal generation section that generates a switching signal of 0.81.

For example, when the CPU accesses bank 0 of memory 2 by outputting address A12 and accessing bank window A, and accessing bank 2 by outputting address B0 and accessing bank window B. explain.

First, 10'' is written in bank register A30 and @2'' is written in bank register B31.Then, when CPU 1 outputs address ``*+'', adder 9 writes ``@2'' to bank register A30.

CPUI address A12 @01 and bank register A
The value of 50 is added and output. Then, the address switching signal generation unit 10 determines that the value of the bank register B31 is ``0''.
It recognizes that the address A12 of the CPU 1 is 'mO', and outputs a switching signal to the selectors 80 and 81 to select the output from the adder 9. As a result, the selectors 80 and 81 select the output from the adder 9. The value obtained by adding 1st shift@0'' of register A30 and @0' of A12 is stored in MA15. of memory 2. Since it is given as MA12, bank 0 of memory 2 can be accessed by the operation of CPU 1 outputting address A12 and accessing bank window.

Next, when CPU1 outputs address B4H14M,
The address switching signal generation section 10 includes a bank register B51.
The value of is not @0# and the address A12 of CPU1
is 11", and outputs a switching signal to the selector 80.81 to select the value of the bank register B31. As a result, the selector 80.81 selects the value of the bank register B31 from 1 straight 12" to the memory 2. MAIS,
Since it is given as MA i 2, bank 2 of memory 2 can be accessed by the operation of CPU 1 outputting address B*+* and accessing bank window B.

Next, if you want to set the bank window to 8 bytes, write @0'' to bank register B51.
The address switching signal generation section 10 includes a bank register B51.
Recognizing that the value of is @01, selector 80.81
A switching signal is output to select the output from the adder 9 regardless of the address accessed by the CPU 1.

From the above, the values given as M2S and MA12 of memory 2 will be the value of bank register A30 when the CPUI outputs address A12, and the value of bank register A30 when outputs address 73 * cost φyo. @
1” is added to the value.

Therefore, if you write "IO" to bank register A30, C
Bank 0 of memory 2 can be accessed by PU1 outputting addresses ), **+, and accessing puncture window A, and bank register A5 is accessed by outputting address B0φyo and accessing bank window B.
Bank 1 of memory 2 corresponding to the value of 0 plus 11'' can be accessed.

Similarly, if 11" is written to bank register A30, CP
t11 is address A*+4. ! , B4))) By outputting 9 and accessing bank winds A and B,
Each bank 1. If bank 2 is accessed and +21 is written to bank register A30, bank 2. Bank 3 can be accessed.

The concept of the above operation is shown in FIG. 10 from the memory 2.

In Figure 10 (a), the bank wind is 4 and each byte is A.
, B is shown, and 佽) is punk wind A.
, B are combined into 8 bytes. In this embodiment, as shown in FIG. You can access it at any time.

In this example, when address A4)+ga, 7344h4kM is output in the order of bank windows A and B, the CPU
Since the address 332 of 1 changes from +0'' to ''1#, the adder 9 could use A12 as the value to add to the bank register A30, but the value to add to the bank register A30 depends on the address for setting the bank window, etc. A, A
For example, if address 33446 is set to +1 for address B and Q4, when changing from B11 to Q**□, A14 of the addresses of CPU1 will be +0” to 1
11, the address added to bank register A50 is set to A14.

Next, an embodiment in which a value other than an address is added to the bank register A30 will be described with reference to FIG.

FIG. 11 is a block diagram of the switching part of the address given to the memory, where 2 is the memory, 30.31 is the bank register A, B, 4 is the decoder, 80.81 is the selector, 9 is the adder, and 90 is the adder. An addition value switching unit switches the value added to 9 to 10# “1” according to the set bank window address, 10 is an address switching signal generation unit, and a is an address bus.

The addition value switching unit 90 sets the addition value to +01 by the output of the decoder 4 when the CPU 1 outputs the first half of the address of the bank wind with a small address, and sets the addition value to +1' when the CPU 1 outputs the second half of the address with a large address. From 0 or more, this embodiment can realize the same function as the embodiment shown in the block diagram of FIG. 9, and the difference from the embodiment is that For A12 which changes from 0# to 61m, the decoder 4 determines the first half and the second half of the bank wind, and only the part where the value to be added is changed from 102 to "1".

In addition, in the embodiments described so far, switching control was performed for the value written to the bank register, but it is possible to have an independent write address to the bank register for each different bank window size. There is also a method of performing switching control on the value written to the bank register itself.

A block diagram of a circuit implementing the method is shown in FIG.

1E12 figure-C12 is me%! J,! So, 31c/< bank registers A and B, and bank register A30
uses a level latch type register, and before writing to the bank register Al5o (1H' of the write signal
When storing in terms of period, the value of data bus b is output as is from bank register A30 (@L'' period). 4 in FIG. 12 is the first half of the bank window. 50 is a decoder that recognizes the second half of the bank register A30 and bank register B.
31 is an I10 control unit that writes address data to
Depending on the I10 write address, a write signal can be output independently to bank register A30 and bank register B31,
At the same time, a write signal is output. In FIG. 12, 6 is a selector that switches and controls the values of bank registers A50 and B31, 9 is an adder that adds +1 to the value of bank register A50, and 11 is a selector that switches between the output of adder 9 and the data bus. a is an address bus, and b is a data bus.

First, when subdividing the bank window into two, addresses that can be written independently are used in bank register A30 and bank register B31, and address data is written. 0 Next, when setting the bank window to one, use an address that can be written to bank register A30 and bank register B31 at the same time, and write address data. , I10 control unit 50 switches selector 11 so that the value of adder 9 is output, so the value written to puncture register B31 becomes the value obtained by adding 11# to the value of bank register A3G.

As a result, when writing is performed to bank register A30 and bank register B31 at the same time, when the CPUI accesses the bank window, it becomes one continuous bank window in a pseudo manner.

As explained above, in this embodiment, two bank windows access the same bank,
By setting the two bank windows together and shifting the banks one by one, two banks can be accessed consecutively, so when transferring data between banks,
All you have to do is rewrite the value in the bank register.

Furthermore, since two banks can be accessed consecutively by combining the two bank windows, the number of times values are written to the bank register can be reduced when accessing successive large data or programs.

In addition, in the embodiments described above, the bank window size is switched to 4 bytes or 8 bytes, and the memory capacity to be accessed is set to 16 bytes, but in the present invention, it can be freely set to an exponential multiple of 2. For example, if you have L bank registers, the bank window size can be reduced to 1/A. By controlling the switching of the bank window size based on the correlation between the values of the L bank registers, the bank window size can be made an arbitrary integral multiple of 1/A. Furthermore, the size of the bank window is determined by how many bits the address from the CPU is connected to the memory, and when m CPU addresses are connected to the memory, the range of the address space is 21. If the number of bits supported by the bank register is n bits, the number of banks is zf1, and the memory that the CPU can access using the bank window is 2 (Il + 4).
This is the address space range shown by .

Further, although the memory in the embodiment has been described as a single element of 16 bytes, there is no limit to the number or capacity of memory elements by generating a chip select signal suitable for the memory element as a data signal.

As described above, by arbitrarily setting the number of bits of the address of the CPU connected to the memory and the number of bits of the bank register, according to the present invention, it is possible to access any memory using a bank window of 20 times the exponent. . In addition, in this embodiment, a CP is used as a device that accesses the memory.
Although U is used, the effects of the present invention can also be obtained by using a device that can access memory, such as a DMA controller during DMA transfer.

〔Effect of the invention〕

According to the present invention, the bank window range determined by the computer system can be subdivided by the bank window size indicated by the address space multiplied by an arbitrary exponential of 2, so that various application software etc. , the optimum number and size of bank windows can be selected taking into account the time and effort required to transfer data between banks, the time and effort required to allocate banks to bankwinds, etc., and this has the effect of enabling efficient software development.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the configuration of the present invention, FIG. 2 is a block diagram showing an overview of the configuration of the prior art, FIG. 3 is a diagram showing a memory map of an example of the prior art, and FIG. 9, 11, and 12 are block diagrams showing the configuration of an embodiment of the present invention. FIG. 5, FIG. 6, FIG. 8, and FIG. 10 are conceptual diagrams of a memory in an embodiment of the present invention. 1...CPU, 2...Memory, 5.30.31...
- Address data recognition means, 6... Address data switching control means, 7... Address data recognition means, 8...
・Address control means? ... Adder, a ... Address bus, i-electronic\ 1L21 Fig. 2 Fig. 4 [¥] Fig. 5 Fig. 6 (f2) (b) Fig. 9 Group 10 ((1) (b ) Tsuta 7th Figure 8 (of (b) :1iA11t￥] Bu 12 Figure

Claims (1)

[Claims] 1. Memory access means for outputting and accessing addresses to memory; address data storage means for storing a plurality of address data; and address data stored in the address data storage means. A memory access control device comprising: address data switching control means for switching and outputting address data; address data recognition means for recognizing the value of the address data stored in the address data storage means; and recognition output from the address data recognition means. Based on the results,
Memory access control characterized by comprising: address control means for switching and outputting the output of the address data switching control means and a part of the address output by the memory access means as part of the address of the memory. method. 2. The address data switching control means switches and outputs the address data stored in the address data storage means based on the address output by the memory access means and the recognition result output by the address data recognition means. The memory access control system according to claim 1, characterized in that: 3. Memory access means for outputting and accessing addresses to memory; address data storage means for storing a plurality of address data; and address data for switching and outputting address data stored in the address data storage means. A memory access control device having a switching control means, an addition means for adding a determined value to a value of address data stored in the address data storage means based on an address output by the memory access means; and address switching signal generating means for generating a switching signal for the address data switching control means based on the address output by the memory accessing means and the value of the address data stored in the address data storage means. Characteristic memory access control method. 4. The memory access control system according to claim 3, further comprising addition value determining means for determining the value to be added by the adding means based on the address output by the memory access means. 5. Memory access means for outputting and accessing addresses to the memory, address data storage means for storing a plurality of address data, and address data for switching and outputting the address data stored in the address data storage means. A memory access control device having a switching control means, a calculation means for calculating address data to be stored in the address data storage means, and address data independently written to the address data storage means, or A memory access control method characterized by comprising a write control means for simultaneously writing calculation results. 6. Memory access is performed by providing a plurality of bank windows in an address area that is permitted to be used in the address space of the CPU, and providing a plurality of banks on the memory that can at least partially be accessed in common from each of the bank windows. The information processing system includes a plurality of setting means for setting data specifying a bank to be accessed, and one of the data specifying the bank set by these setting means as valid. An information processing system comprising: a selection means for selecting; and a bank address generation means for generating an address of a bank to be accessed based on data specifying the bank selected by the selection means.