JP2513835B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2513835B2 JP2513835B2 JP1098110A JP9811089A JP2513835B2 JP 2513835 B2 JP2513835 B2 JP 2513835B2 JP 1098110 A JP1098110 A JP 1098110A JP 9811089 A JP9811089 A JP 9811089A JP 2513835 B2 JP2513835 B2 JP 2513835B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- substrate
- ground
- hole
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体装置内のキャパシタの接地構造，特にMMIC（Mo
nolithic Microwave IC）のMIM（Metal Insulator Meta
l）構造キャパシタの接地構造に関し， 低接地インダクタンス，小占有面積の特徴を有するバ
イア孔方式によって機械的なストレスフリーのキャパシ
タ接地構造を得ることを目的とし， 基板上に順に積層された下部電極，誘電体膜，上部電
極で構成されるキャパシタと，該基板の下側に接地電位
に接続される接地導電層とを有し，該基板は該キャパシ
タの下側に貫通孔が形成され，該下部電極は該貫通孔を
通じて該接地電極層と電気的に接続され，該誘電体膜及
び該上部電極は該貫通孔に対応する部分が欠如されたパ
ターンに形成されているように構成する。DETAILED DESCRIPTION [Overview] The grounding structure of a capacitor in a semiconductor device, especially MMIC (Mo
nolithic Microwave IC) MIM (Metal Insulator Meta
l) Regarding the grounding structure of the structural capacitor, the purpose is to obtain a mechanical stress-free capacitor grounding structure by the via hole method, which has the characteristics of low grounding inductance and small occupying area. A capacitor having a dielectric film and an upper electrode, and a ground conductive layer connected to a ground potential on the lower side of the substrate, the substrate having a through hole formed on the lower side of the capacitor, The electrode is electrically connected to the ground electrode layer through the through hole, and the dielectric film and the upper electrode are formed in a pattern lacking a portion corresponding to the through hole.
本発明は半導体装置内のキャパシタの接地構造，特に
MMICのMIM構造キャパシタの接地構造に関する。The present invention relates to a grounding structure for a capacitor in a semiconductor device, especially
The grounding structure of the MIM structure capacitor of MMIC.
半絶縁性（SI−）GaAs基板を用いたMMICにはMIM構造
の平行平板型キャパシタが多く用いられている。Parallel plate capacitors of MIM structure are often used for MMIC using semi-insulating (SI-) GaAs substrate.
本発明は,MIM構造のキャパシタの低インダクタンスの
高周波接地構造として使用できる。INDUSTRIAL APPLICABILITY The present invention can be used as a low-inductance high-frequency grounding structure for a MIM structure capacitor.
基板として，例えばSI−GaAs基板を用いたMMICにおい
ては,MIM構造のキャパシタが随所に用いられている。In MMICs that use SI-GaAs substrates, for example, MIM structure capacitors are used everywhere.
このキャパシタは，回路によりキャパシタの片側を接
地するものも多数ある。Many of these capacitors have one side grounded by a circuit.
この場合の高周波接地構造としては，次のものがあ
る。In this case, there are the following high-frequency grounding structures.
極細ワイヤボンディング方式（又はリボンボンディ
ング方式） 第２図は極細ワイヤボンディングによる接地構造を説
明する平面図である。Ultrafine Wire Bonding Method (or Ribbon Bonding Method) FIG. 2 is a plan view illustrating a grounding structure by extrafine wire bonding.
図において，絶縁性基板１上に順次キャパシタ下部電
極2,誘電体膜3,キャパシタ上部電極４が形成され，基板
下に形成されている接地（GND）面と下部電極２とを極
細ワイヤ７でボンディングした構造である。In the figure, a capacitor lower electrode 2, a dielectric film 3, and a capacitor upper electrode 4 are sequentially formed on an insulating substrate 1, and a ground (GND) surface formed under the substrate and the lower electrode 2 are connected by a fine wire 7. It is a bonded structure.
バイア（Via）孔方式 SI−GaAs基板を貫通するバイア孔を開け，この孔を通
じて導通をとり接地する方式である。Via hole method This is a method in which a via hole is formed through the SI-GaAs substrate, and conduction is provided through this hole for grounding.
第３図はバイア孔方式の接地構造を説明する断面図で
ある。FIG. 3 is a sectional view for explaining a via hole type grounding structure.
図において,SI−GaAs基板１上に順次キャパシタ下部
電極2,誘電体膜3,キャパシタ上部電極４が形成され，下
部電極２はキャパシタ部より延長した部分で，バイア孔
５内及び基板裏面に形成された接地導電層（接地面）６
に接続される。In the figure, a capacitor lower electrode 2, a dielectric film 3, and a capacitor upper electrode 4 are sequentially formed on a SI-GaAs substrate 1, and the lower electrode 2 is a portion extending from the capacitor portion and formed in the via hole 5 and on the back surface of the substrate. Ground conductive layer (ground plane) 6
Connected to.
μ波帯，或いはmm波帯においては，キャパシタと接地
電位間に直列に入る接地インダクタンスLGNDは回路の安
定性や高利得を得るためにできるだけ小さいことが望ま
しい。例えば,2GHz帯ではLGND＜1nHが必要となる。In the μ-wave band or mm-wave band, it is desirable that the ground inductance L GND that enters in series between the capacitor and the ground potential be as small as possible in order to obtain circuit stability and high gain. For example, in the 2GHz band, L GND <1nH is required.
そのためと，配置の自由度の点からバイア孔方式がよ
く使われる。For that reason, the via hole method is often used in terms of the degree of freedom of arrangement.
バイア孔方式でははLGND＜0.1nHの低接地インダクタ
ンスが得られる。With the via hole method, a low ground inductance of L GND <0.1nH can be obtained.
ところが,10GHz以上の周波数帯ではもっと小さい接地
インダクタンスが要求されることと，キャパシタの占有
面積を小さくするために第３図を変形して第４図の構造
のものが用いられるようになった。However, smaller ground inductance is required in the frequency band of 10 GHz or more, and Fig. 3 is modified to use the structure of Fig. 4 in order to reduce the occupied area of the capacitor.
第４図は従来例の図で，改良型のバイア孔方式の接地
構造を説明する断面図である。FIG. 4 is a view of a conventional example and is a cross-sectional view for explaining an improved via-hole type grounding structure.
第３図においてはバイア孔をキャパシタの外に設けた
のに対して，第４図の構造はキャパシタの真下に設け
て，キャパシタの配置の占有面積を小さくしている。In FIG. 3, the via hole is provided outside the capacitor, whereas in the structure of FIG. 4, the via hole is provided directly below the capacitor to reduce the area occupied by the capacitor.
しかしながら，このような構造を持ったチップを,AuS
n又はAuGe等のろう材を用いてステージにボンディング
する際に，バイア孔内の接地導電層（金あるいは銀メッ
キ層）６がろう材と溶融し，凝固する際に機械的なスト
レスが発生し，キャパシタ部を膨らませたり凹ませたり
して変形させ，誘電体（Si3N4,又はSiO2）層にクラック
を発生させ，そのクラックに金属が侵入してキャパシタ
を短絡させ，或いは動作中に短絡させたりする事故が生
ずることがわかった。However, a chip with such a structure is
When bonding to the stage using a brazing material such as n or AuGe, the ground conductive layer (gold or silver plating layer) 6 in the via hole melts with the brazing material and mechanical stress occurs when it solidifies. , The capacitor part is deformed by swelling or denting, and cracks are generated in the dielectric (Si 3 N 4 or SiO 2 ) layer, and metal penetrates into the cracks to short-circuit the capacitor, or during operation. It turns out that an accident such as a short circuit occurs.
本発明は低接地インダクタンス，小占有面積の特徴を
有するバイア孔方式によって機械的なストレスフリーの
キャパシタ接地構造を得ることを目的とする。It is an object of the present invention to obtain a mechanical stress-free capacitor grounding structure by a via hole method having the features of low grounding inductance and small occupied area.
上記課題の解決は，基板上に順に積層された下部電
極，誘電体膜，上部電極で構成されるキャパシタと，該
基板の下側に接地電位に接続される接地導電層とを有
し，該基板は該キャパシタの下側に貫通孔が形成され，
該下部電極は該貫通孔を通じて該接地導電層と電気的に
接続され，該誘電体膜及び該上部電極は該貫通孔に対応
する部分が欠如されたパターンに形成されている半導体
装置により達成される。A solution to the above problem is to have a capacitor composed of a lower electrode, a dielectric film, and an upper electrode, which are sequentially laminated on a substrate, and a ground conductive layer connected to a ground potential on the lower side of the substrate, The substrate has a through hole formed under the capacitor,
The lower electrode is electrically connected to the ground conductive layer through the through hole, and the dielectric film and the upper electrode are formed by a semiconductor device in which a portion corresponding to the through hole is formed in a pattern. It
本発明は，ストレスが発生するバイア孔上部にはキャ
パシタ構造を形成しないで下部電極のみを残して接地接
続を可能にすることにより，チップのろう付けの際のス
トレスを緩和して，製造歩留の低下と素子の信頼性の低
下を防止するようにしたものである。The present invention alleviates the stress at the time of brazing a chip by forming a capacitor structure above the via hole where stress is generated and leaving only the lower electrode to allow the ground connection, thereby reducing the manufacturing yield. To prevent the deterioration of the device and the reliability of the device.
第１図（１），（２）は本発明の一実施例によるバイ
ア孔方式の接地構造を説明する断面図と平面図である。1 (1) and 1 (2) are a sectional view and a plan view for explaining a via hole type grounding structure according to an embodiment of the present invention.
図において，厚さ75μｍのSI−GaAs基板１上に順次キ
ャパシタ下部電極2,誘電体膜3,キャパシタ上部電極４が
形成され，下部電極２はキャパシタ部分でバイア孔５内
及び基板裏面に形成された接地導電層６に接続される。In the figure, a capacitor lower electrode 2, a dielectric film 3, and a capacitor upper electrode 4 are sequentially formed on a SI-GaAs substrate 1 having a thickness of 75 μm, and the lower electrode 2 is formed in the via hole 5 and the back surface of the substrate at the capacitor portion. Connected to the ground conductive layer 6.
誘電体膜3,キャパシタ上部電極４はバイア孔５の上部
で欠如したパターンに形成する。The dielectric film 3 and the capacitor upper electrode 4 are formed in a pattern that is missing above the via hole 5.
ここで，キャパシタは 下部電極２が厚さ0.3μｍのAuGeNiAu膜， 誘電体膜３が厚さ0.2μｍのSi3N4膜， 上部電極４が厚さ２μｍのAuメッキ膜 で構成される。Here, in the capacitor, the lower electrode 2 is composed of a AuGeNiAu film having a thickness of 0.3 μm, the dielectric film 3 is a Si 3 N 4 film having a thickness of 0.2 μm, and the upper electrode 4 is composed of an Au plating film having a thickness of 2 μm.
又，接地導電層６は厚さ15μｍのAuメッキ膜で形成さ
れる。The ground conductive layer 6 is formed of a 15 μm thick Au plating film.
前記したように，キャパシタ接地構造において考慮し
なければならない点は次のように要約することができ
る。As described above, the points to be considered in the capacitor grounding structure can be summarized as follows.
キャパシタは低接地インダクタンス，低直列抵抗で
あること。The capacitor should have low ground inductance and low series resistance.
チップ上のキャパシタ配置に自由度があること。 There is flexibility in the placement of capacitors on the chip.
キャパシタ配置の占有面積が小さいこと。 The area occupied by the capacitor is small.
この例においては，上記の考慮点およびは第３図
と第４図の構造の中間位の値となるが，キャパシタを短
絡させる致命的な欠陥を生じることはない。In this example, the above-mentioned considerations and are intermediate values of the structures of FIGS. 3 and 4, but do not cause a fatal defect that short-circuits the capacitor.
ろう材にAuSnを用いてチップのろう付けを行ったとこ
ろ，多数試料についてキャパシタの短絡は全然発生しな
かった。従って，製造歩留の向上と素子の信頼性向上に
有効であることが確かめられた。又，接地インダクタン
スは0.05nHと低い値が得られた。When AuSn was used as the brazing material, the chips were brazed and no short circuit of the capacitors occurred for many samples. Therefore, it was confirmed to be effective in improving the manufacturing yield and improving the reliability of the device. In addition, the ground inductance was as low as 0.05nH.
第５図（１），（２）は本発明を適用したMMICの一例
を示す平面図と回路図である。5 (1) and 5 (2) are a plan view and a circuit diagram showing an example of an MMIC to which the present invention is applied.
このMMICは１〜8GHz広帯域２段増幅器（利得≒8dB）
で，チップサイズ1.3mm×1.7mmのSI−GaAs基板に形成さ
れ，キャパシタC2,C4に本発明が適用されている。This MMIC is a 1-8 GHz wide band 2-stage amplifier (gain ≈ 8 dB)
Thus, the present invention is applied to capacitors C 2 and C 4 which are formed on a SI-GaAs substrate having a chip size of 1.3 mm × 1.7 mm.
GaAs MES FET Q1,Q2はイオン注入によりチャネル領域
を形成し，抵抗ＲもSI−GaAs基板にイオン注入して抵抗
体としている。回路図の矩形はマイクロストリップ線路
を表している。The GaAs MES FETs Q 1 and Q 2 form a channel region by ion implantation, and the resistor R is also ion-implanted into the SI-GaAs substrate to form a resistor. The rectangle in the circuit diagram represents the microstrip line.
キャパシタC2は１個のバイア孔，キャパシタC4は２個
のバイア孔５を経由して，接地端子VGGに接続されてい
る。The capacitor C 2 is connected to the ground terminal V GG via one via hole and the capacitor C 4 via two via holes 5.
以上説明したように本発明によれば，低接地インダク
タンス，小占有面積の特徴を有するバイア孔方式によっ
て機械的なストレスフリーのキャパシタ接地構造を得る
ことができる。As described above, according to the present invention, it is possible to obtain a mechanical stress-free capacitor ground structure by the via hole method having the features of low ground inductance and small occupied area.
従って,MMICの製造歩留と信頼性を向上することがで
きる。Therefore, the manufacturing yield and reliability of MMIC can be improved.
第１図（１），（２）は本発明の一実施例によるバイア
孔方式の接地構造を説明する断面図と平面図， 第２図は極細ワイヤボンディングによる接地構造を説明
する平面図， 第３図はバイア孔方式の接地構造を説明する断面図， 第４図は従来例の図で，改良型のバイア孔方式の接地構
造を説明する断面図， 第５図（１），（２）は本発明を適用したMMICの一例を
示す平面図と回路図である。 図において， １は基板でSI−GaAs基板， ２はキャパシタ下部電極， ３は誘電体膜， ４はキャパシタ上部電極， ５はバイア孔， ６は接地導電層 である。1 (1) and 1 (2) are a sectional view and a plan view for explaining a via hole type grounding structure according to an embodiment of the present invention, and FIG. 2 is a plan view for explaining a grounding structure by extra fine wire bonding. FIG. 3 is a cross-sectional view illustrating a via-hole grounding structure, FIG. 4 is a view illustrating a conventional example, and a cross-sectional view illustrating an improved via-hole grounding structure, FIG. 5 (1), (2) FIG. 2A is a plan view and a circuit diagram showing an example of an MMIC to which the present invention is applied. In the figure, 1 is a substrate, an SI-GaAs substrate, 2 is a capacitor lower electrode, 3 is a dielectric film, 4 is a capacitor upper electrode, 5 is a via hole, and 6 is a ground conductive layer.
Claims (1)
膜，上部電極で構成されるキャパシタと， 該基板の下側に接地電位に接続される接地導電層とを有
し， 該基板は該キャパシタの下側に貫通孔が形成され， 該下部電極は該貫通孔を通じて該接地導電層と電気的に
接続され， 該誘電体膜及び該上部電極は該貫通孔に対応する部分が
欠如されたパターンに形成されていることを特徴とする
半導体装置。1. A substrate comprising a lower electrode, a dielectric film, and an upper electrode, which are sequentially stacked on a substrate, and a ground conductive layer connected to a ground potential on the lower side of the substrate. A through hole is formed under the capacitor, the lower electrode is electrically connected to the ground conductive layer through the through hole, and the dielectric film and the upper electrode lack a portion corresponding to the through hole. A semiconductor device, which is formed in a patterned pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1098110A JP2513835B2 (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1098110A JP2513835B2 (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02276269A JPH02276269A (en) | 1990-11-13 |
| JP2513835B2 true JP2513835B2 (en) | 1996-07-03 |
Family
ID=14211189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1098110A Expired - Lifetime JP2513835B2 (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513835B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208726A (en) * | 1992-04-03 | 1993-05-04 | Teledyne Monolithic Microwave | Metal-insulator-metal (MIM) capacitor-around-via structure for a monolithic microwave integrated circuit (MMIC) and method of manufacturing same |
| JP2006173595A (en) * | 2004-11-22 | 2006-06-29 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device and on-board radar system using the same |
| CN105280727A (en) * | 2015-11-06 | 2016-01-27 | 中国电子科技集团公司第十三研究所 | Microwave internal matching power transistor matching capacitor and manufacturing method thereof |
-
1989
- 1989-04-18 JP JP1098110A patent/JP2513835B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02276269A (en) | 1990-11-13 |
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