JPS5843578A - Gaas integrated circuit - Google Patents
Gaas integrated circuitInfo
- Publication number
- JPS5843578A JPS5843578A JP56141994A JP14199481A JPS5843578A JP S5843578 A JPS5843578 A JP S5843578A JP 56141994 A JP56141994 A JP 56141994A JP 14199481 A JP14199481 A JP 14199481A JP S5843578 A JPS5843578 A JP S5843578A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- dielectric layer
- substrate
- integrated circuit
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 abstract description 13
- 238000007747 plating Methods 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 229910001258 titanium gold Inorganic materials 0.000 abstract description 2
- 229910010252 TiO3 Inorganic materials 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＧａＡｌ アナログ集積回路等のＧａＡ・集積
回路に関するちのである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to GaA integrated circuits such as GaAl analog integrated circuits.
ＧａＡｌ電界効果トランジスタ（以下ＧａＡ＠ＦＩＴと
略称する）と分布定数同一路による入出力整合回路から
構成された従来のＧａＡａア！ログ集積回路（以下単に
ＧａＡａ ＸＣと略称する）の構造と製法について、図
面によって説明する。第１図１ａｌ ｌｂ＋け従来のＧ
ａＡａ ＸＣを表わす平面図および断面図である。また
第８図は前記第１図に示す従来のＧ＆Ａａ工Ｃの製法を
表わす工程別断面図であり、なお第２図ＩＪＬＩ〜１（
１１は横方向断面、第８図１１’ｌけ縦方向断面を示す
。The conventional GaAa field-effect transistor (hereinafter abbreviated as GaA@FIT) and an input/output matching circuit with the same distributed constant path are used. The structure and manufacturing method of a log integrated circuit (hereinafter simply referred to as GaAa XC) will be explained with reference to the drawings. Figure 1 1al lb+ke conventional G
FIG. 3 is a plan view and a cross-sectional view showing aAa XC. In addition, FIG. 8 is a cross-sectional view of each process showing the conventional manufacturing method of G&Aa process C shown in FIG. 1, and FIG.
11 shows a transverse cross section, and FIG. 8 11'l shows a longitudinal cross section.
ます゛、オＬ１図（ＪＬＩに示すように厚さｌ ＯＯｐ
ｍの半絶縁性ＧａＡｓ基板（１）上の所定部分＃Ｃ８１
などをイオン注入することに第８図（ｂ＋に示すように
ｎ型妨作層１２１を＠成する。 −１
−つぎに第８図
１０１に示すようにｎ型切作層偉１上にＡｕＧＩＳＮｌ
のリフトオフ合金化によりオーミック接勉をなすソース
電、極−→−−ト←４１３）およびドレイン電極（４）
を形成し、さらに第３図１（１１に示すようにＡｊのリ
フトオフによるショットキゲート電極（６）を形成して
ＧａＡｍ ＩＦＩＴ ′Ｉｒ′Ｉｒ中る。さらに第８
図ｔｅｌに示すように（ｊａＡｓ ＩＦＩＣＴのゲート
４１ ｌ ｆｉｌ側と−５にイン 。゛、O L1 diagram (thickness l OOp as shown in JLI)
Predetermined portion #C81 on the semi-insulating GaAs substrate (1) of
By ion implantation, an n-type blocking layer 121 is formed as shown in FIG. 8 (b+). -1 -Next, as shown in FIG.
The source electrode, electrode (413) and drain electrode (4) which form ohmic contact by lift-off alloying of
A Schottky gate electrode (6) is formed by lift-off of Aj as shown in FIG.
As shown in figure tel (jaAs IFICT gate 41 l fil side and -5 input).
電極１４１側にそれぞれ例えばｃｕ Ａｕ等のリフトオ
フで形成された分布定数回路配線にょる入カ整 ′今回
１＠ ｆ６１および出力整合回路（〕）を形成すること
により、入力端午１８１および一カ端子（９１を有する
第１図１ａｌ（ｂｌに示すＧａＡｓ ＸＣを完成する。By forming the input terminal 181 and the output matching circuit () on the electrode 141 side using distributed constant circuit wiring formed by lift-off such as Cu Au, etc. Complete the GaAs XC shown in FIG.
第１図に示す従来のＧａＡ―工ＣＫ−おい゛てけ半゛絶
縁″性基板１１＋の誘電率−が１３程度であり、自由空
間波長λａｉｒに相当する伝送癲路をＧａＡｓ基板上の
波長に基づいてＧａＡ、ａ ＩＣの入−出カ整命パ４−
７ンが設計され、 ＧａＡｓ １０チツプの大きさもこ
の局方！＆ＩＤＩＭｇｃ ｌ’すＸ、、に！、１ｔｌＬ
ｚ−１９ｍ従ってこのような雫合“回路部の複雑な組合
せからなる実際の（）ａＡｌＩＣにおいては、できるだ
けチップ面積を小さくして高集積化を図ることが要求さ
れる。The dielectric constant of the conventional GaA substrate 11+ shown in FIG. 1 is about 13, and the transmission path corresponding to the free space wavelength GaA,a IC input-output control pattern 4-
7 chips were designed, and the size of GaAs 10 chips is also this pharmacopoeia! &IDIMgc l'suX...! ,1tlL
z-19m Therefore, in an actual (a)AlIC consisting of a complex combination of such drop-combined circuit sections, it is required to minimize the chip area and achieve high integration.
本発明はこのような従来のＧａＡ１１１Ｃの欠点に鑑み
てな寧れたものであｈ％ＧａＡ−基板の表面に形成され
た（口）路パターン上にこのＧａＡｓ基板−よりも高い
誘電率の誘電体層を形成しこ？誘電体層をマイクロ波集
積回路基板のアースとなる放熱部材に接着したのでチッ
プ面積が小さく、かち高集積度の配線を有するＧａＡｌ
ＩＣを提供するものである。The present invention has been developed in view of the drawbacks of the conventional GaA111C. Forming body layers? Since the dielectric layer is bonded to the heat dissipation member that serves as the ground for the microwave integrated circuit board, the chip area is small and GaAl has highly integrated wiring.
It provides IC.
以下、図面に゛従って本無明の一喚施例に２いて説明す
る。Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
第８図は本発明の一実施例になるＧａＡｌＩＣの製法を
示す工程別断面図である。。FIG. 8 is a cross-sectional view of each step showing a method for manufacturing GaAlIC according to an embodiment of the present invention. .
まず第８図（ａｌに示すように第１引ｅ）に相当する従
来ＯＧａＡｓ （ＩＣを牙１．８図の工程に従って形成
する。但し、この際、後述するように入カ雫今回路部（
６）およ渉、、前方整合回路部（７）のパターン寸法は
第１図に示す従来のＧａＡＩＩ工Ｃに比較して小さくな
る。First, a conventional OGaAs (IC) corresponding to FIG. 8 (al) is formed according to the process shown in FIG.
6) The pattern size of the front matching circuit section (7) is smaller than that of the conventional GaAII process C shown in FIG.
つぎに第８図１ｂ＋に示すように、第３図（ａｌに示す
ＧａＡｓ ＩＣ“の上に例えばεが８７程変であ゛り厚
さ力Ｅ １０ ＃ｍのＢａＴｉ０ｊ等の雪電体層叫をス
パッタなどに゛よ′わ形成しためち、ホトレジストＯ’
４をマスクとし゛てスパツタエ゛ツチなどで、入力端子
部（８１お上び出力端子部（９１に対応する誘電体層’
ＩＩＢの一部分子エツチオ７′シンこの部分に′第３−
図１０１に示すようにＴｉＡｕ ’３着およびＡｕメッ
キなどにより金属層Ｑ１を形成する。つぎに第３図１１
１１ Ｋ禾すよ°うにリサトオ７法によ□り二′づの金
属層Ｉの間□の誘電体層□＋ｔａの上′に゛金ＩＴ（ｕ
）を形成する。このような工程によ′）作られたＧａＡ
ｌＩＣ”４才３図＋ｓ−ｉに示すようにムＵメッキを施
したベース幀と４４クロ波集積回路用の回路゛パターン
が投けられたセラミック基板Ｏ＠からなるパシケージに
ゲリ”ツプチ′ツ”プ方式でマクンドする。゛このマク
ントは熱圧着ま゛たはけ入だ付けによ′り行なわれ゛る
。Next, as shown in FIG. 8 1b+, a snow electric layer such as BaTi0j with a thickness force E 10 #m and a thickness force E 10 #m with a variation of ε of about 87, for example, is formed on the GaAs IC shown in FIG. 3 (al). The photoresist O' is formed by sputtering or the like.
4 as a mask, remove the dielectric layer corresponding to the input terminal section (81) and the output terminal section (91) using a sputtering technique or the like.
Part of the molecule of IIB
As shown in FIG. 101, a metal layer Q1 is formed by TiAu'3 plating and Au plating. Next, Figure 3 11
11 Gold IT (u
) to form. GaA produced by this process
As shown in Figure 3 + s-i of ``IC'' 4 years old, a hole is inserted into a passi-cage consisting of a base plated with mu-U plating and a ceramic substrate O@ on which a circuit pattern for a 44 chromatic integrated circuit is cast. ``Makundo'' is done by the ``pudding'' method. ``This macundo is done by thermo-compression bonding or soldering.
本゛発明の一笑・施例は、“入出力のｉ金回′路′の゛
分□”希當数パターンとアース面の間の物質がＧａＡ−
基゛ 板よりも高い誘電率例えばＢａＴｉ０’ｓ等の誘
電体で形成されているため、前述の管゛内□波長λｆは
λａ ｉ ｒｚｉ となう、前記従来のＧａＡ−工・Ｃ
のそれの約％となるので面積も従来のものに比べ約にに
することができる。An example of the present invention is that the material between the rare pattern of the input/output gold circuit and the ground plane is GaA-
Since it is formed of a dielectric material having a higher permittivity than the substrate, such as BaTi0's, the wavelength λf inside the tube is λa i rzi , compared to the conventional GaA-C
Since the area is about % of that of the conventional one, the area can be reduced to about 20% compared to the conventional one.
また特性インピーダンスが５Ｏｎ−の場合に１分布定数
回路の配線の幅とこの配線と誘電体−を介したアースと
の罰の厚さは−等しいこ−とカニ知−られている。した
がってこの発明の−、実施例＃：ｔ＃Ｓ電体ｗＡｉαの
厚さをｌ−０２ｍにし”たので前記従、米のＧａ１Ａｓ
ＩＣの厚さが１ ’０ ’０°ｐ’ｍ、−・の′−絶
縁性、基板＋１１［゛比べ配・線の□幅をイ。にでき、
これによ、り配線の集・積゛度を′高・めるこ゛とがで
きる。It is also known that when the characteristic impedance is 5 On-, the width of the wiring in a monodistributed constant circuit and the thickness of the ground via this wiring and the dielectric are equal. Therefore, in this invention, the thickness of the t#S electric body wAiα was set to 1-02 m, so that the
The thickness of the IC is 1'0'0°p'm, the insulation of the board is +11 [', and the □ width of the wiring is . can be done,
As a result, it is possible to increase the concentration and density of wires.
□なお、この誘□電体層（ＩＣの種類や厚さは・上記−
実施例に限定されるものでなく適当に選ぶこ−とにより
、パターン設計の自由度を大きくするご表ができる□。□Please note that this dielectric layer (the type and thickness of the IC are the same as above-
By making appropriate selections without being limited to the examples, it is possible to create a chart that increases the degree of freedom in pattern design.
゛パ・ ・”また上記本発明の一実施例で
は動作層上にＧａＡ日ＰＥ′ｒを形成したものを゛とり
′あげたが、こ。``Also, in one embodiment of the present invention described above, GaA PE'r was formed on the active layer.
のようなαｊＡｓ ＦｌｎＴに代えショットキダイオー
ドなどの他のＧａ’Ａｓ素子カ；−形成嘔れ九も−のも
含まれることけもちろ入である。、 ・上記説明のよ
うに、本発明は第１の同一パターンに形成されたＧａム
一 基板よりも高い誘電率の誘電体層と；この誘電体層
が接着されアースとなる放熱部材１・よび表面にオ８０
回路パターンを有する絶縁基板よりなるマイクロ波集積
回路基板を設けたのでＧａＡ−ＩＣの面積を小さくする
ことができると共に、配線の高集積化が可能になるとい
う優れた効果を有する。It is to be understood that other Ga'As elements such as Schottky diodes may be used instead of αjAs FlnT. As described above, the present invention includes: a first Ga film formed in the same pattern; a dielectric layer having a higher dielectric constant than the substrate; O80 on the surface
Since a microwave integrated circuit board made of an insulating substrate having a circuit pattern is provided, the area of the GaA-IC can be reduced and the wiring can be highly integrated, which is an excellent effect.
オ１図１８Ｌ１ （ｂ＋は従来のＧａＡＩＩ工Ｃを表わ
す平面図および断面図、オ８図はオ１図のＧａＡｌ１
ＩＣの製法を表わす工程別断面図、オ８図は本発明の一
実施例になるＧａＡＪ工Ｃの製法を表わす工程別断面図
である。
１１１は半絶縁性基板、＋１１けｎｆｉ！Ｊ４ｔｈ１作
層、１３１１４）ｔ＋ｓ＞“°°”７°ＴＯ７−２パ−
ｔ′・ｙ−ｈ＠＠。
（ａｌ ＋７１は入出力整合回路、１８１ （ｉｌ’１
入出力端子、ｔｔαは高誘電体層、（１１） ＃１
金属膜、（１４）けＡｕ メッキへペース、−はマイク
ロ波集積回路用セラミツ゛り基板である。
なお図中、同一符号は同一または相当部を表わす。
代理人 葛 野 信 −
圭
１ゝ
ｔｌ： ゛
Ｉｔ、、、。
ｊ
第１図
＜ｂ）
７
じ
手続補正書（自発）
１．・１１件の表示 特願昭 ５６−１４１９９
４号２、発明の名称 ＧａＡｓ集積回路３、補正
をするｎ
事件との関係 特許出願人
（２）O1 Figure 18L1 (b+ is a plan view and cross-sectional view showing the conventional GaAII process C, O8 is the GaAl1 shown in O1)
FIG. 8 is a cross-sectional view showing the process for manufacturing an IC. FIG. 111 is a semi-insulating board, +11kenfi! J4th1 layer, 13114) t+s>"°°"7°TO7-2 par-
t′・y−h＠＠. (al +71 is an input/output matching circuit, 181 (il'1
Input/output terminal, ttα is high dielectric layer, (11) #1
Metal film, (14) plated with Au plating, - is a ceramic substrate for microwave integrated circuits. In the drawings, the same reference numerals represent the same or corresponding parts. Agent Shin Kuzuno - Kei 1ゝtl: ゛It...... j Figure 1<b) 7 Written amendment to the same procedure (voluntary) 1.・Displaying 11 items Patent application Sho 56-14199
No. 4 No. 2, Title of the invention GaAs integrated circuit 3, Amendment to be made n Relationship to the case Patent applicant (2)
Claims (1)
の表面に形成された能動素子および分布定数線路からな
るオ！の回路パターン゛、このオｌの回／ 路パターン上に形成された前記ＧａＡｓ基板よりも高い
誘電率の誘電体層と、この誘電体層が接着されアースと
なる放熱部材および表面にオ８の回路パターンを有する
絶縁基板よりなるマイクロ波集積回路基板とを備えたＧ
ａＡａ集積回路。 （！１ 誘電体層はＢａＴｉＯｓで形成されることを特
徴とする特許請求の範囲オ１項に記載のＧ＆ムー集積回
路。 （３１オｌの回路パターンの分布定数線路の幅は誘電体
層の厚さと等しいことを特徴とする特許請求の範囲オ１
項に記載のＧ＆ムー集積回路。[Claims] C1l A semi-insulating GaAs substrate, an active element formed on the surface of the GaAs substrate, and a distributed constant line. circuit pattern, a dielectric layer having a higher dielectric constant than the GaAs substrate formed on this circuit pattern, a heat dissipating member to which this dielectric layer is bonded and which serves as a ground, and an O8 layer on the surface. G comprising a microwave integrated circuit board made of an insulating substrate having a circuit pattern.
aAa integrated circuit. (!1) The G&MU integrated circuit according to claim 1, wherein the dielectric layer is formed of BaTiOs. (31) The width of the distributed constant line of the circuit pattern of Claim O1 characterized in that the thickness is equal to
The G & Mu integrated circuit described in Section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141994A JPS5843578A (en) | 1981-09-08 | 1981-09-08 | Gaas integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141994A JPS5843578A (en) | 1981-09-08 | 1981-09-08 | Gaas integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5843578A true JPS5843578A (en) | 1983-03-14 |
Family
ID=15304917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56141994A Pending JPS5843578A (en) | 1981-09-08 | 1981-09-08 | Gaas integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843578A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04321425A (en) * | 1991-04-19 | 1992-11-11 | Kiyoji Kazume | Opening and closing device for flapping roof |
| EP0703614A3 (en) * | 1994-08-31 | 1997-03-12 | Texas Instruments Inc | Flip-clip with heat-conducting layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS523977U (en) * | 1975-06-23 | 1977-01-12 |
-
1981
- 1981-09-08 JP JP56141994A patent/JPS5843578A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS523977U (en) * | 1975-06-23 | 1977-01-12 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04321425A (en) * | 1991-04-19 | 1992-11-11 | Kiyoji Kazume | Opening and closing device for flapping roof |
| EP0703614A3 (en) * | 1994-08-31 | 1997-03-12 | Texas Instruments Inc | Flip-clip with heat-conducting layer |
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