JP2513203B2 - Hybrid integrated circuit mounting method - Google Patents

Hybrid integrated circuit mounting method

Info

Publication number
JP2513203B2
JP2513203B2 JP62016695A JP1669587A JP2513203B2 JP 2513203 B2 JP2513203 B2 JP 2513203B2 JP 62016695 A JP62016695 A JP 62016695A JP 1669587 A JP1669587 A JP 1669587A JP 2513203 B2 JP2513203 B2 JP 2513203B2
Authority
JP
Japan
Prior art keywords
adhesive
substrate
lead frame
attached
mother
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62016695A
Other languages
Japanese (ja)
Other versions
JPS63184392A (en
Inventor
康夫 花岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62016695A priority Critical patent/JP2513203B2/en
Publication of JPS63184392A publication Critical patent/JPS63184392A/en
Application granted granted Critical
Publication of JP2513203B2 publication Critical patent/JP2513203B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Electrical Connectors (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路のマザー基板への実装方法に
関する。
The present invention relates to a method for mounting a hybrid integrated circuit on a mother board.

〔発明の概要〕[Outline of Invention]

本発明は、混成集積回路の実装方法であり、ハイブリ
ツドIC基板に取付けられたリードフレームの側面にマザ
ー基板側に凸部を備えた接着剤または粘着剤付きテープ
を貼付けた状態で各リードの端部をマザー基板の取付用
孔部へ挿入するとともに、上述したテープの凸部をマザ
ー基板に接着し、この後半田付けすることにより、容易
且つ正確な実装を可能としたものである。
The present invention is a method for mounting a hybrid integrated circuit, in which an end of each lead is attached with an adhesive or a tape with an adhesive having a convex portion on the mother substrate side attached to the side surface of the lead frame attached to the hybrid IC substrate. By inserting the portion into the mounting hole of the mother board, adhering the convex portion of the above-mentioned tape to the mother board, and then soldering it, easy and accurate mounting is possible.

〔従来の技術〕[Conventional technology]

第6図は、ハイブリツドIC(混成集積回路)基板
(1)にタイバーカツトされたF型リードフレーム
(2)が取付けられた状態を示す。この後、各リード
(5)の端部をマザー基板(図示せず)の取付用孔部へ
挿入し、半田付けを行う。
FIG. 6 shows a state in which the tie bar cut F-type lead frame (2) is attached to a hybrid IC (hybrid integrated circuit) substrate (1). After that, the ends of the leads (5) are inserted into the mounting holes of the mother board (not shown) and soldered.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の実装方法によれば、第6図に示すよう
に、ハイブリツドIC基板(HIC基板と略す)(1)にリ
ードフレーム(2)を取付け、その後各リード(5)を
マザー基板の取付用孔部へ挿入するまでの間にリード
(5)の先端が広がつたり、曲がつたりしてリード
(5)の間隔が一定ではなくなるため、挿入するのが困
難になることもあつた。また、リード(5)自体の幅が
一定であるため、HIC基板(1)をマザー基板に対して
所定の高さに保持しておくことができなかつた。更に、
半田デイツプの際、浮力のためリード(5)が安定しな
いという問題点もあつた。
According to the conventional mounting method described above, as shown in FIG. 6, the lead frame (2) is attached to the hybrid IC substrate (abbreviated as HIC substrate) (1), and then each lead (5) is attached to the mother substrate. Before the lead (5) is inserted into the hole, the tip of the lead (5) may be widened or bent, and the interval between the leads (5) may not be constant, which may make insertion difficult. It was Further, since the width of the lead (5) itself is constant, it was impossible to hold the HIC substrate (1) at a predetermined height with respect to the mother substrate. Furthermore,
At the time of soldering, the lead (5) was not stable due to buoyancy.

本発明は、上記問題点を解決することができる混成集
積回路の実装方法を提供するものである。
The present invention provides a method for mounting a hybrid integrated circuit that can solve the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、第1図に示すように、リードフレーム
(2)付きハイブリッドIC基板(1)をマザー基板
(4)に取付ける工程を有する混成集積回路の実装方法
において、マザー基板(4)側に凸部を備えた接着剤ま
たは粘着剤付きテープをリードフレーム(2)の側面に
貼付ける工程と、リード(5)の端部をマザー基板
(4)の取付用孔部(6)に挿入するとともに、接着剤
又は粘着剤付きテープの凸部(7)を図3に示すよう
に、マザー基板(4)の例えば上面に沿って折り曲げ
て、これに接着し、半田付けする工程と、接着剤または
粘着剤付きテープ(3)をリードフレーム(2)および
マザー基板(4)から剥がす工程を経て、混成集積回路
を基板上に実装する。
As shown in FIG. 1, the present invention is a hybrid integrated circuit mounting method including a step of mounting a hybrid IC substrate (1) with a lead frame (2) on a mother substrate (4), in which a mother substrate (4) side is mounted. Adhesive or tape with adhesive having a convex portion is attached to the side surface of the lead frame (2), and the ends of the leads (5) are inserted into the mounting holes (6) of the mother board (4). At the same time, as shown in FIG. 3, the convex portion (7) of the adhesive or the tape with the adhesive is bent along, for example, the upper surface of the mother substrate (4), adhered thereto, and soldered, and the adhesive. Alternatively, the hybrid integrated circuit is mounted on the substrate through a step of peeling the adhesive tape (3) from the lead frame (2) and the mother substrate (4).

本発明で使用する接着剤又は粘着剤は、比較的耐熱性
のある樹脂を主成分とし、一時的な仮止め効果を有して
いる一般の接着剤、粘着剤であれば良い。また使用する
テープ(3)は、例えば紙、耐熱性プラスチツク(ポリ
エチレン及びその共重合樹脂(例えばエチレン−酢酸ビ
ニル)、ポリプロピレン、ポリアミド、シリコーン等)
を材料として、或る程度の硬度を有するように比較的厚
く形成する。
The adhesive or pressure-sensitive adhesive used in the present invention may be a general adhesive or pressure-sensitive adhesive containing a resin having relatively high heat resistance as a main component and having a temporary temporary fixing effect. The tape (3) used is, for example, paper, heat-resistant plastic (polyethylene and its copolymer resin (eg ethylene-vinyl acetate), polypropylene, polyamide, silicone, etc.).
Is used as a material and is formed relatively thick so as to have a certain hardness.

〔作用〕[Action]

本発明によれば、HIC基板(1)をマザー基板(4)
に実装する前のリードフレーム(2)の側面に接着剤又
は粘着剤付きのテープ(3)を貼付けておくため、この
テープ(3)によりリード(5)間の間隔を正確に保つ
ことができると共にリードフレーム(2)に貼付けるテ
ープ(3)のマザー基板(4)側に所定間隔をおいて複
数の凸部(7)を形成し、リード(5)を取付用孔部
(6)へ挿入した際、凸部(7)がマザー基板(4)に
接着することにより、半田ディップ時のHIC基板(1)
の浮き上がりを防止することができ、HIC基板(1)を
マザー基板(4)に対して所定の高さに保つことができ
る。
According to the present invention, the HIC substrate (1) is replaced by the mother substrate (4).
Since the tape (3) with an adhesive or a pressure-sensitive adhesive is attached to the side surface of the lead frame (2) before being mounted on, the gap between the leads (5) can be accurately maintained by this tape (3). A plurality of convex portions (7) are formed at predetermined intervals on the mother substrate (4) side of the tape (3) attached to the lead frame (2), and the leads (5) are attached to the mounting holes (6). When inserted, the convex part (7) adheres to the mother board (4), so that the HIC board (1) during solder dipping
Can be prevented, and the HIC substrate (1) can be kept at a predetermined height with respect to the mother substrate (4).

〔実施例〕 図面を参照して本発明の実施例を説明する。Embodiment An embodiment of the present invention will be described with reference to the drawings.

本発明は、先ず第1図及び第2図に示すように、H
(ハイブリツド)IC基板(1)の両側に取付けられたF
型リードフレーム(2)の側面にマザー基板側に凸部
(7)を備えた接着剤付き紙テープ(3)を貼付ける。
第2図は、リードフレーム(2)の紙テープ(3)を貼
付けてタイバーカツトする前の状態を示す。貼付ける面
は、リードフレーム(2)の内側、外側のいずれの面で
も良い。この紙テープ(3)をリードフレーム(2)に
貼付けることによつてHIC基板(1)をマザー基板
(4)に対して所定の高さに保持しておくことができ、
その高さの調整は紙テープ(3)の貼付け位置又はテー
プ(3)の幅を変えることにより行う。そして、このよ
うにマザー基板側に凸部(7)を備えた接着剤付き紙テ
ープ(3)がリードフレーム(2)の側面に貼付けられ
た状態で各リード(5)の端部をマザー基板(4)の取
付用孔部(6)へ挿入するとともに、第3図に示すよう
に、接着剤付きの紙テープ(3)の凸部(7)をマザー
基板(4)の上面に沿って折り曲げて接着する。紙テー
プ(3)がリード(5)に貼付けられていることによ
り、実装前にリード(5)が広がつたり曲がつたりする
のを防止することができると共に、紙テープ(3)の下
側端部の位置にHIC基板(1)の高さを保つことができ
る。この後、紙テープ(3)がリードフレーム(2)お
よびマザー基板(4)に貼付けられた状態で半田付けを
行う。このとき紙テープ(3)の凸部(7)がマザー基
板(4)に貼り付けられていることから、半田付けによ
るリードすなわちHIC基板(1)の浮き上がりを防止で
きる。そして、この半田付け工程終了後に紙テープ
(3)を剥す。
First, as shown in FIG. 1 and FIG.
F mounted on both sides of (hybrid) IC substrate (1)
An adhesive-attached paper tape (3) having a convex portion (7) on the mother substrate side is attached to the side surface of the mold lead frame (2).
FIG. 2 shows a state before the paper tape (3) of the lead frame (2) is attached and the tie bar is cut. The surface to be attached may be either the inside or the outside of the lead frame (2). By attaching this paper tape (3) to the lead frame (2), the HIC substrate (1) can be held at a predetermined height with respect to the mother substrate (4),
The height is adjusted by changing the attachment position of the paper tape (3) or the width of the tape (3). Then, with the adhesive-attached paper tape (3) having the protrusions (7) on the mother substrate side attached to the side surface of the lead frame (2), the end portions of the leads (5) are attached to the mother substrate ( 4) is inserted into the mounting hole (6) and the convex portion (7) of the adhesive-attached paper tape (3) is bent along the upper surface of the mother substrate (4) as shown in FIG. To glue. By attaching the paper tape (3) to the leads (5), it is possible to prevent the leads (5) from expanding or bending before mounting, and at the same time, to the lower side of the paper tape (3). The height of the HIC board (1) can be maintained at the end position. Then, soldering is performed with the paper tape (3) attached to the lead frame (2) and the mother substrate (4). At this time, since the convex portion (7) of the paper tape (3) is attached to the mother substrate (4), it is possible to prevent the leads, that is, the HIC substrate (1) from being lifted up by soldering. Then, after the soldering process is completed, the paper tape (3) is peeled off.

また、第4図に示すように、リード(5)がHIC基板
(1)の内側に位置するように折曲げたリードフレーム
(2)を使用する場合、接着剤付きの紙テープ(3)も
外側に幅をとらないようにリードフレーム(2)の内側
に貼付けるようにする。
Also, as shown in FIG. 4, when using a lead frame (2) bent so that the leads (5) are located inside the HIC substrate (1), the paper tape (3) with adhesive is also outside. Be sure to attach it to the inside of the lead frame (2) so that it does not have a width.

次に第5図に示す実施例の場合、紙テープ(3)を貼
付けた後のリードフレーム(2)のタイバーカツトを斜
めに行つて、各リード(5)の取付用孔部(6)への挿
入を容易にすることができるようにしたものである。
Next, in the case of the embodiment shown in FIG. 5, the tie bar cut of the lead frame (2) after the paper tape (3) is attached is diagonally moved to the mounting hole (6) of each lead (5). It is designed to facilitate the insertion.

〔発明の効果〕〔The invention's effect〕

本発明によれば、ハイブリツドIC基板に取付けられた
リードフレームの側面にマザー基板側に凸部を備えた接
着剤又は粘着剤付きのテープを貼付けた後、マザー基板
への実装を行い、このとき凸部(7)をマザー基板
(4)に接着させたので、半田付けに際しての浮き上が
りを防止することができる。このように本発明によれ
ば、リード間の間隔を正確に保つことができてマザー基
板の取付用孔部への挿入が容易になる。また、半田デイ
ツプ時においてもリードが必要以上に取付用孔部に沈み
込むのを防ぐことができ、ハイブリツドIC基板とマザー
基板との所定間隔を保つことが可能になる。
According to the present invention, an adhesive or a tape with an adhesive having a convex portion on the mother board side is attached to the side surface of the lead frame attached to the hybrid IC board and then mounted on the mother board. Since the convex portion (7) is adhered to the mother substrate (4), it is possible to prevent floating during soldering. As described above, according to the present invention, the interval between the leads can be accurately maintained, and the insertion into the mounting hole of the mother substrate becomes easy. Further, it is possible to prevent the leads from sinking more than necessary into the mounting holes even at the time of soldering, and it is possible to maintain a predetermined distance between the hybrid IC substrate and the mother substrate.

【図面の簡単な説明】[Brief description of drawings]

第1図は実施例の斜視図、第2図は実施例の正面図、第
3図は実施例の側面図、第4図は他の実施例の斜視図、
第5図は他の実施例の正面図、第6図は従来例の斜視図
である。 (1)はHIC基板、(2)はリードフレーム、(3)は
紙テープ、(4)はマザー基板、(5)はリード、
(6)は取付用孔部である。
1 is a perspective view of the embodiment, FIG. 2 is a front view of the embodiment, FIG. 3 is a side view of the embodiment, and FIG. 4 is a perspective view of another embodiment.
FIG. 5 is a front view of another embodiment, and FIG. 6 is a perspective view of a conventional example. (1) is HIC board, (2) is lead frame, (3) is paper tape, (4) is mother board, (5) is lead,
(6) is a mounting hole.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】リードフレーム付きハイブリッドIC基板を
マザー基板に取付ける混成集積回路の実装方法におい
て、 上記マザー基板側に凸部を備えた接着剤または粘着剤付
きテープをリードフレームの側面に貼付ける工程と、 リード端部をマザー基板の取付用孔部へ挿入するととも
に、接着剤又は粘着剤付きテープの凸部とマザー基板と
を接着し、半田付けする工程と、 接着剤又は粘着剤付きテープをリードフレーム及びマザ
ー基板から剥がす工程とを有することを特徴とする混成
集積回路の実装方法。
1. A hybrid integrated circuit mounting method for mounting a hybrid IC substrate with a lead frame on a mother substrate, wherein a step of attaching an adhesive or adhesive tape having a protrusion on the mother substrate side to a side surface of the lead frame. Insert the lead end into the mounting hole of the mother board, bond the convex part of the adhesive or adhesive tape to the mother board, and solder the solder and the adhesive or adhesive tape. And a step of peeling the lead frame and the mother substrate from each other.
JP62016695A 1987-01-27 1987-01-27 Hybrid integrated circuit mounting method Expired - Fee Related JP2513203B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62016695A JP2513203B2 (en) 1987-01-27 1987-01-27 Hybrid integrated circuit mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62016695A JP2513203B2 (en) 1987-01-27 1987-01-27 Hybrid integrated circuit mounting method

Publications (2)

Publication Number Publication Date
JPS63184392A JPS63184392A (en) 1988-07-29
JP2513203B2 true JP2513203B2 (en) 1996-07-03

Family

ID=11923429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62016695A Expired - Fee Related JP2513203B2 (en) 1987-01-27 1987-01-27 Hybrid integrated circuit mounting method

Country Status (1)

Country Link
JP (1) JP2513203B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61174753U (en) * 1985-04-19 1986-10-30

Also Published As

Publication number Publication date
JPS63184392A (en) 1988-07-29

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