JP2512874B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a solid-state imaging device of a photoelectric charge gate storage type using an electrostatic induction transistor (hereinafter referred to as “SIT”), and in particular, the device. The present invention relates to improvements in signal detection methods such as signal detection and precharge / reset.

[Prior Art] Conventionally, an electrostatic induction transistor (hereinafter referred to as "SIT")
Various methods have been already known as a signal reading method for a solid-state imaging device using the above, particularly a signal detecting method and a precharge / reset method.

For example, JP-A-60-100886 and JP-A-60-199277.
The publication discloses a signal reading method of a solid-state imaging device in which SITs are arranged in a matrix.

Further, Japanese Laid-Open Patent Publication No. 60-219876 discloses a signal read method using a source follower.

Among these, JP-A-60-199277 and JP-A-60-
Each of those disclosed in Japanese Patent No. 219876 will be described below.

Conventional Example 1 First, the one disclosed in JP-A-60-199277 is
This will be described with reference to FIG.

In the figure, a cell that performs an optical signal of one pixel (hereinafter referred to as "SI
Q _ij (referred to as “T cell”) (i = 1 to m, j to n) is configured by the SIT 10 and the gate capacitor 12, respectively. SIT
Drain of the cell Q _ij is respectively connected to the column line LH _aj, this column line LH _aj is the signal read line.

The column line LH _aj has, on the one hand, a transfer transistor Q
_aj , a storage capacitor C connected between its output and ground
_aj, it is commonly connected to the video line LV through each column select transistors Q _bj. A voltage Va _DD as a video power supply is applied to the video line LV via a load resistance _RL .

Here, a circuit including the transfer transistor Q _aj , the storage capacitor C _aj, and the column selection transistor Q _{bj is referred} to as a read selection circuit 14.

On the other hand, the column line LH _aj is connected to the pre-charge transistor Q _cj , and the pre-charge voltage V _aP is applied thereto.

The gate of the column selection transistor Q _bj described above is
Each is connected to the horizontal scanning circuit 16.

Next, the source of the SIT cell Q _ij is respectively connected to the first row line LV _ai, these row lines LV _ai, is grounded via respective row select transistors Q _di.

The gate capacitor 12 of the SIT cell Q _{ij and} the gate of the row selection transistor Q _di are connected to the second row line LV _bi, and each row line LV _bi is connected to the vertical scanning circuit 18. .

Parasitic capacitance C _bj exists in each of the above-mentioned column lines LH _aj . That is, the storage capacitance C _aj and the parasitic capacitance C _bj are connected in parallel to the column line LH _aj .

Next, the signal reading operation in the above conventional example will be described with reference to the time chart showing the signal waveforms of the respective parts in FIG.

First, as shown in FIG.
_{When the} drive signal φ _a is applied to the gate of _aj at time t _a1 , each transfer transistor Q _aj becomes conductive.

Then, at time t _a2 to time in this state, when the gate driving signal phi _c of the precharge transistor Q _cj are respectively applied, the precharge transistor Q _cj becomes conductive, and the storage capacitor C _aj column line LH _aj Both the parasitic capacitance C _bj will be precharged up to the voltage V _aP (see FIG. _7E ).

Next, at time t _a3 , the drive signal φ _c described above is turned off (see FIG. 7B). Thereafter, at time t _a4 , the row selection pulse φ _gi , for example, φ _g1 is output from the vertical scanning circuit 18 to the second
Is applied to the row line LV _b1, so that the read pulse is applied to the gate capacitor 12 of the SIT cell Q _1j which are respectively connected to the row line LV _b1.

At the same time, the first row line LV _a1 is connected to the row selection transistor Q.
_d1 is grounded by being conducted by φ _g1 , and SIT
Only the cells Q _{11 to} Q _1n in the first row of the cell Q _ij will be conductive.

On the other hand, photoelectrically accumulated charges ΔQ _g are accumulated in each accumulation gate of the SIT cell Q _ij according to the amount of incident light.

Therefore, the gate voltage ΔV _g of the SIT cell Q _ij changes by ΔV _g = ΔQ _g / C. Where C is the total gate capacitance,
It includes a capacitor capacitance C _g and a storage gate junction capacitance C _J.

When the gate selection pulse φ _g1 is applied to the change ΔV _{g of the} gate voltage, the SIT cell Q _ij is turned on and the gate voltage Δg is changed.
Drain current I _D is amplified by the I _D -I _G characteristics of SIT10 flows according V _g, so that the discharge of the parasitic capacitance C _bj and the storage capacitor C _aj column line LH _aj which are pre-charged is done.

As a result, the voltage V _caj of the storage capacitor C _{aj changes} from a precharge voltage V _aP to a, b, c depending on the amount of incident light on each cell, as shown in FIG.
In the figure, a indicates the case of dark output, and b and c indicate the case where the amount of incident light increases in that order.

Next, since φ _gi becomes low level at the timing of time t _a5 (see FIG. 7C), the SIT cell Q _ij is turned off,
The current path is cut off.

At the same time, the drive signal φ _a also becomes low level (see FIG. 9A), the transfer transistor Q _aj also turns off, and
The storage capacitor C _aj will be separated from the signal reading column line LH _aj .

Further, at time t _a6 , φ _bj is applied from the horizontal scanning circuit 16 to the gate of the column selection transistor Q _bj (see FIG. 7D). As a result, the column selection transistor Q _bj becomes conductive, and the storage capacitor C _aj is charged by the video voltage V _aDD . The charging current at this time is converted to a voltage by the load resistance R _L , and as shown in FIG.
It will be output to the outside as _out .

The signal read method using the read selection circuit 14 as described above will be referred to as a read method using a storage capacitor.

Conventional Example 2 Next, the one disclosed in JP-A-60-219876 is
Description will be made with reference to FIG.

In the figure, the source of the SIT cell Q _ij is the column line LH _bj
, And these column lines LH _bj are signal read lines. In addition, the column line LH _bj has a parasitic capacitance C _dj.
Exist respectively.

The column line LH _bj is, on the one hand, a column select transistor
Commonly connected to the video line LV via Q _ej . The video line LV is grounded via the load resistance R _L. On the other hand, the column line LH _bj is grounded via the reset transistor Q _fb .

The base of the column selection transistor Q _ej described above is
Each of them is connected to the horizontal scanning circuit 20 and is referred to as a read selection circuit 22.

Next, the drain of the SIT cell Q _ij is common to all cells, and the power supply voltage V _bDD is applied.

On the other hand, the row lines LV _ci to which the gates of the SIT cells Q _ij are connected are connected to the vertical scanning circuits 24, respectively.

Next, the signal reading operation in the above conventional example will be described with reference to the time chart of FIG.

First, at time t _b1 as shown in FIG.
The gate selection pulse φ _gi is a row line LV _ci , for example, a row line.
When applied to LV _c1 , the SIT cells Q _{11 to} Q _1n become conductive.

Further, as shown in FIG. 6F, the column line LH _bj is reset by the rise of the drive signal φ _f .

At this time, photoelectrically accumulated charge ΔQ _g is accumulated in the accumulation gate of the SIT cell Q _ij according to the amount of incident light,
The gate voltage ΔV _g of the SIT cell Q _ij is ΔV _g =
Only ΔQ _g / C has changed.

When the gate selection pulse φ _gi is applied to the change ΔV _{g of the} gate voltage, all the SIT cells Q _{11 to} Q _1n become conductive.

Therefore, according to the gate voltage change ΔV _g , I _D −V of SIT10
_The drain current I _D amplified by the _G characteristic flows. Therefore, the voltage V _LHbj of the column line LH _bj changes like a, b, c according to the light quantity, as shown in FIG. In the figure, a indicates a dark state, and b and c indicate a case where the amount of incident light increases in that order.

Next, when the column selection transistor Q _e1 is applied by being applied from the time t _b2 drive signal φ _b1 horizontal scanning circuit 20, the source current I _S of the SIT cell Q ₁₁ flows to the load resistance R _L via the video line LV. At the same time, the discharge current from the parasitic capacitance C _d1 also flows.

Therefore, the signal output V _out has a downward-sloping waveform as shown in FIG.

Next, at time t _b3 , the above-mentioned signals are read from the SIT cell Q ₁₂ (see FIG. 7C). Similarly, at time t _b4 , the signal is read from the SIT cell Q _1j (see (D) in the same figure).

Further, from time t _b5 , the above operation is repeated.

The SIT as described above is used as a source follower and a signal is read by a column selection transistor, which is called a source follower / column selection transistor system.

[Problems to be Solved by the Invention] Although it is possible to read signals for some time even with the signal reading method described above, there are the following disadvantages.

First, in Conventional Example 1, by selectively conducting only the SIT cells selected by the first and second row lines, the discharge of the corresponding storage capacitance due to the conduction of the non-selected SIT cells is prevented,
The purpose is to use SIT having a high optical amplification factor as a photoelectric conversion element of each cell and suppress crosstalk between the cells.

However, when the precharge transistor Q _cj is turned off at the timing of t _a3 in FIG. 11 (see FIG. 11B), the parasitic capacitance C _ci existing in the first row line LV _ai is not precharged. _Therefore , the storage capacitance voltage V _Caj is reduced (see (E) in the same figure).

That is, the accumulated charge accumulated in the storage capacitor C _aj
Discharge through the cell Q _ij and the parasitic capacitance C _ci , and the storage capacitance voltage V _Caj becomes lower than the precharge voltage V _aP . This was confirmed by monitoring the voltage V _LVai on the first row line LV _ai (see (F) in the figure).

As a result, the discharge of the accumulated charges due to such parasitic capacitance reduces the advantage of configuring the image pickup device by the SIT having a high optical amplification factor of about 10 ⁵ to 10 ⁸ .

Further, the discharge output through the non-selected cells appears in the signal output V _out in the dark state, and this is output as a false signal. Therefore, there is an inconvenience that crosstalk between cells becomes large.

Next, in Conventional Example 2, the power supply voltage V _aDD is commonly applied to the drains of the SIT cells Q _ij .

For this reason, if a cell configuration having a high optical amplification factor is used, a false signal will be mixed by the non-selected cells, and the dark output will increase.

Therefore, there is no choice but to use a normal-off type SIT cell configuration having a relatively low optical amplification factor (10 ² to 10 ³ ), and there is a disadvantage that the high photosensitivity characteristic of the SIT cannot be fully utilized.

The present invention has been made in view of the problems of the conventional technology as described above, and makes it possible to sufficiently detect the signal with a high optical amplification factor by fully utilizing the characteristics of SIT, and to improve the crosstalk between cells. It is an object of the present invention to provide a solid-state imaging device capable of suppressing and further reducing the dark output.

[Means for Solving Problems] In the present invention, a plurality of SIT cells corresponding to pixels are sequentially selected by a selection switch means and connected to a signal reading means, and a signal of light incident on the selected SIT cell is detected. The read-out solid-state imaging device is characterized by including a potential adjusting means for setting the same potential between the first main electrode and the second main electrode of the non-selected SIT cell.

According to one aspect of the invention, the SIT cells are arranged in a two-dimensional matrix; the first main electrode of each SIT cell is connected to any of a plurality of column lines,
The second main electrode is connected to any one of the plurality of first row lines; the potential adjusting means precharges the column line and the first row line to the same voltage. Have means.

According to another aspect of the present invention, the potential adjusting means is
It has reset means for resetting the column line and the first row line to the grounded state.

[Operation] In the present invention, the cell first and second main electrodes other than the SIT cell from which the signal is read are adjusted to the same potential by the potential adjusting means.

According to one aspect, the lines to which the first and second main electrodes of each cell are connected are each precharged to the same voltage. According to another aspect, the line to which the first and second main electrodes are connected is reset to ground.

As a result, the potentials between the first and second main electrodes of the non-selected cell become equal, the leak current does not flow, and the false signal at the dark output by the non-selected cell is reduced.

Embodiments Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals will be used for the same or corresponding parts as in the above-mentioned conventional technique.

Basic Configuration and Operation First, a basic configuration example of the present invention and its operation will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a basic cell configuration example of the present invention. In the figure, the drain of the SIT cell QA is connected to the column line LHA, and this column line LHA serves as a signal read line. The column line LHA is connected to the video line LV via the read selection circuit 30, and the signal output V _out is obtained from this.

The read selection circuit 30 has, for example, a storage capacitance type configuration including a transfer gate, a storage capacitance, and a column selection gate as shown in FIG.

This column line LHA has a precharge transistor QB
The precharge voltage V _P is applied via the.

The source of the SIT cell QA is connected to the first row line LVA, and the precharge voltage V _P is applied to the row line LVA via the precharge transistor QC.

The first row line LVA is also grounded via the row select transistor QD.

Next, the gate of the SIT cell QA and the gate of the row selection transistor QD are respectively connected to the second row line LVB, and this row line LVB is connected to a vertical scanning circuit (not shown). .

The above-mentioned column line LHA and row line LVA have parasitic capacitances CA and CB, respectively, and the video line LB has a load resistance R.
_The voltage V _DD is applied via _L.

Next, the operation of the above device will be described with reference to the time chart of FIG.

First, at time t _A1 in the figure, when the read selection circuit 30 drive signal φA is applied as shown in FIG.
As described in FIG. 10, the transfer transistor becomes conductive.

Next, at time t _A2 , when the drive signal φB is applied as shown in FIG. 2 (B), the precharge transistors QB and QC are respectively rendered conductive, and the parasitic capacitance CA of the column line LHA and the read selection circuit. The storage capacitance included in 30 is precharged to the voltage V _P. At the same time, the parasitic capacitance CB of the first row line LHA is also precharged to V _P.

By precharging the parasitic capacitance as described above, there is no potential difference between the drain and source of the SIT cell QA.

In FIGS. 6E and 6F, the voltages VA and VB of the storage capacitance (or parasitic capacitance CA) and the parasitic capacitance CB of the read selection circuit 30 are shown. At time t _A2, the VA = VB = V _P.

Next, even if the drive signal φB is turned off at time t _A3 , the voltage VA of the storage capacitor and the voltage VB of the row line LVA are both precharged to the same potential. Therefore, the voltage of the storage capacitor
VA does not change, and therefore no discharge occurs from the storage capacitor of the read selection circuit 30.

Next, at time t _A4 , when the drive signal φC is applied as shown in FIG. 7C, the SIT cell QA and the row selection transistor QD are rendered conductive. Because of this, line lines
The LVA will be grounded immediately.

Therefore, the drain current amplified by the I _D -V _D characteristic of the SIT flows according to the amount of charge ΔQ accumulated in the gate of the SIT cell QA according to the light amount, and the read selection circuit 30
The voltage VA of the storage capacitor of is reduced (see (E) in the figure).

This change in voltage VA changes with time as described in FIG.
Drive signal φD in read selection circuit 30 at t _A6
Is applied (see FIG. 2 (D)), and the detection signal output V _out shown in FIG. 2 (G) is obtained.

In FIGS. 7E and 7G, a is for dark output, and b and c are for increasing incident light quantity in that order.

As described above, the output V _{out in the} dark state indicated by a is the time
Since the storage capacitance voltage VA does not decrease from the precharge voltage V _P during the time from t _A3 to t _A4, it can be suppressed to a sufficiently small value.

Next, another basic configuration example will be described with reference to FIG. In this example, the source and drain of the SIT cell QA in FIG. 1 are interchanged. In the following description, the components corresponding to those in FIG. 1 will be denoted by the symbol " _R ".

In FIG. 3, the source of the SIT cell QA _R is the column line LH.
This column line LHA _R is connected to A _R and serves as a signal read line. The column line LHA _R has a read selection circuit 30.
_It is connected via _R to the video line LHA _R from which the signal output V _outR is obtained.

The read selection circuit 30 _R has, for example, a storage capacitance type configuration including a transfer gate, a storage capacitance, and a column selection gate as shown in FIG.

This column line LHA _R , on the other hand, is connected to the transistor QB
_Grounded via _R.

Next, the drain of the SIT cell QA _R is connected to the first row line LVA _R.
Is connected to, this row line LVA _R, the transistor QD _R
The voltage V _PR is applied via the.

The first row line LVA _R is further grounded through the transistor QC _R.

Then, the gates of the transistors QB _R of SIT cell QA _R, are respectively connected to the second row line LVB _R, the row line LVB _R, connected to a vertical scanning circuit (not shown) There is.

Column line LHA _R described above, the row line LVA _R are each present a parasitic capacitance CA _R, CB _R are each, the video line LV _R, the load resistance R _LR is connected.

As described above, in this example, the method of applying the related voltage is changed. That is, the ground potential and the power supply voltage V _DD are exchanged, the precharge voltage V _P becomes the ground potential reset voltage, and the precharge transistor QB, QC
Are reset transistors QB _R and Q _{C R} , respectively.

The read selection circuit 30 _R may be configured by a transfer transistor, a storage capacitor, and a column selection transistor, or may be configured by a column selection transistor.

Further, the SIT cell QA _R is composed of SIT having a high optical amplification factor, like the SIT cell QA in FIG.

Even with the configuration in which the source and drain of the SIT are interchanged as described above, it is possible to reduce the false signal and dark output due to the leak current of the non-selected cells by the same operation as in FIG.

Further, such an effect can be obtained even in the case of a read method using a read transistor 30 _R with a transfer transistor, a storage capacitor, and a storage capacitor using a column selection transistor.
The same can be achieved in the case of the read method using the source follower / column selection transistor configured by the column selection transistor.

First Embodiment Next, the first embodiment of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 shows the configuration of the first embodiment.
The cells in the figure are arranged in a matrix.

In the figure, SIT cell Q that detects the signal of one pixel
_ij (i = 1 to m, j = 1 to n) is composed of a SIT 10 and a gate capacitor 12, respectively. The drain of the SIT cell Q _ij is respectively connected to the column line LH _aj, this column line LH _aj is the signal read line.

The column line LH _aj has, on the one hand, a transfer transistor Q
_aj , storage capacitance C _aj , connected between its output and ground
The column selection transistors Q _bj are commonly connected to the video line LV. A voltage Va _DD as a video power supply is applied to the video line LV via a load resistance _RL .

The transfer selection transistor Q _aj , the storage capacitance C _aj, and the column selection transistor Q _{bj form} a read selection circuit.

On the other hand, the column line LH _aj is connected to the pre-charge transistor Q _cj , and the pre-charge voltage V _aP is applied thereto.

The base of the column selection transistor Q _bj described above is
Each is connected to the horizontal scanning circuit 100.

Next, the source of the SIT cell Q _ij is respectively connected to the first row line LV _ai, these row lines LV _ai, is grounded via respective row select transistors Q _di.

Further, the gate capacitor 12 of the SIT cell Q _{ij and} the gate of the row selection transistor Q _di are each connected to the second row line LV _bi, and each row line LV _bi is connected to the vertical scanning circuit 102. .

Parasitic capacitance C _bj exists in each of the above-mentioned column lines LH _aj . That is, the storage capacitance C _aj and the parasitic capacitance C _bj are connected in parallel to the column line LH _aj .

 The above configuration is similar to that shown in FIG.

Next, the characteristic part of this embodiment will be described. The above-mentioned first row lines LV _ai are connected to the precharge transistors TA _i , respectively, and the precharge voltage V _aP is applied thereto respectively. It is like this.

The drive signal φ _c applied to the gate of the precharge transistor Q _cj described above is applied to the gates of these precharge transistors TA _i .

Next, the signal reading operation in the above embodiment will be described with reference to the time chart showing the signal waveform of each part in FIG. The time chart of the figure is
It is similar to that shown in FIG.

First, as shown in FIG.
_{When the} drive signal φ _a is applied to the gate of _aj at time t _A1 , each transfer transistor Q _aj becomes conductive.

Then, at time t _A2 In this state, the precharge transistors Q _cj, the gate driving signal phi _c of the TA _i is respectively applied, the precharge transistors Q _cj, TA _i become respectively conductive, column lines LH _aj storage capacitance C _aj and parasitic capacitance C
_bj and the parasitic capacitance C _ci existing in the first row line LV _ai
And are both precharged to the voltage V _aP (see (E) and (F) in the same figure).

Next, at time t _A3 , the drive signal φ _c described above is turned off (see FIG. 7B). After that, at time t _A4 , a row selection pulse φ _gi , for example, φ _g1 is applied from the vertical scanning circuit 102 to the second row line LV _b1, and the gate capacitors of the SIT cells Q _1j connected to the row line LV _b1 respectively. A read pulse will be applied to 12.

At the same time, the first row line LV _a1 is connected to the row selection transistor Q.
_d1 is grounded by being conducted by φ _g1 , and SIT
Only the cells Q _{11 to} Q _1n in the first row of the cell Q _ij will be conductive.

On the other hand, photoelectrically accumulated charges ΔQ _g are accumulated in each accumulation gate of the SIT cell Q _ij according to the amount of incident light.

Therefore, the gate voltage ΔV _g of the SIT cell Q _ij changes by ΔV _g = ΔQ _g / C. Where C is the total gate capacitance,
It includes a capacitor capacitance C _g and a storage gate junction capacitance C _J.

When the gate selection pulse φ _gi is applied to the change ΔV _{g of the} gate voltage, the SIT cell Q _ij is turned on and the gate voltage Δ _gi is changed.
Drain current I _D is amplified by the I _D -I _G characteristics of SIT10 flows according V _g, so that the discharge of the parasitic capacitance C _bj and the storage capacitor C _aj column line LH _aj which are pre-charged is done.

As a result, the voltage V _caj of the storage capacitor C _{aj changes} from a precharge voltage V _aP to a, b, c depending on the amount of incident light on each cell, as shown in FIG.
In the figure, a indicates the case of dark output, and b and c indicate the case where the amount of incident light increases in that order.

Next, since φ _gi becomes low level at the timing of time t _A5 (see FIG. 7C), the SIT cell Q _ij is turned off,
The current path is cut off.

At the same time, the drive signal φ _a also becomes low level (see FIG. 9A), the transfer transistor Q _aj also turns off, and
The storage capacitor C _aj will be separated from the signal reading column line LH _aj .

Further, at time t _A6 , φ _bj is applied from the horizontal scanning circuit 100 to the gate of the column selection transistor Q _bj (see FIG. 7D). As a result, the column selection transistor Q _bj becomes conductive, and the storage capacitor C _aj is charged by the video voltage V _aDD . The charging current at this time is converted to a voltage by the load resistance R _L , and as shown in FIG.
It will be output to the outside as _out .

As described above, in this embodiment, signal reading is performed by the same operation as that shown in FIG.

Second Embodiment Next, a second embodiment of the present invention will be described. This second embodiment is similar to that shown in FIG.
In the first embodiment of the figure, the drain and the source of the SIT are exchanged.

In FIG. 6, the same symbols as those of the corresponding components in the first embodiment are designated by the symbol " _R " to indicate the respective components.

FIG. 7 shows signal waveforms during operation. Fifth
It is almost the same as that of the first embodiment shown in the figure, except that
The voltage waveforms of the precharge and reset of the storage capacitors shown in FIGS. 7E and 7F are reversed, and the output waveform of FIG. 9G is also reversed accordingly and the positive voltage direction is changed. Become.

In the second embodiment, by the reset transistor T _iR workings of the first row line LV _AIR, FIG (E), as shown respectively in (F), the storage capacitor at time t _A2, the parasitic capacitance of all Since it is reset, there is no leak current due to non-selected cells. Therefore, discharge from the storage capacitor is suppressed, and dark output is sufficiently suppressed.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 shows the configuration of the third embodiment, and FIG. 9 shows a time chart of its operation.

Since the third embodiment has a modified configuration of the above-described second embodiment, the same reference numerals will be used for components common to or corresponding to those of the second embodiment.

In this embodiment, as shown in FIG.
In the embodiment, C _ajR ) and the transfer transistor (in the second embodiment,
This is different from the second embodiment in that there is no Q _ajR ), and signal reading is performed by a reading method using a source follower / column selection transistor.

Next, the operation of the third embodiment will be described with reference to FIG.

First, at time t _B1 , when the drive signal φ _giR is applied from the vertical scanning circuit 102 _R to the second row line LV _biR (see FIG. 7A), the corresponding i row, for example, the first row is selected. To be done.

That is, the drain of the SIT cell Q _11R to Q _1NR, together with the power supply voltage V _addr via a row select transistor Q _d1R is respectively applied, to the gate driving signal phi _G1R is that each applied.

Therefore, only the SIT cells Q _{11R to} Q _1nR in the first row are conductive, but the SIT cells connected to the other rows are not conductive.

Further, due to the fall of the drive signal φ _{CR at} the time t _B1 (see (F) in the figure), the reset transistor
Q _cjR and T _iR are _{turned off} , and the column line LH _ajR and the first row line LHV _ajR are reset.

Therefore, the voltage of the source and drain of the unselected SIT cell,
That parasitic capacitance C _BJR, the voltage of C ciR V _{CbjR, CciR} becomes the same potential, no leakage current flows.

On the other hand, the SIT cell Q _11R to Q _1NR were passed, the amplification of the drain current is made to correspond to the amount of charge stored in the gate by the incident light, the potential V _CbjR column line LH _AJR is the in accordance with the light amount It increases as shown in FIG.

Then, at time t _B21 , as shown in FIG. 7B, when the drive signal φ _b1R is input from the horizontal scanning circuit 100 _R to the column selection transistor Q _b1R , the column selection transistor Q _b1R
Conducts.

Thus, through the video line LV _R, SIT to the load resistor R _LR
The source current I _S of the cell Q _11R will flow during the conduction period. At this time, the discharge current from the parasitic capacitance C _b1R also flows, and the signal output V _outR becomes as shown in FIG.

The above signal read operation is _performed for the SIT cells Q _{12R to} Q _{1nR at} times t _{B22 to} t _B2n (see (C), (D) and (G) in the same figure).

The dark output component of the output signal V _outR is satisfactorily reduced because the leak current of the non-selected cells is suppressed.
Therefore, even when the SIT having a high optical amplification factor is arranged, the false signal output is suppressed and the crosstalk between the cells can be reduced.

Effects of the Embodiments According to the above embodiments, the row selection switch means and the column selection switch means enable the SIT for reading a specific signal.
Only cells are selected.

Then, the line to which the drain and the source of the SIT cell are connected is precharged or reset by the precharge transistor or the reset transistor.

As a result, the drain-source potentials of the non-selected cells become equal, the leak current stops flowing, and the false signal at the dark output by the non-selected cells can be sufficiently suppressed.

Therefore, it is possible to realize a solid-state image pickup device having a high optical amplification factor and sufficiently suppressing crosstalk between cells by arranging the cells with a matrix of SITs with a high optical amplification factor SIT. You can

Further, since the output in the dark state is small, there is an effect that a large dynamic range of photoelectric conversion characteristics can be secured.

Further, not only the storage capacity method using the transfer gate / storage capacity / column selection transistor, but also the read method using the source follower / column selection switch, which cannot be applied to the high light width increasing rate SIT cell, is as shown in the third embodiment. Applicable, high optical amplification factor SI with sufficiently suppressed crosstalk
A T-cell solid-state imaging device can be realized.

In other words, the fact that a cell configuration with such a high optical amplification factor can be achieved means that the cell density can be improved by using a cell with the same optical amplification factor as the conventional one.

Even when SIT cells with a relatively low light amplification factor are arranged in a matrix, false signals due to non-selected cells that are illuminated by more than the saturated light intensity are suppressed, so solid-state imaging with less crosstalk between cells. The device can be realized.

Other Embodiments Note that the present invention is not limited to the above-described embodiments at all, and, for example, in the above-described embodiments, for row / column selection,
Although the transistors for precharging and resetting are constituted by MOS transistors, the present invention is not limited to this, and they may be constituted by, for example, normally-off type SITs.

Further, the SIT configuring each cell is not limited to the vertical type, but a horizontal type, for example, MOSSIT or junction type SIT may be used.

Further, although the above embodiments are examples of the two-dimensional image pickup device, the present invention is also applied to the one-dimensional image pickup device.

[Effects of the Invention] As described above, according to the present invention, the characteristics of SIT can be fully utilized to enable signal detection with a high optical amplification factor, and crosstalk between cells can be favorably suppressed. Further, there is an effect that the dark output can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first basic configuration example of the present invention, FIG. 2 is a time chart showing the operation of the apparatus of FIG. 1, and FIG. 3 is a second basic configuration of the present invention. FIG. 4 is a circuit diagram showing the structure of the first embodiment, FIG. 5 is a time chart showing the operation of the first embodiment, and FIG. 6 is a circuit diagram showing the structure of the second embodiment. FIG. 7 is a time chart showing the operation of the second embodiment, FIG. 8 is a circuit diagram showing the configuration of the third embodiment, FIG. 9 is a time chart showing the operation of the third embodiment, and FIG. FIG. 11 is a circuit diagram showing a first conventional example, FIG. 11 is a time chart showing the operation of the first conventional example, and FIG.
FIG. 13 is a circuit diagram showing a conventional example of the above, and FIG. 13 is a time chart showing the operation of the second conventional example. [Explanation of symbols of main parts] 10 …… SIT, CA, CB …… parasitic capacitance, LHA …… column line, LNA
…… First row line, LVB …… Second row line, QA …… S
IT cell, QB, QC ... Precharge transistor, QB _R , QC _R
...... Reset transistor.

Claims (4)

(57) [Claims] 1. A fixed image pickup device for sequentially selecting a plurality of pixel-corresponding SIT cells by a selection switch means and connecting them to a signal reading means to read a light signal incident on a selected SIT cell. A solid-state imaging device, comprising: a potential adjusting unit that sets the first main electrode and the second main electrode of the SIT cell to the same potential. 2. The SIT cells are arranged in a two-dimensional matrix, and the first main electrode of each SIT cell is connected to any one of a plurality of column lines, and the second main electrode. The solid-state imaging device according to claim 1, wherein is connected to any one of the plurality of first row lines. 3. The potential adjusting means includes the column line and the first line.
3. The solid-state image pickup device according to claim 2, further comprising precharge means for precharging the row line of FIG. 4. The potential adjusting means includes the column line and the first line.
3. The solid-state imaging device according to claim 2, further comprising reset means for resetting the row line and the row line of FIG.