JP2507422B2 - Bitmap image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a bitmap image processing device having a hardware window function.

(Prior Art) In recent years, bitmap image processing devices, such as bitmap display devices, require a display function called multi-window display in order to display a plurality of information on one display screen. Conventionally, Nikkei Electronics, 1986.5 has been used as a means to realize window display.
19 (no.395 pp 221-250), (1) bi
Two methods are known, a software window based on the t blt method (bit block transfer method) and a hardware window based on (2) display address control. However, in the software method (1), as shown in the above-mentioned document, the transfer time becomes longer as the window size becomes larger, the responsiveness deteriorates, and the prioritization in the case of overlapping windows becomes complicated. There was a problem such as becoming.
On the other hand, in the hardware method of (2), i82786 (display control LS of Intel Corp.
In the case of I), when the number of windows increases, the process of updating memory contents such as descriptors becomes complicated when moving windows, changing display addresses, and changing priority, and memory access by i82786 This increases the number of times, leading to a decrease in performance on the processor side. Further, the i82786 has a problem that the hardware window function cannot be used when the image 2-port memory is used as the frame memory.

(Problems to be Solved by the Invention) As described above, the conventional bitmap display device cannot realize an efficient hardware window function using the 2-port memory.

The present invention has been made in view of the above circumstances, and an object thereof is to realize an efficient hardware window function by using a 2-port memory as a frame memory and to control display priority among a plurality of hardware windows. It is to provide a bitmap image processing device that can be easily performed.

[Configuration of the Invention] (Means for Solving Problems) According to the present invention, it is determined whether or not the display scan position, which is the current display target position, is within a plurality of arbitrarily set window display regions. Further, there are provided a window detecting means for detecting, a window display priority setting means for setting the display priority of the plurality of window display areas, and a frame memory for storing image data. This frame memory has p 2-port memories of 1 bit × m (column) × n (row). The two-dimensional memory space of the frame memory is managed by dividing each row by l · p bit units, and each 1-bit area obtained by equally dividing each divided area into
The 1 bit at each address location of the 2-port memory is allocated in a fixed order. According to the present invention, the background address indicating the memory coordinates in the frame memory where the background display data for the display scan position is stored and the frame memory memory coordinates where the window display data for the display scan position is stored. And a first multiplexer for selecting one of the window addresses shown for each window display area according to the detection result of the window detection means and the setting contents of the window display priority setting means, and the output from this first multiplexer. A second multiplexer for switching the generated address and the drawing address according to the detection result of the window detecting means, an address conversion circuit for converting the address output from the second multiplexer into an address for each of the two-port memories, and Change from address conversion circuit The data is serially output in l-bit units from each of the two-port memory by the addresses of each two-port memory to be output, the shift register circuit is provided to further convert the serial data.

(Operation) In the above-mentioned configuration, the address conversion circuit is configured such that each l-bit obtained by equally dividing continuous l · p-bit data from the bit position in the memory space of the frame memory indicated by the address output from the second multiplexer into p equal parts. The address of the 2-port memory to which is assigned is generated for each 2-port memory. Each 2-port memory is addressed by the address from the address conversion circuit, whereby the 1 × m bits of the designated row are serially output in 1-bit units sequentially from the bits of the designated column. The shift register circuit sequentially selects the data serially output from each 2-port memory in 1-bit units from the output data from the 2-port memory to which the address output from the second multiplexer is assigned, and converts the serial data into serial data. To do. This serial data is used for image output. That is, according to the above configuration, a hardware window using the 2-port memory becomes possible. Further, according to the above configuration, the switching of the plurality of window display areas can be performed by the first multiplexer according to the setting content of the priority setting means, so that the display priority of the window display area can be changed. It is possible only by changing the setting contents of the setting means.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings by taking a bitmap display device as an example.

FIG. 1 is a block configuration diagram showing an embodiment of an address control circuit provided in the bitmap display device, and FIG. 2 is a block configuration diagram of the bitmap display device. In the bitmap display device of FIG. 2, 11 is a CPU for controlling the entire device, and 12 is a system bus of the CPU 11. 13 is a drawing circuit for performing straight line generation and bit blt (bit block transfer), 14 is a drawing data bus 14a,
The control bus 14 for the drawing circuit 13 comprises a drawing address bus 14b and a control bus 14c. When the CPU 11 performs drawing processing such as generation of straight lines, the drawing circuit 13 and the drawing bus 14 can be omitted. Reference numeral 15 is a display timing circuit for generating vertical and horizontal synchronizing signals, blanking signals, etc. for the CRT monitor 22 described later, 16 is a display memory scan address generation, and switching of this address and the drawing address from the drawing address bus 14b, etc. Address control circuit for
Reference numeral 17 is a frame memory for storing figures and images. The frame memory 17 is addressed by the memory address output from the address control circuit 16. 18
Is a data control circuit (optional) that performs color conversion, arithmetic processing (raster operation), alignment, etc. when drawing in the frame memory 17, and 19 is a shift register that converts the display data output from the frame memory 17 into serial data Circuit. Reference numeral 20 is a look-up table (LUT) that receives the output data from the shift register circuit 19 and performs color conversion and luminance conversion. Reference numeral 21 is a digital / digital converter that converts the output data from the look-up table 20 into an analog signal.
An analog converter (DAC) 22 is a CRT monitor that displays the output signal from the converter 21 as a video signal on the screen.

Here, regarding the concept of the hardware window realized by the bitmap display device of FIG.
This will be described with reference to FIG. In this embodiment, the memory space of the frame memory 17 (frame memory space) FMS
Is 2048 × 1024 dots, and the displayable area (screen space) SS of the CRT monitor 22 is 1280 × 1024 dots. That is, the memory space FMS of the frame memory 17 is the CRT monitor 22.
It is set large enough for the screen space SS of. In this embodiment, an area of 1280 × 1024 dots starting from an arbitrary position (BMx, BMy) of the frame memory space FMS is displayed on the entire surface of the screen space SS. This is called background display. Further, in this embodiment, in an arbitrary rectangular area on the screen space SS, an arbitrary rectangular area on the frame memory space FMS having the same size as this area is displayed instead of the background display. This is called hardware window display.

Next, FIG. 4 (a) shows the memory configuration of the frame memory 17 that realizes the frame memory space FMS described above.
This will be described with reference to (b). The frame memory 17 is the fourth
Eight 2-port memories 17-0 to 17-17 as shown in FIG.
-7 is used. 2-port memory 17-0
17-7 is, for example, 4 bits such as NEC μ 41264 ×
It is a 2-port memory with a shift register of 256 (columns) x 256 (rows). Each row of the frame memory space FMS of the frame memory 17 realized by the two-port memories 17-0 to 17-7 is divided into 32 areas A0 to A63 and managed.

Bit 0 of area A0 in the 0th row of frame memory space FMS
4 bits of 0th row and 0th column in the two-dimensional memory space of the 2-port memory 17-0 are allocated to bit 3 to bits 4 to 7 of the area A0 of the 0th row of the frame memory space FMS. Is assigned 4 bits in the 0th row and 0th column of the 2-port memory 17-1. Similarly, 4 bits of 0th row and 0th column of the 2-port memory 17-7 are allocated to bits 28 to 31 of the area A0 of the 0th row of the frame memory space FMS.
In addition, 2-port memories 17-0 to 17-0 are provided in each 4-bit area (bit 0 to bit 3, bit 4 to bit 7, ... Bit 28 to bit 31) of the area A1 of the 0th row of the frame memory space FMS.
4 bits of the 0th row and the 1st column of 17-7 are allocated. Similarly, 4 bits of the 0th row and 63rd column of the 2-port memories 17-0 to 17-7 are allocated to the 4-bit areas of the final area A63 of the 0th row of the frame memory space FMS, respectively. 2 in each 4-bit area of the first area A0 of the first row of FMS
4 bits of the 0th row and 64th column of the port memories 17-0 to 17-7 are allocated. In addition, the second of the frame memory space FMS
2-port memory in each 4-bit area of the row head area A0
4 bits of the 0th row and 128th column of 17-0 to 17-7 are allocated, and the 2-port memories 17-0 to 17- are assigned to the 4-bit areas of the head area A0 of the 3rd row of the frame memory space FMS. 4 bits of 0th row and 192nd column of 7 are allocated.

That is, in this embodiment, the 2-port memory 17-i (i =
If the areas obtained by dividing each row of 0 to 7) in units of 64 bits are B0 to B3, the j-th row (j = 0 to 0) of the same memory 17-i will be described.
255), each 4 bits of each column position of the area B0 are bits 4i to bits of the areas A0 to A63 of the 4th row of the frame memory space FMS.
4i + 3 are allocated in a distributed manner, and 4 bits at each column position of the area B1 of the j-th row of the memory 17-i are allocated to the frame memory space FM.
Bits 4i to 4i + 3 of areas A0 to A63 in the 4j + 1th row of S
It is distributed and allocated to. Similarly, the j-th memory 17-i
Each 4 bits of each column position of the row area B2 is the 4j + th bit of the area A0 to A63 of the 2nd row of the frame memory space FMS.
4i + 3 are allocated in a distributed manner, and each 4 bits of each column position of the area B3 of the j-th row of the memory 17-i is a frame memory space.
Bits 4i to 4i + of areas A0 to A63 on the 4th row + 3rd row of FMS
3 are distributed and allocated.

Therefore, the 2-port memory 17-0 has four memory planes P0 to P3 (see FIG. 5 (a)) assigned to bits 0 to 3 of the respective areas A0 to A63 of the frame memory space FMS. Memory plane, for example, memory plane
Bit 0 to bit 63 of the area B0 of the j-th row (j = 0 to 255) of P0 are bit 0 of the areas A0-A63 of the 4j-th row of the frame memory space FMS as shown in FIG. 4 (b). Assigned to
Bit 0 to bit of area B1 in the j-th row of memory plane P0
63 is an area A0 to A of the 4j + 1th row of the frame memory space FMS
Assigned to bit 0 of 63. Similarly, memory plane
Bits 0 to 63 of the area B2 of the j-th row of P0 are, as shown in FIG. 4 (b), the 4j + th of the frame memory space FMS.
Bit 0 of the area A0 to A63 of the second row, bit 0 to bit 63 of the area B3 of the jth row of the memory plane P0 are assigned to bit 0 of the area A0 to A63 of the 4j + th row of the frame memory space FMS. To be

Now, the x address (x coordinate) of any two-dimensional memory address (coordinate) on the frame memory space FMS of the frame memory 17 is displayed by 11 bits of x10 to x0 (LSB),
It is expressed by 10 bits of y address (y coordinate) y9 to y0 (LSB). As is clear from the description of the memory configuration of the frame memory 17, the x addresses x4 to x2 indicate the memory (memory chip) number (#i) of the 2-port memory 17-i to which the corresponding address is assigned, Two bits x1 and x0 are 2-port memory 17-i to which the corresponding address is assigned.
The number (bit number in 2-port memory) indicating the inner memory plane is shown. The 5 bits x4 to x0 indicate the bit position (bit number in word) in the 32-bit area to which the corresponding address is assigned. Lower 2 bits y1, y of the above y address
The concatenated data of 0 and the upper 6 bits x10 to x5 of the x address is the 2-port memory 17-i to which the corresponding address is assigned.
Column address of the upper 8 bits of the y address y9
~ Y2 is a 2-port memory 17 to which the corresponding address is assigned
-I indicates the row address. The above relationship is shown in FIG.

Here, the configuration of FIG. 1 will be described. In the address control circuit 16 of FIG. 1, 31 and 32 are memory start coordinates BM (in the frame memory space FMS) for background display.
x, BMy is set memory start coordinate register (BMX, B
MY), 33-1 to 33-3 are hardware windows W1 to W3
Memory start coordinate register (WMX) in which x memory start coordinates WMx1 to WMx3 for display (on frame memory space FMS) are set, and y memory start coordinates WMy1 to WMy3 are set in 34-1 to 34-3. This is the memory start coordinate register (WMY). 35-1 to 35-3 are for displaying the hardware windows W1 to W3 (on the screen space SS) x
Window display coordinate registers (WSX) in which the display start coordinates WSx1 to WSx3 are set, and 36-1 to 36-3 are window display coordinate registers (WSY) in which the y display start coordinates WSy1 to WSy3 are similarly set. 37-1 to 37-3 are window display coordinate registers (WEX) in which the x display end coordinates WEx1 to WEx3 (on the screen space SS) for displaying the hardware windows W1 to W3 are set, 38-1 to 38-3 Is a window display coordinate register (WEY) in which y display end coordinates WEy1 to WEy3 are similarly set. Registers 31, 32, 33-1, ... 38-3 are
It can be set by the CPU 11 shown in FIG. 39, 40 is CRT
Current x, y on monitor 22 (on screen space SS)
Scan counter (VXC, VYC) that indicates the display scan position
Is.

41 and 42 are the background (frame memory space FMS) to be displayed at the current display scan position of the CRT monitor 22.
Memory address counter (BMXC, BMYC) indicating the memory address (x, y coordinates), 43-1 to 43-3, 44-1 to 44
-3 is the (frame memory space FMS of windows W1 to W3 that should be displayed at the current display scan position of the CRT monitor 22.
It is a memory address counter (WMXC, WMYC) that shows the memory address (x, y coordinates) (above). 45-1 to 45-3 are window enable registers (WEN) that specify whether or not to display windows W1 to W3, and can be set by the CPU 11.

46-1 to 46-3 are window detection circuits. The window detection circuit 46-i (i = 1 to 3) has a window display coordinate register 35-i when window Wi display is designated by the window enable register 45-i.
To 38-i and the contents of the scan counters 39 and 40 are compared, and the window is displayed when the display scan position indicated by the scan counters 39 and 40 is inside the window Wi defined by the registers 35-i to 38-i. A window detection circuit that outputs a detection signal WONi. The window detection circuit 46-i receives the data transfer signal DTi when horizontal retrace, when the x coordinate indicated by the scan counter 39 enters the window Wi area, and when it exits the window Wi area. Is output.

47 is a background memory address indicated by the memory address counters 41 and 42 and a memory address counter 43-
A multiplexer (MUX) 48 for selecting one of the window memory addresses indicated by 1,44-1 to 43-3,44-3 according to a window selection signal WS0, WS1 from a priority control circuit 73, which will be described later, An OR gate which will be described later includes a drawing memory address (drawing address) supplied via (the drawing address bus 14b of) the drawing bus 14 shown in FIG. 2 and a display memory address (display address) selectively output from the multiplexer 47. A multiplexer that switches in accordance with the data transfer signal DT from 71, 49 is a memory address selectively output from the multiplexer 48 (y address consisting of 9 bits of y9 to y0, x address consisting of 11 bits of x10 to x0). 2-port memory 17-0 to 17-7 according to the transfer signal DT
It is an address conversion circuit that converts each address. 71 is an OR gate that takes the OR of the data transfer signals DT1 to DT3 output from the window detection circuits 46-1 to 46-3 and outputs the OR output as the data transfer signal DT. 72 is the window W1 to W3. Specify display priority, for example p0 to p2
Priority register consisting of 3 bits, 73 is the window detection signal WON1 from the window detection circuits 46-1 to 46-3
~ Based on the setting values of WON3 and priority register 72, the window with the highest priority among the detected windows is determined, and the window number is a 2-bit selection signal.
This is a priority control circuit that outputs WS0 (lower) and WS1 (upper). Note that WS0 = WS1 = 0 indicates the background.

FIG. 6 shows a block configuration of the address conversion circuit 49 shown in FIG. In the figure, reference numeral 51 is an adder for adding "1" to x addresses (x coordinates) x10 to x5 of x5 or more among the memory addresses output from the multiplexer 48, and 52-0 to 5-5.
2-7 is provided corresponding to the 2-port memories 17-0 to 17-7, and the above x addresses x10 to x5 from the multiplexer 48 are provided.
Or a multiplexer that selects either one of the x addresses incremented by the adder 51, 53 is a multiplexer
To the multiplexers 52-0 to 52-7 (the selection control terminal S thereof) based on the 3 bits x4 to x2 of the memory addresses output from 48 and the data transfer signal DT from the OR gate 71 shown in FIG. Is a mask generation circuit for generating the selection mask signals S0 to S7. The input / output logic of the mask generation circuit 53 is shown in FIG. Referring again to FIG. 6, 54-0 to 54
-7 is an address in which y1 and y0 of the memory addresses output from the multiplexer 48 are added to the upper addresses of the addresses selectively output from the multiplexers 52-0 to 52-7 and a memory address output from the multiplexer 48. of
By switching y9 to y2 according to the switching signal CASL from the memory timing circuit (not shown), a 2-port memory
It is a multiplexer for switching a column address and a row address for 17-0 to 17-7.

FIG. 8 shows a block configuration of the priority control circuit 73 shown in FIG. In the figure, 81-0 and 81-1 have 8 inputs 0 to 7, and the window detection circuit 46-1 shown in FIG.
Select signal for input i (i is one of 0 to 7) specified by window detection signals WON1 to WON3 from ~ 46-3
It is an 8-input 1-output multiplexer that is selected as WS0 and WS1. In this embodiment, the signals of logic "0", "1", "0" are fixedly input to the inputs 0, 1, 2 of the multiplexer 81-0, and the input 0 also has p0 of the priority register 72 similarly. Bit is input. Input of multiplexer 81-0 4,5
A signal of logic "1" is fixedly input to each of the two, and a level inversion signal from the p2 bit inverter 82 of the priority register 72 is also input to the input 6. Further, a signal q0 described later is supplied to the input 7 of the multiplexer 81-0. On the other hand, signals of logic "0", "0", "1" are fixedly input to the inputs 0, 1, 2 of the multiplexer 81-1 and the p0 bit inverter of the priority register 72 is also input 3 for the same. The level inversion signal from 83 is input. Also multiplexer
A signal of logic "1" is fixedly input to the input 4 of 81-1 and a level inversion signal from the p1 bit inverter 84 of the priority register 72 is also input to the input 5. Further, a signal of logic "1" is fixedly input to the input 6 of the multiplexer 81-1 and the signal q1 is also supplied to the input 7. This signal q1 is the output signal of the NAND gate 85 which takes the NAND of p1 and p2 bits of the priority register 72. On the other hand, the signal q0 is an output signal of the OR gate 86 which takes the OR of the signal q1 and the p2 bit level inversion signal of the priority register 72.

FIG. 9 shows the setting contents p2 to p0 of the priority register 72.
And the display priority of windows W1 to W3 and the relationship between signals q0 and q1.

As is clear from FIGS. 8 and 9, the priority control circuit 73 detects a window (window display area) when it is detected by at least one of the window detection circuits 46-1 to 46-3. The window having the highest display priority indicated by the priority register 72 is determined and the selection signals WS1 and WS0 indicating the window number are output. For example, if the window W1 is determined,
WS1 and WS0 are "0" and "1", and when the window W2 is determined, WS1 and WS0 are "1" and "0". Similarly, when the window W3 is determined, both WS1 and WS0 are "1".
Becomes On the other hand, when none of the windows W1 to W3 is detected, that is, the window detection signals WON1 to WO
When both N3 are logic "0", both WS1 and WS0 are "0", indicating the background.

FIG. 10 shows a block configuration of the shift register circuit 19 shown in FIG. In the figure, 61 is a 2-port memory 17-
A 32-bit register that latches the data serially output from 0 to 17-7 in 4-bit units (may be omitted in low resolution and low speed systems), 62 is a 2-port memory 17-0 to 17-
3-bit chip specification counter (CNTR) that specifies the current display target data output source memory (memory chip) of 7
Is. The counter 62 outputs x4 to x of memory addresses output from the multiplexer 48 in the address control circuit 16.
The 3 bits of x2 are loaded at the start of the data transfer memory cycle, and are counted up, for example, eight times for each memory cycle. 63 selects one of the 4-bit output data from the 2-port memories 17-0 to 17-7 latched in the register 61 according to the count value of the counter 62 8
Input / output 1 output multiplexer, 64 is multiplexer 63
The 4-bit data selected and output from is converted into serial data and the lookup table (LUT) 20 shown in FIG.
It is a 4-bit shift register (SR) that outputs to.

 Next, the operation of the embodiment of the present invention will be described.

First, a normal background display will be described.
The CPU 11 sets the memory start coordinates BMx, BMy in the memory start coordinate registers 31, 32 in the address control circuit 16 via the system bus 12 and resets the window enable registers 45-1 to 45-3. Register 45
When -1 to 45-3 are in the reset state, the window detection signals WON1 to WON3 are the window detection circuits 46-1 to 46-3.
Both are kept at "0" by. In this case, the priority control circuit 73 sets all the selection signals WS1 to WS0 to "0" regardless of the setting contents of the priority register 72. Multiplexer 47
When both WS1 and WS0 are “0”, selects only the address indicated by the memory address counters 41 and 42 for background display. The counter 41 presets the contents of the register 31 for each horizontal retrace, and the counter 42 registers 32 for each vertical retrace.
Preset the contents of. Window detection circuit 46-1
46-3 sets the data transfer signals DT1 to DT3 to "1" once for each horizontal retrace line. When at least one of DT1 to DT3 becomes "1", the data transfer signal DT output from the OR gate 71 also becomes "1". When DT = 1, the multiplexer 48 selects the address output from the multiplexer 47 (here, the address for background display).

X4 of the address output from the multiplexer 48
.. x2, and the data transfer signal DT from the OR gate 71 are supplied to the mask generation circuit 53 in the address conversion circuit 49. The mask generation circuit 53 outputs mask selection signals S0 to S7 according to the logic shown in FIG. 7 in accordance with the combination of the logical values of x4 to x2 and DT. That is, the mask generation circuit 53
= O, the mask selection signals S0 to
Set all S7 to “0”. On the other hand, when DT = 1, x4 to x2
If the value i indicates 0, that is, if the data is transferred from the word boundary (bit 0) of the 32-bit area of the frame memory space FMS of the frame memory 17, the mask generation circuit 53 outputs all the mask selection signals S0 to S7. Set to “0”. On the contrary,
If i is 1 or more, that is, if the data transfer is from a position that is not a word boundary within the 32-bit area, the mask generation circuit 53 sets the mask selection signals S0 to Si-1 to "1" and the mask selection signal Si. ~ Set S7 to “0”.

The multiplexers 52-0 to 52-7 are the mask generation circuit 53.
If the mask selection signals S0 to S7 from "0" are "0", x10 to x5 of the addresses output from the multiplexer 48 are selected, and if "1", the adder 51 sets 1 to x10 to x5. The added value (that is, the value obtained by adding 1 to the lower 6 bits of another address of the corresponding 2-port memory) is selected. Select output data from multiplexers 52-0 to 52-7 (6 bits)
2 bits of y1 and y0 of the display address selected by the multiplexer 48 are added to the upper part of the. The data to which y1 and y0 are added and the display addresses y9 to y0 selected from the multiplexer 48 are the two-port memory 17-
As column address and row address of 0 to 17-7,
The signals are switched and output from the multiplexers 54-0 to 54-7.
As a result, when the value i indicated by x4 to x2 is 1 or more, the access position of the 2-port memories 17-0 to 17-i-1 is one column next to the 2-port memories 17-i to 17-7. , It is possible to output in units of 32 bits from positions other than word boundaries. Since the mask selection signal S7 is always "0", the multiplexer 52-7 always outputs x10 from the multiplexer 48.
Select ~ x5. Therefore, the multiplexer 52-7 can be omitted.

The data transfer signal DT from the OR gate 71 is also supplied to a memory timing circuit (not shown). This memory timing circuit synchronizes with the memory clock MCK in response to the signal DT and includes the frame memory 17 (the 2-port memories 17-0 to 17-
The data transfer cycle of 7) is performed, and the drawing circuit 13 or
The CPU 11 is notified of random access prohibition.

The 2-port memories 17-0 to 17-7 are the multiplexer 54
Addressing is performed by the row and column addresses switched and output from -0 to 54-7. As a result, 4 × 256 bits of each designated row of the two-port memory 17-0 to 17-7 is shifted to each shift register (not shown) in the memory 17-0 to 17-7.
A data transfer cycle (memory data transfer cycle) is performed, and then serial output is performed in order from the bit (4 bits) in the designated column, for example, in synchronization with the memory clock MCK. 2-port memory 17-0 to 17
Each 4-bit serial output data from -7 is latched in the register 61 in synchronization with the serial output operation.
On the other hand, the counter 62 is loaded with x4 to x2 of the display addresses selected by the multiplexer 48 at the same time as the latch operation of the register 61 in the memory cycle (data transfer memory cycle) where DT = 1. x4 to x2
Indicates the memory number (#i) of the 2-port memory 17-i, which is bit-allocated to the memory address (memory coordinate for background display in this example) selected from the multiplexer 48. The counter 62 counts up eight times in each memory cycle.

The multiplexer 63 outputs the 4-port output data from the 2-port memories 17-0 to 17-7 latched in the register 61 from the 2-port memory having the memory number (#i) indicated by the count value of the counter 62. Select output data. As a result, the data sequentially output from the 2-port memories 17-0 to 17-7 in 4-bit units from the multiplexer 63 are memory numbers #i, # i + 1 ... # 7, # 0 ... # i-1.
Are repeatedly selected and output in this order. The 4-bit selection output data from the multiplexer 63 is converted into serial data by the shift register 64. The serial output data from the shift register 64 is supplied to the look-up table 20 and used for screen display in the screen space SS of the CRT monitor 22.

The above operation will be described more specifically. For example, address 12 of the frame memory space FMS of the frame memory 17 (0th line 1st
Suppose you want to display from 2 columns of memory coordinates).
In this case, x4 to x2 are "3", and this value is the counter 62.
2 port memory 17-0 to 17-
Data sequentially output in units of 4 bits from 7 are repeatedly output from the multiplexer 63 in the order of memory numbers # 3, # 4 ... # 7, # 0, # 1, # 2. The value of x4 to x2 is "3".
In the case of, the 2-port memory 17-0 with the memory numbers # 0 to # 2
The column address of 17-2 is the other 2-port memory 17-3
It is +1 compared to that of 17-7. Therefore, in the output data (32 bits) from the shift register 64 in each memory cycle, the 4 bits from the 2-port memory 17-3, which is bit-assigned to the 12th address of the frame memory space FMS, are located at the leftmost position. And below 2 port memory
17-4 to 17-7 in the same row, 4 bits from the column position, and 1 column of the 2-port memory 17-0 to 17-2, 4 bits from the next position, so that the display from the 12th address is correct. Can be done.

Next, the window display will be described with reference to the timing chart of FIG. 11 by taking as an example the case of performing two window displays of W1 and W2 which partially overlap each other as shown in FIG. First, the CPU 11 causes the memory start coordinate registers 33-1 and 34-1 in the address control circuit 16 to display the (frame memory space FM) for the hardware window W1.
The memory start coordinates WMx1 and WMy1 (on S) are set, and the memory start coordinates WMx2 and WMy2 (on the frame memory space FMS) for the hardware window W2 are set in the memory start coordinate registers 33-2 and 34-2. Further, the CPU 11 causes the window display coordinate registers 35-1 and 36-1 to display the display start coordinate WS (on the screen space SS) for the hardware window W1.
Set x1 and WSy1, and set the window display coordinate register 35-2, 3
The display start coordinates WSx2 and WSy2 (on the screen space SS) for the hardware window W2 are set in 6-2. Similarly C
PU11 uses the window display coordinate registers 37-1 and 38-1 for the hardware window W1 (on the screen space SS).
The display end coordinates WEx1, WEy1 are set, and the display end coordinates WSx2, WSy2 (on the screen space SS) for the hardware window W2 are set in the window display coordinate registers 37-2, 38-2. Further, the CPU 11 uses the window enable register 4
Set 5-1 and 45-2.

When registers 45-1 and 45-2 are set, the window
Display of W1 and W2 is permitted. In this case, the window detection circuit 46-1 determines that the y coordinate of the display scan position indicated by the scan counter 40 is within the y-direction boundary of the window indicated by the registers 36-1 and 38-1 and the scan counter 39-1.
From the memory cycle where the x coordinate of the display scan position indicated by is coincident with the left boundary (of the display area) of the window W1 indicated by the register 35-1 is coincident with the right boundary (of the display area) of the window W2 indicated by the register 37-1. The window detection signal WON1 is set to "1" during the memory cycle. Further, the window detection circuit 46-1 uses the memory cycle in which the value of the scan counter 39 matches the value of the register 35-1 and the memory cycle next to the memory cycle in which the value of the scan counter 39 matches the value of the register 37-1. And the data transfer signal
Set DT1 to “1”. The above is the window detection circuit 46-2.
Is the same as above, and if necessary, in the above explanation of the operation of the window detection circuit 46-1, the registers 35-1 to 35-1
38-1 to registers 35-2 to 38-2 and data transfer signal DT
Please replace 1 with the data transfer signal DT2.

Of the window detection signals WON1 to WON3 from the window detection circuits 46-1 to 46-3, the signal WON1 is first set to "1". In this case, the priority control circuit 73 outputs the selection signal WS1 of logic “0” and the selection signal WS0 of logic “1” to the multiplexer 47 in order to specify the window W1. The multiplexer 47 responds to WS1 = 0 and WS0 = 1 by displaying the window indicated by the memory address counters 43-1 and 44-1.
Select W1 display memory address.

Now, in the first memory cycle T1 of the period when the signal WON1 is "1", that is, the detection period of the window W1 (display area thereof), the data transfer signal of logic "1" is output from the window detection circuit 46-1.
DT1 is output. In the OR gate 71, the signal DT1 is logical "1".
During the cycle T1 of, the data transfer signal DT is set to logic "1" as shown in the timing chart of FIG. When DT = 1, the display address (here, the address for displaying the hardware window W1) selected and output from the multiplexer 47 is converted by the multiplexer 48 into the address conversion circuit.
It is selectively output to 49 and is converted into an address for each of the 2-port memories 17-0 to 17-7 in the same address conversion circuit 49 as in the background display described above.

The 2-port memories 17-0 to 17-7 are addressed by the address from the address conversion circuit 49 when DT = 1. As a result, the 4 × 256 bits of each designated row of the 2-port memory 17-0 to 17-7 becomes the same memory 17-0 to 17-7.
The data is loaded into each shift register (not shown) therein, and then serially output in synchronization with the memory clock MCK from the bit (4 bits) of the designated column. Each 4-bit serial output data from the 2-port memory 17-0 to 17-7 is x4 to the address selected by the multiplexer 48.
When the value of x2 is i, the memory numbers #i, # i + 1 ... # 7, # 0 ... #i are the same as in the background display described above.
The output is repeatedly switched in the order of -1. As a result, the display of the memory contents of the window W1 area in the frame memory 17 is started.

The window W1 is displayed as described above, and when the window detection circuit 46-2 eventually detects the display area of the window W2 (the left boundary thereof), the same circuit 46-2 is displayed.
Then, as shown in FIG. 11, a window detection signal WON2 of logic "1" is output. The priority control circuit 73 uses a selection signal.
When WS1 and WS2 are logic "1", that is, the detection circuits 46-1 and 46-2
When the display areas of the windows W1 and W2 are detected by, the window having the higher display priority among the windows W1 and W2 is determined according to the setting content of the priority register 72. Now, assuming that the window W2 is set to have a higher priority (W2> W1) than the window W1 by the priority register 72, the priority control circuit 73 determines that the window W2 has a higher priority.
In order to specify W2, the selection signal WS1 of logic "1" and the selection signal WS0 of logic "0" are output to the multiplexer 47.
The multiplexer 47 selects the window W2 display memory address indicated by the memory address counters 43-2 and 44-2 according to WS1 = 1 and WS0 = 0.

Now, in the first memory cycle T2 of the period in which the signal WON2 is "1", that is, the detection period of (the display area of) the window W2, the data transfer signal of logic "1" is output from the window detection circuit 46-2.
DT2 is output, whereby the data transfer signal DT becomes logic "1" again as shown in the timing chart of FIG. This results in a multiplexer during cycle T2.
The address for displaying the hardware window W2 selectively output from 47 is selectively output to the address conversion circuit 49 by the multiplexer 48, and is converted into the address of each of the 2-port memories 17-0 to 17-7 in the address conversion circuit 49. It The 2-port memories 17-0 to 17-7, when DT = 1,
Addressing is performed by the address from the address conversion circuit 49. As a result, similarly to the case of displaying the window W1 described above, the memory contents of the window W2 area in the frame memory 17 are read out, and the display of the window W2 area is started.

When the window W2 is displayed as described above, and eventually the value of the scan counter 39 matches the value of the register 37-1, the window detection circuit 46-1 detects the right boundary of the display area of the window W1. Then, the window detection signal WON1 is returned to logic "0" as shown in FIG. 11, and the data transfer signal DT1 is transferred in the next memory cycle T3.
To "1" again. At this time, the window W2 having a higher display priority than the window W1 is being displayed, and the window detection circuit 46-2 outputs the window detection signal WO of logic "1".
N2 is still being output. Therefore, the selected output content of the multiplexer 47 is the memory address counter 43-
The address for displaying the window W2 indicated by 2,44-2 remains the same. In the cycle T3, the window W2
Since the data transfer cycle of the display area is unnecessary, the signal DT can be prohibited.

Now, the value of the scan counter 39 is now in the register 37.
-2, the window detection circuit
46-2 detects the right boundary of the display area of window W2,
The window detection signal WON2 is set to logic "0" as shown in FIG.
At the same time, the data transfer signal DT2 is set to "1" again in the next memory cycle T4. Priority control circuit 73, W
When ON2 becomes “0”, WON1 and WON3 are also “0”.
Set the selection signals WS1 and WS0 to “0” to specify the background. When WS1 and WS0 become “0”, the multiplexer 47 selects the background display address indicated by the memory address counters 41 and 42, as described above. The background display address selected by the multiplexer 47 is selectively supplied to the address conversion circuit 49 by the multiplexer 48 during the T4 period of DT = 1.
Further, the address is converted by the circuit 49 and supplied to the frame memory 17, whereby the background display described above is restarted.

As described above, according to this embodiment, the frame memory 17 for displaying the background and the window is displayed.
The x coordinate (display start coordinate) of (frame memory space FMS) can be finely specified up to a multiple of 4. The display start y-coordinate can be specified in 1-dot units in both the background display and the window display.

Although the bit map display device has been described above, the present invention is directed to a device which has a frame memory and cuts out and outputs the contents of an arbitrary rectangular area in the memory, for example, a bit map image processing of a laser printer, an electrostatic plotter device or the like. It can also be applied to devices.

[Effects of the Invention] As described in detail above, according to the present invention, a hardware window using a two-port memory can be realized, so that the transfer speed can be increased. Also, according to the present invention, the display priority order among a plurality of hardware windows can be arbitrarily specified, and the priority order can be changed easily and at high speed. Moreover, even if there is overlap between windows, it is possible to easily switch windows based on priority.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address control circuit directly related to the present invention, FIG. 2 is a block diagram showing a bit map display device having the address control circuit shown in FIG. 1, and FIG. FIG. 4 (a) and FIG. 4 (b) are diagrams for explaining the concept of the hardware window.
FIG. 5 is a diagram for explaining the memory configuration of the frame memory shown in FIG. 5, FIG. 5 is a diagram for explaining the relationship between the address of the frame memory and the address of the 2-port memory that constitutes the frame memory, and FIG. 6 is the address shown in FIG. FIG. 7 is a block diagram of the conversion circuit, FIG. 7 is a diagram showing the input / output logic of the mask generation circuit shown in FIG. 6, FIG. 8 is a block diagram of the priority control circuit shown in FIG. 1, and FIG. FIG. 10 is a diagram showing the setting contents of the priority register shown in FIG. 1, the window display priority defined by the same contents, and the correspondence relationship with the signals q0 and q1 in the priority control circuit shown in FIG. 2 is a block diagram of the shift register circuit shown in FIG. 2, and FIG. 11 is a timing chart for explaining the operation when the hardware window is displayed. 11 ... CPU, 16 ... Address control circuit, 17 ... Frame memory, 17-0 to 17-7 ... 2-port memory, 19 ... Shift register circuit, 22 ... CRT monitor, 46-1 to 46-3 ... Window detection circuit, 47,48,52-0 to 52-7,54-0 to 54-7,63,8
1-0, 81-1 ... Multiplexer (MUX), 49 ... Address conversion circuit, 51 ... Adder, 53 ... Mask generation circuit, 62 ... Counter (CNTR), 64 ... Shift register (SR), 72 ... Priority register , 73 ... Priority control circuit.

Claims (1)

(57) [Claims] 1. A frame memory for storing image data having p 2-port memories of 1 bit × m (columns) × n (rows), wherein each row of the two-dimensional memory space is divided by l · p bits. Then, in each l-bit area obtained by equally dividing each divided area into p, the l of each address position of the 2-port memory is
A frame memory in which bits are allocated in a fixed order, a plurality of window setting means for setting an arbitrary window display area, and a window display for setting a display priority of each window display area set by the plurality of window setting means For each window display area, it is determined whether the priority setting means, the scan counter means indicating the display scan position, and the display scan position indicated by the scan counter means are within the window display area set by the plurality of window setting means. The window display means for detecting the background detection data, and the background display data to the display scan position indicated by the scan counter means are stored according to the detection result of the window detection means and the setting contents of the window display priority setting means. The above frame The background address indicating the internal memory coordinates, and the frame memory internal memory coordinates storing the window display data to the display scan position indicated by the scan counter means are set by the plurality of window setting means. A first multiplexer that selects one of the window addresses shown for each window display area, and a second multiplexer that switches the address output from the first multiplexer and the drawing address according to the detection result of the window detecting means. Of the 2-port memory allocated to each l bit obtained by equally dividing p consecutive data of lp bits from the bit position in the memory space of the frame memory indicated by the address output from the second multiplexer. 2 for each address
The address conversion circuit generated for each port memory and the address generated for each 2-port memory from this address conversion circuit are used to generate an l from each 2-port memory.
A shift register circuit for sequentially selecting data output serially bit by bit from output data from a 2-port memory to which an address output from the second multiplexer is assigned, and converting the serial data into serial data; A bit map image processing device characterized in that an image is output by serial data output from the shift register circuit.