JPS63241671A - Bit map image processor - Google Patents

Abstract

PURPOSE:To accelerate a transfer speed by providing a window detecting circuit for detecting a window position and a frame memory for storing image data. CONSTITUTION:An address converting circuit in an address control circuit 16 generates, for respective two port memories, the address of two port memories to allocate respective l bits equally divided into (p) the data of a continuous l.p bit from a bit position on the memory space of a frame memory 17 shown by the address outputted from a multiplexer (MUX) 48. For respective 2 port memories, the lXm bit of the designated row is serially outputted at an lbit unit in the order from the bit of the designated column by the address from an address converting circuit 18. A shift register 19 selects the data serially outputted at the l bit unit from respective 2 port memories in the order from the output data from 2 port memories to allocate the address outputted from the MUX 48 and converts them to serial data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bitmap image processing device having a hardware window function.

(Prior Art) In recent years, bitmap image processing devices, such as bitmap display devices, require a display function called multi-window display in order to display a plurality of pieces of information on one display screen. Conventionally, as a means to realize window display, Nikkei Electronics, 19
8B, 5.19 (no, 395pp 221-25
As shown in (1) bit blt method (
Two methods are known: (2) a software window based on a bit block transfer method (2) and a hardware window based on display address control.

However, with the software method (1), as shown in the above literature, as the window size increases, the transfer time becomes longer, responsiveness decreases, and prioritization becomes complicated when windows overlap. There were some problems. On the other hand, in the hardware method (2), in the case of the f8278B (display control LSI manufactured by Intel Corporation in the United States) shown in the above document, when the number of windows increases, it becomes difficult to move the windows or change the display address. Furthermore, when changing the priority order, updating the contents of memory such as a disk libter becomes complicated, and the number of memory accesses by 182786 increases, resulting in a decrease in performance on the processor side. Furthermore, in the 1827H, there was a problem in that if a 2-port image memory was used as the frame memory, the hardware window function could not be used.

(Problems to be Solved by the Invention) As described above, the conventional bitmap display device cannot realize an efficient hardware window function using a two-port memory.

The present invention has been made in view of the above circumstances, and its object is to provide a bitmap image processing device that can realize an efficient hardware window function by using a two-port memory as a frame memory.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a window detection circuit for detecting a window position and a frame memory for storing image data are provided. This frame memory is Nobit Xm (column) x
It has p 2-port memories of n (rows). The two-dimensional memory space of the frame memory is managed by dividing each row into 1.p bit units, and each divided area is divided into nine equal parts, each l bit area containing the nobit at each address position of the two-port memory. Allocated in a fixed order. The present invention further includes a first multiplexer that switches between the background address and the window address in accordance with the detection result of the window detection circuit, and a first multiplexer that switches the address output from the first multiplexer and the drawing address in accordance with the detection result of the window detection circuit. a second multiplexer that switches
an address conversion circuit that converts the address output from the multiplexer into an address for each of the two port memories;
A shift register circuit is provided which further converts the data serially output in 1-bit units from each 2-port memory into serial data based on the address of each 2-port memory converted and output from the address conversion circuit.

(Function) In the above configuration, the address conversion circuit divides the data of consecutive nord bits from the bit position in the memory space of the frame memory indicated by the address output from the second multiplexer into nine equal parts, each of 12 bits. The address of the 2-port memory to which is allocated is generated for each 2-port memory. Each 2-port memory is addressed by an address from the address conversion circuit, whereby the no.times.m bits of the designated row are serially output in units of l bits starting from the bits of the designated column. The shift register circuit sequentially selects the data serially output in l-bit units from each 2-port memory from the output data from the 2-port memory to which the address output from the second multiplexer is assigned and converts it into serial data. do. This serial data is used for image output. That is,
According to the above configuration, a hardware window using 2-port memory is possible.

(Embodiment) Hereinafter, an embodiment of the present invention will be described using a bitmap display device as an example with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an address control circuit provided in a bit map display device, and FIG.
The figure is a block diagram of a bitmap display device. In the bitmap display device shown in FIG. 2, 11 is a CPU that controls the entire device, and 12 is a CPU.
There are 11 system buses. 13 is straight line generation, bit
A drawing circuit that performs bit (bit block transfer) etc. 14 is a drawing data bus 14a1 a drawing address bus 14
A drawing bus 14 for the drawing circuit 13 is composed of a control bus 14c and a control bus 14c. Note that drawing processing such as straight line generation is performed by the CPU.
When using IL, the drawing circuit 13 and the drawing bus 1
4 can be omitted. 15 is a CRT monitor 22 which will be described later.
1B is a display timing circuit that generates vertical and horizontal synchronization signals, blanking signals, etc. for the display, 1B is a display memory scan address generation circuit, and this address and the drawing address bus 14.
17 is a frame memory for storing figures, images, etc.; and 17, a frame memory for storing figures, images, etc.; Frame memory 17 is address control circuit 1
It is addressed by the memory address output from B. 18 is a data control circuit (optional) that performs color conversion, arithmetic processing (rusk operation), alignment, etc. when drawing to the frame memory 17; 19 is a shift circuit that converts display data output from the frame memory 17 into serial data; It is a register circuit. 20 receives output data from the shift register circuit 19 and performs color conversion;
Lookup table (LUT) for brightness conversion, 2
1 is a digital/analog converter (
DAC), 22 is a CRT monitor that displays the output signal from the converter 21 as a video signal on the screen.

The concept of a hardware window realized by the bitmap display device of FIG. 2 will now be explained with reference to FIG. 3. In this embodiment, the memory space (frame memory space) FM of the frame memory 17
S is 2048 x 1024 dots, and CRT monitor 2
Displayable area (screen space) SS of 2 is 1280X
There are 1024 dots. That is, the memory space FMS of the frame memory 17 is set to be sufficiently large compared to the screen space SS of the CRT monitor 22.

In this example, the starting position is 1280x
An area of 1024 dots is displayed on the entire screen space SS. This is called background display. Furthermore, in this embodiment, an arbitrary rectangular area on the frame memory space FMS having the same size as this area is displayed in an arbitrary rectangular area on the screen space SS instead of the background display. This is called hardware window display.

Next, the memory configuration of the frame memory 17 that realizes the above frame memory space FMS will be explained in FIGS. 4(a) and 4(a).
This will be explained with reference to b). The frame memory 17
As shown in Figure (a), eight 2-port memories 17-0~
17-7.

The 2-port memories 17-O to 17-7 are 4-bit x 256 (column) such as NEC's μPD412B4.
It is a 2-port memory with a ×256 (row) shift register. Frame memory space FMS of frame memory 17 realized by 2-port memories 17-0 to 17-7
Each row has 64 areas AO to Al33 in units of 32 bits.
It is divided into and managed.

Area A in the 0th row of the frame memory space FMS.

The 4 bits in the 0th row and 0th column in the two-dimensional memory space of the 2-port memory 17-0 are assigned to bits 0 to 3 of the frame memory space FMSO. 7 is assigned 4 bits in the 0th row and 0th column of the 2-port memory 17-1. Similarly, bits 28 to 28 of the area AO in the 0th row of the frame memory space FMS
Bit 31 contains the 0th row and 0th bit of the 2-port memory 17-7.
4 bits of the column are allocated. Further, (bits 0 to 3 .
Each 4-bit area (bit 4 to bit 7, . . . bit 28 to bit 31) has two port memories 17-o to 17-o.
The 4 bits in the 0th row and 1st column of -7 are allocated. Similarly, the final area AB3 of the 0th row of the frame memory space FMS
Each 4-bit area includes 2-port memories 17-0 to 17-1.
4 bits in the 0th row and 63rd column of the frame memory space FMS are allocated, and each 4 bit area of the leading area AO of the first row of the frame memory space FMS is assigned the 0th row of the 2-port memories 17-θ to 17-7.
Four bits in the 64th row and column are allocated. Furthermore, 4 bits in the 0th row and 128th column of the 2-port memories 17-0 to 17-7 are allocated to each 4-bit area in the leading area AO in the 2nd row of the frame memory space FMS. Each 4-bit area of the first area AO of the third line of the 2-port memories 17-0 to 17-7 contains
4 bits of the column are allocated.

That is, in this embodiment, the two-port memory 17-i (i
= 0 to 7) is divided into 64-bit units and the area obtained is BO-B3. The 4th bit is the area A in the 4jth row of the frame memory space FMS.
Bits 41 to 41+3 of O-AB3 are allocated in a distributed manner, and 4 bits in each column position of area B1 in the jth row of the memory 17-1 are allocated to bits 41 to 41+3 of the frame memory space FMS.
1 row area AO~, 13 bits 41~bits 41+3
will be distributed and allocated. Similarly, 4 bits in each column position of area B2 in the jth row of the memory 17-1 are distributed and allocated to bits 41 to 41+3 of areas AO to AH in iJj+2 rows of the frame memory space FMS. The 4 bits in each column position of area B3 in the jth row of 17-1 are as follows:
Area AO in the 4j+3rd row of frame memory space FMS
It is distributed and allocated to bits 4i to 41+3 of A63.

Therefore, the 2-port memory 17-0 is allocated to the four memory planes PO to P3, which are allocated to bits 0 to 3 of each area AO-AG3 of the frame memory space FMS.
(see FIG. 5(a)), for example, bits 0 to 63 of the area BO in the jth row (j=0 to 255) of the memory plane PO are as shown in FIG. 4(b). As shown in FIG.
Assigned to bit 0 of O to A83, memory plane P
Bits 0 to 63 of the area Bl in the third row of O are the areas AO to A6 in the 4jth, 1st row of the frame memory space FMS.
Assigned to bit O of 3. Similarly, bits 0 to 63 of area B2 in the jth row of the memory plane PO are as shown in FIG. bit 0 of area B3 in the jth row of memory plane PO
~Bit 63 is the 4j+ bit of the frame memory space FMS.
It is assigned to bit 0 of the 3-row area AD-A83.

Now, frame memory space FMS of frame memory 17
The X address (X coordinate) of any two-dimensional memory address (coordinate) above is represented by 1l bits xlo ~ xo (LSB), and the X address (y coordinate) y9 ~ yO (L
It is expressed by 10 bits of SB).

As is clear from the explanation of the memory configuration of the frame memory 17 described above, X4 to X2 of the above X addresses indicate the memory (memory chip) number (#i) of the 2-port memory 17-j to which the corresponding address is allocated, xi, xO's 2
The bit is 2-port memory 1 to which the corresponding address is assigned.
Indicates the number indicating the memory plane within 7-1 (bit number within the 2-point memory).

Furthermore, 5 bits from X4 to xO indicate the bit position within the 32-bit area (bit number within the word) to which the corresponding address is allocated. The concatenated data of the lower 2 bits yt, yo of the above X address and the upper 6 bits X10 to x5 of the X address is the 2-port memory 17- to which the corresponding address is allocated.
1 column address, and the upper 8 bits y9 to y2 of the X address indicate the row address of the 2-port memory 17-1 to which the corresponding address is allocated. The above relationship is shown in FIG.

Here, the configuration of FIG. 1 will be explained. In the address control circuit I6 of FIG. 1, 31.32 are registers (BMX, B
MY), 33.34 are registers (WM
X, WMY).

35 and 36 are start display coordinates W S x (on the screen space SS) for hardware window display.

Window display coordinate register (WS
X, WSY), 37.38 is the end display coordinate (on screen space SS) for hardware window display WE
Window display coordinate register where x, WEy are set (
WEX, WEY). Registers 31 to 38 are the second
It can be set using the CPU II shown in the figure. 39.40
is a scan counter (V) indicating the current display scan position on the CRT monitor 22 (on its screen space SS).
XC, VYC).

41 and 42 are memory address counters (BMXC) indicating the memory address (coordinates) (on the frame memory space FMS) of the background to be displayed at the current display scan position of the CRT monitor 22;

BMYC), 43.44 are memory address counters (WMXC, WMYC) indicating the memory address (coordinates) (on the frame memory space FMS) of the window to be displayed at the current display scan position of the CRT monitor 22. 45 is a window enable register (WEN) that specifies whether or not to display a window;
It can be set using the UII. 46 compares the contents of the window display coordinate registers 35 to 38 with the contents of the scan counters 39.40 when window display is specified by the register 45, and sets the scan counters 39.46 to 39.46.
A window detection circuit outputs a window detection signal WON when the display scan position indicated by 40 is within the window defined by registers 35-38. This window detection circuit 46 outputs a data transfer signal DT during horizontal retrace, when the X coordinate indicated by the scan counter 39 enters the window area, and when it exits the window area. ing. A multiplexer (MUX) 47 selects either the background memory address indicated by the memory address counters 41 and 42 or the window memory address indicated by the memory address counters 43 and 44 in accordance with the window detection signal WON from the window detection circuit 46. , 48 is the second
Drawing bus 14 (drawing address bus 14b) shown in the figure
A multiplexer 49 switches between the drawing memory address supplied via the multiplexer 47 and the display memory address selectively output from the multiplexer 47 in response to the data transfer signal DT from the window detection circuit 46.
Memory address selected and output from 8 (X of y9 to yO
This is an address conversion circuit that converts the address (X address of X10 to xO) into an address for each of the two-port memories 17-0 to 17-7 in accordance with the data transfer signal DT from the window detection circuit 46.

FIG. 6 shows the configuration of the address conversion circuit 49. In the figure, 51 is an X address (X coordinate) X1 that is greater than or equal to x5 among the memory addresses output from the multiplexer 48.
Adder that adds “1” to 0 to X5, 52-0 to 52-
7 is provided corresponding to the 2-port memories 17-0 to 17-7, and the above-mentioned X address xlO from the multiplexer 48 is provided.
A multiplexer 53 selects either x5 or the X address incremented by 1 by the adder 51, 53 is the 3 bits x4 to x2 of the memory address output from the multiplexer 48, and the window detection circuit 46 shown in FIG. This is a mask generation circuit that generates selection mask signals SO to S7 to (selection control terminals S of) multiplexers 52-0 to 52-7 based on the data transfer signal DT from the multiplexers 52-0 to 52-7. The input/output logic of this mask generation circuit 53 is shown in FIG.

Referring again to FIG. 6, 54-0 to 54-7 have yl and yo of the memory addresses output from the multiplexer 48 in the first place of the addresses selectively output from the multiplexers 52-0 to 52-7. By switching the added address and y9 to y2 of the memory addresses output from the multiplexer 48 in response to a switching signal CASL from a memory timing circuit (not shown), the 2-port memories 17-0 to 17-7 are This is a multiplexer that switches between column and row addresses.

FIG. 8 shows the configuration of the shift register circuit 19 shown in FIG. In the same figure, 61 is a 2-port memory 17-0~
A 32-bit register that latches the data serially output from 17-7 in 4-bit units (can be omitted in low-resolution, low-speed systems), 62 is a 2-port memory 17-0~
A 3-bit chip designation counter (memory chip) that designates the current display target data output source memory (memory chip) among l7-7.
CNTR). The counter 62 loads three bits of X4 to x2 of the memory address output from the multiplexer 48 in the address control circuit 16 at the start of a data transfer memory cycle, and counts up, for example, eight times in each memory cycle. It's becoming a sea urchin. 63 is a 2-port memory 17-0~ latched in the register 61
One of the 4-bit output data from 17-7 is sent to counter 6.
A multiplexer 64 with 8 outputs and 1 output is selected according to the count value of 2, and 64 converts the 4-bit data selectively output from the multiplexer 63 into serial data and outputs it to the look-up table (LUT) 20 shown in FIG. This is a 4-bit shift register (SR).

Next, the operation of one embodiment of the present invention will be explained.

First, normal background display will be explained. C
PU11 is a register 31.3 in the address control circuit 16.
2, memory start coordinate BMx via system bus 12
, BMy are set, and the register 45 is reset. When the register 45 is in the reset state, the window detection signal WON is kept at "0" by the window detection circuit 46. In this case, the multiplexer 47 is a memory address counter 41.4 for background display.
Select only the address indicated by 2. A counter 41 presets the contents of the register 31 for each horizontal retrace, and a counter 42 presets the contents of the register 32 for each vertical retrace. The window detection circuit 46 converts the data once for each horizontal flyback and sets the transmission signal DT to "1". Thereby, the multiplexer 48 selects the background display address (display address) output from the multiplexer 47.

Three bits X4 to X2 of the display address selected from the multiplexer 48 and the window detection circuit 4
The data transfer signal DT from 6 is supplied to the mask generation circuit 53 in the address conversion circuit 49.

The mask generation circuit 53 outputs mask selection signals SO to S7 according to the logic shown in FIG. 7 in accordance with the combination of the logical values of X4 to X2 and DT. That is, in the case of DT-0, the mask generation circuit 53 sets all mask selection signals SO to S7 to "0" regardless of X4 to X2. On the other hand, DT=0
In this case, if the value i indicated by X4 to is the mask selection signal SO
-S7 are all set to "0". On the other hand, if i is 1 or more, that is, if data is transferred from a position that is not a word boundary within a 32-bit area, the mask generation circuit 53 sets the mask selection signal SO~51-1 to "1". , sets the mask selection signal 5t-S7 to "0".

If the mask selection signals SO to S7 from the mask generation circuit 53 are "0", the multiplexers 52-0 to 52-7 select xlO-x5 from among the display addresses selected from the multiplexer 48, and set them to "1". ”, adder 5
I selects the value obtained by adding 1 to xlO-x5 (that is, the value obtained by adding 1 to the lower 6 bits of the column address of the corresponding 2-port memory). Multiplexer 52-0 to 52-7
The upper part of the selected output data (6 bits) from the multiplexer 48 includes the display address yt,
Two bits of yo are added. The data to which yi and yo are added and y9 to yO of the display addresses selected from the multiplexer 48 are the 2-port memory 17
-0 to 17-7 are switched and output from multiplexers 54-0 to 54-7 as column addresses and row addresses, respectively. As a result, when the value i indicated by X4 to
This is the next column position, and it is possible to output in 32-bit units from a position that is not on a word boundary. Note that the mask selection signal S
Since 7 is always "0", multiplexer 52-7 always receives xl from multiplexer 48.

~Select X5. Therefore, multiplexer 52-
7 can be omitted.

The data transfer signal DT from the window detection circuit 46 is also supplied to a memory timing circuit (not shown). This memory timing circuit responds to the data transfer signal DT times the signal.
Frame memory 17 in synchronization with memory clock MCK
It performs a data transfer cycle for the 2-port memories 17-0 to 17-7, and notifies the drawing circuit 13 or CPU II that random access is prohibited.

Two-port memories 17-0 to 17-7 are addressed by row and column addresses switched and output from multiplexers 54-0 to 54-7. As a result, 4 x 256 pixels in each specified row of 2-port memory 17-0 to 17-7
A data transfer cycle (in which bits are loaded into each shift register (not shown) in the memory 17-0 to 17-7)
A data transfer cycle of the memory is performed, and then the bits of the designated column (4 bits) are sequentially output serially in synchronization with, for example, the memory clock MCK. Each 4-bit serial output data from the two-port memories 17-0 to 17-7 is written to the register 61 in synchronization with the serial output operation. On the other hand, the counter 62 has
Of the display addresses selected from the multiplexer 48, X4 to X2 are loaded simultaneously with the latch operation of the register 61 in the memory cycle (data transfer memory cycle) of DT-1. X4 to X2 indicate the memory number (#i) of the two-port memory 17-1 to which bits are assigned to the memory address (in this example, memory coordinates for background display) selected by the multiplexer 48. The counter 62 performs a count-up operation eight times in each memory cycle.

The multiplexer 63 has the 2 latched in the register 61.
Among the 4-bit output data from each of the port memories 17-0 to 17-7, the output data from the 2-port memory with the memory number (#i) indicated by the count value of the counter 62 is selected. As a result, the multiplexer 63 outputs data sequentially in 4-bit units from the 2-port memories 17-0 to 17-7 with memory numbers #i, #i+l, . . .
#7. The selections are repeatedly output in the order of #0...#i-1. The 4-bit selected output data from multiplexer 63 is converted into serial data by shift register 64. Serial output data from the shift register 64 is supplied to the lookup table 20 and output to the CRT monitor 2.
The screen is displayed on the second screen space SS.

The above operation will be explained in more detail. For example, address 12 (0th
It is assumed that the data is to be displayed from the memory coordinates of the 12th row and 12th column. In this case, X4 to X2 are "3" and this value is loaded into the counter 62, so the data sequentially output in 4-bit units from the 2-port memories 17-0 to 17-7 is stored at memory number #3. ．． #4...#7. #0. #
1. The signals are selectively output from the repeat multiplexer 63 in the order of #2.

Also, if the value of X4~X2 is "3", memory number #0~
The column addresses of #2 2-port memories 17-0 to 17-2 are increased by 1 to those of the other 2-port memories 17-3 to 17-7. Therefore, the output data (32 bits) from the shift register 64 in each memory cycle is transferred from the 2-port memory 17-3 to the 4-bit address 12 of the frame memory space FMS.
The bit is located on the leftmost side, and the following 2-port memory 17-
4 bits from the same row 1 column position of 4 to 17-7 = 25-, and 2-port memory 17-0 to 17
The order is 4 bits from the position one column after -2, and the display can be performed correctly from address 12.

Next, window display will be explained with reference to the timing chart of FIG. 9. When window display is required, the CPU 11 uses the register 35 in the address control circuit 16.
．． 36 is the display start coordinate WS for the hardware window.
x, WSy, display end coordinates WEx, WEy for the hardware window are set in the registers 37 and 38, and the window enable register 45 is set.

When register 45 is set, window display is permitted.

In this case, the window detection circuit 46 detects that the X coordinate of the display scan position indicated by the scan counter 40 is
．． It is within the y-direction boundary of the window indicated by 38,
And X of the display scan position indicated by the scan counter 39
The window detection signal WON is set to 1'' during a memory cycle whose coordinates coincide with the left boundary of the window indicated by the register 35 and a memory cycle whose coordinates coincide with the right boundary of the window indicated by the register 37. Furthermore, the window detection circuit 46 A memory cycle in which the value of the counter 39 matches the value of the register 35, and the scan counter 3
In the next memory cycle after the memory cycle in which the value of 9 matches the value of the register 37, the data transfer signal DT is set to "1".

Window detection signal WO from window detection circuit 46
When N is "1", the multiplexer 47 selects the window display memory address indicated by the memory address counters 43 and 44. The display address (in this case, the hardware window display address) selectively output from the multiplexer 47 is selectively output to the address conversion circuit 49 by the multiplexer 48 when the data transfer signal DT from the window detection circuit 46 is 1''. Then, in the same address conversion circuit 49, the 2-port memories 17-0 to 17-0 are
It is converted into an address every 17-7. 2 port memory 1
7-0 to 17-7 are addressed by the address from the address conversion circuit 49 when DT=1.

As a result, the 4x256 bits in each specified row of the 2-port memories 17-0 to 17-7 are
The data is loaded into each shift register (not shown) in the memory, and then serially output in synchronization with the memory clock MCI starting with the bits (4 bits) of the designated column. Assuming that the value of X4 to X2 of the address selected from the multiplexer 48 is i, the serial output data of each 4 bits from the 2-port memories 17-0 to 17-7 are as follows, as in the case of the background display described above. Memory number #i, #i
+1...#7. It is repeatedly switched and output in the order of #O...#i-1. This causes the memory contents of the window area to be displayed.

In the memory cycle following the cycle in which the value of the scan counter 39 matches the value of the register 37, the data transfer signal DT becomes "1" as described above.

At this time, the window detection signal WON is returned to 0''. In the cycle when DT=1.WON=O, the address for background display indicated by the memory address counters 41 and 42 is selectively stored in the address conversion circuit 49. is supplied, and the background display described above is resumed.

As described above, according to this embodiment, the frame memory 17 performs background display and window display.
The X coordinate (display start coordinate) of (frame memory space FMS) can be specified in detail up to a multiple of 4. Note that the display start X coordinate can be specified in units of one dot for both background and window display.

The above description has been about a bitmap display device, but the present invention is also applicable to bitmap image processing devices that have a frame memory and cut out and output the contents of an arbitrary rectangular area within the memory, such as a laser printer or an electrostatic plotter device. It can also be applied to devices.

[Effects of the Invention] As detailed above, according to the present invention, a hardware window using 2-port memory can be realized.
Transfer speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an address control circuit directly related to the present invention, FIG. 2 is a block diagram of a bitmap display device equipped with the address control circuit of FIG. 1, and FIG. Figures 4(a) and 4(b) are diagrams explaining the concept of hardware windows.
Figure 5 is a diagram explaining the memory configuration of the frame memory shown in Figure 5. Figure 5 is a diagram explaining the relationship between the addresses of the frame memory and the addresses of the 2-port memory that constitutes the frame memory. Figure 6 is the address shown in Figure 1. Figure 7 is a block diagram of the conversion circuit; Figure 7 is a diagram showing the input/output logic of the mask generation circuit shown in Figure 6; Figure 8 is a block diagram of the shift register circuit shown in Figure 2; Figure 9 is the hardware. 5 is a timing chart for explaining an operation when displaying a window. 11...CPU, 1G...Address control circuit, 17
...Frame memory, 17-0 to 17-7...2 port memory, 19...Shift register circuit, 22...
・CRT monitor, 46...Window detection circuit, 47
．． 48.52-0~52-7°54-0~54-7.
! ...Multiplexer (MUX), 49...Address conversion circuit, 51...Adder, 53...Mask generation circuit, 62...Counter (CNTR), 64...
Shift register (SR). Applicant's agent Patent attorney Takehiko Suzue = 31 -

Claims (1)

[Claims] A frame memory for storing image data having p 2-port memories of l bits x m (columns) x n (rows),
Each row of the two-dimensional memory space is divided into l/p bit units, and each divided area is divided into p equal l-bit areas,
A frame memory to which l bits of each address position of the 2-port memory are allocated in a fixed order, a window detection circuit that detects the window position, and a background address and a window address are switched according to the detection result of this window detection circuit. a first multiplexer; a second multiplexer that switches between the address output from the first multiplexer and the drawing address according to the detection result of the window detection circuit; 2 allocated to each l bit obtained by dividing consecutive l p bits of data from a bit position in the memory space into p equal parts.
An address conversion circuit that generates the address of the port memory for each 2-port memory, and an address generated from this address conversion circuit for each 2-port memory, which is serially output from each 2-port memory in l bit units. a shift register circuit that sequentially selects data from the output data from the two-port memory to which the address output from the second multiplexer is assigned and converts the data into serial data; A bitmap image processing device characterized by outputting an image using serial data.