GB2216759A

GB2216759A - Windowed display including characters

Info

Publication number: GB2216759A
Application number: GB8905935A
Authority: GB
Inventors: Keiji Ihara; Masashi Kawamoto
Original assignee: Victor Company of Japan Ltd; Nippon Victor KK
Current assignee: Victor Company of Japan Ltd; Nippon Victor KK
Priority date: 1988-03-15
Filing date: 1989-03-15
Publication date: 1989-10-11
Anticipated expiration: 2009-03-15
Also published as: DE3908503A1; GB2216759B; KR920005607B1; KR890015113A; JPH01233483A; DE3908503C2; GB8905935D0

Description

r.' c.

22 16 7 5 9 1 TITLE OF THE INVENTION CHARACTER DISPLAY APPARATUS BACKGROUND OF THE INVENTION

This invention relates to a character display apparatus such as an output terminal display apparatus of a computer system.

Computer systems generally have a character display apparatus. In some computer systems, during a multi-window display mode of operation, a plurality of different pictures corresponding to respective different tasks are indicated on a common screen of a display apparatus. Such a multi-window display operation is performed through a software or a program of instructions given to a main processing section of the computer system. Accordingly, the multi-window display operation increases an operation load to the main processing section of the computer system. The increase in the operation load causes a slowdown of the execution of tasks including the multi-window display operation. In a slow multi-window display operation, windows tends to be controlled at inadequate speeds. SUMMARY OF THE INVENTION

It is an object of this invention to provide a character display apparatus which performs a quick and smooth multi-window display operation.

A character display apparatus of this invention 1 1 includes a control circuit. A memory has sections corresponding to respective logical pictures. The memory sections store display data included in the respective logical pictures. A character generator connected to the memory generates a signal representative of a character in accordance with a signal outputted from the memory. A display device has a physical display screen. A display circuitconnected between the character generator and the display device drives the display device in accordance with the character signal from the character generator. A control circuit includes a set of registers for holding preset addresses denoting physical display start and end points in a row direction, physical display start and end points in a column direction, a logic display start point in a row direction, and a logic display start point in a column direction for each of windows. The control circuit includes a device for incrementing addresses from said preset addresses. The control circuit controls a transfer of the display data from the memory to the character generator in accordance with said preset addresses and the incremented addresses and allows at least one window to be taken out from the logical pictures and be actually displayed on the physical display screen at a position determined by the preset addresses.

1 BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of a character display apparatus according to an embodiment of this invention.

Fig. 2 is a block diagram of the display control circuit of Fig. 1.

Fig. 3M is a front view of a display screen in the embodiment of Fig. 1.

Fig. MB) is an enlarged view of a portion of Fig. 3(A).

Fig. 4 is a diagram showing raster number signals in the embodiment of Fig. 1.

Fig. 5 is a diagram showing the display screen, a window, and related signals in the embodiment of Fig. 1.

Fig. 6 is a block diagram of a portion of the window control circuit of Fig. 2.

Fig. 7 is a block diagram of another portion of the window control circuit of Fig. 2.

Fig. 8(A) is a front view of the display screen which indicates windows.

Pigs. 8(B)-8(D) are diagrams showing the waveforms of various signals which occur during a period where the display screen is scanned along the line I-I of Fig. 8(A).

Fig. 9W is a diagram showing the arrangement of physical memories.

Fig. 9(B) is a diagram of logic display screens i i i corresponding to the physical memories of Fig. 9M.

Fig. 10 is a diagram of a portion of the display control cirucuite the display screen, and the states of the column window signal and the row window signal of the 5 embodiment of Fig. 1.

Fig. 11 is a timing diagram of various signals in the embodiment of Fig. 1.

Fig. 12 is a diagram showing a multi-window display operation in the embodiment of Fig. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Firstly, a brief description will be made on a multi-window display operation performed by a character display apparatus of an embodiment of this invention. As shown in Fig. 12, logical pictures "111-114" are prepared in memories. The logical picture is a phantom picture from which a window of picture is produced. A rectangular portion 'W' of the logical picture 11111, a rectangular portion "B" of the logical picture 11211, a rectangular portion "C" of the logical picture 1'311, and a rectangular portion "D" of the logical picture H411 are actually indicated on a screen 1 in the form of windows W1, W2, W3, and W4 respectively. The screen 1 is also referred to as the physical display screen on which a window of picture is actually displayed as a physical display.

In regions where at least two of the windows Wl-W4 - 5 overlap, selected one of the windows Wl-W4 are actually fully displayed and overshadows the other behind it in accordance with a priority instruction inputted via a keyboard. In the case of Fig. 12, the window W3 has the highest priority and the window W4 has the lowest priority. The window W2 has a higher priority than the window W1.

The position of the portion "A" relative to the logical picture "111 is varied accordingly by an instruction inputted via the keyboard. The size of the portion 'W' is also varied accordingly by an instruction inputted via the keyboard. Since the portion "A" is rectangular, the position of the portion onA" relative to the logical picture nln and the size of the portion 'W' are determined by directing the positions of the left upper corner and the right lower corner of the portion "All. The other portions nB", nC", and 11D11 can be varied similarly.

The position of the window Wl relative to the screen 1 is moved by an instruction inputted via the keyboard. The movement of the window Wl ralative to the screen 1 can be performed independently of the position of the portion "All relative to the logical picture "l". Accordingly, the portion 'W' can ramain unchanged during the movement of the window W1. The variation or positional control of the portion "All relative to the logical picture 111" can be performed independently of the position of the window Wl relative to the screen 1. Accordingly, the window Wl can remain stationary during the positional control of the portion "A" relative to the logical picture "1", that is, during a scrolling process performed on the prelimiary 5 picture "1".

As shown in Fig. 3(A), the screen 1 has a two-dimensional arrangement of rectangular or square unit areas 2 each corresponding to one character. The position of each of these unit areas 2 is denoted by a display column number xp and a display row number yp. As shown in Fig. 3(B), each of these unit areas 2 has an arrangement of scanning line segments or linear raster segments extending horizontally and are identified by a scanning line number or a raster number RA which varies from 0 to a given number RMAX.

With reference to Fig. 1, a character display apparatus 10 includes a display control circuit 11. The display control circuit 11, a display memory 12, a central processing unit (CPU) 16, a read only memory (ROM) 17, a random access memory (RAM) 18, and an interface circuit 19 are mutually connected via a bus-9. The display memory 12 is preferably composed of a dual-port dynamic random access memory 12. The display control circuit 11 outputs signals DAO-DA7, signals RAS and CAS, and signals WE and OE to the display memory 12. The signals DAO-DA7 represent display j i 1 i i 1 i address denoting a storage location of a segment of the display memory 12 into and from which the display data are written or read. The signals RAS and CAS represent a row address and a column address strobes. The signal WE corresponds a write enable signal which allows the data writing into the display memory 12. The signal OE corresponds an output enable signal which allows the data transfer from the display memory 12.

A clock generator 13 feeds a display clock signal to the display control circuit 11 and the display memory 12. The display clock signal contains pulses which occur at a given period corresponding to an interval of one character along a scanning line on a screen. A known character generator 14 generates a signal representative of a character in accordance with an output signal from the display memory 12. For example, the character generator 14 is composed of a ROM. The character generator 14 is controlled by a raster number signal outputted from the display control circuit 11. A known display circuit 15 drives a display 15A in accordance with the character signal from the character generator 14 so that a character represented by the character signal can be displayed on a screen of the display 15A. The display circuit 15 is controlled by a cursor signal, a display sync signal, and a display timing signal outputted from the display control i i circuit 11. For example, the display 15A is composed of a cathode ray tube (CRT).

The devices 11-19 within the character display apparatus 10 are powered by a power supply 10A. It should be noted that the connections of these devices to the power supply 10A is omitted from Fig. 1. Characters to be displayed, instructions to be executed, and other information can be inputted into the character display apparatus 10 via a keyboard 19A 'connected to the interface circuit 19. In general, the character display apparatus 10 is connected to an external host computer 10B via the interface circuit 19.

As will be made clear hereafter, multi-window display operation is entirely controlled by the display control circuit 11. The display memory 12 is basically divided into sections which correspond to respective logical pictures or respective windows and which hold display data for the respective windows. In principle, the display data of the respective windows relate to different tasks executed by the host computer 10B respectively. For example, the display memory 12 has four sections corresponding to four windows.

A program stored in the ROM 17 enables the CPU 16 to write and read display data into and from the display memory 12 via the bus 9 and the control circuit 11.The f display data are bidirectionally transmitted between the display memory 12 and the host computer 10B through the interface circuit 19.

As shown in Fig. 2, the display control circuit 11 includes a signal generator 21 which generates a display sync signal and a display timing signal on the basis of the display clock signal in a known way. Specifically, the signal generator 21 includes counters counting the pulses of the display clock signal and generating the display sync signal and the display timing signal. As described previously, the display sync signal and the display timing signal are fed to the display circuit 15.

A signal generator 22 connected to the signal generator 21 generates a signal RA representative of a raster number corresponding to a currently scanned raster segment, a signal xp representative of a currently scanned column, and a signal yp representative of a currently scanned row on the basis of the display clock signal and the output signals from the signal generator 21.

Specifically, the signal generator 22 includes counters counting the pulses of the display clock signal and the output signals from the signal generator 21 and generating the raster number signal RA, the display column signal xp, and the display row signal yp. The raster number signal RA, the display column signal xp, and the display row signal yp are simply referred to as the raster number RA, the display column Xpr and the display row yp respectively. The display column xp and the display row yp denote acurrently scanned unit area of the screen. The raster -9 number RA denotes a currently scanned raster segment within the unit area of the screen which is denoted by the display column xp and the display row yp.

A register 23 connected to the bus 9 holds data setting the regions of windows, that is, the positions and sizes of windows with respect to the physical screen. The register 23 also holds data setting the regions of windows, that is, the positions and sizes of windows with respect to the logical pictures. The register 23 further holds data setting the priorities of windows in a region of the screen where at least two windows overlap. In addition, the register holds data determining whether or not each window is actually indicated on the screen. These window setting and determining data are inputted into the character display apparatus 10 by a command of the keyboard 19A and are transmitted to the register 23 via the CPU 16.

A signal generator 24 generates a signal Rs representative of a raster number in respect of each window on the basis of the display sync signal and output signals from the register 23 and a window control circuit 25.

Specifically, the signal generator 24 includes counters 1 which correspond to the respective windows and which count the pulses of the display sync signal to generate the respective window raster number signals Rs. The counters of the signal generator 24 are controlled by the output signals from the register 23 and the window control circuit 25. The window raster number signal Rs is simply referred to as the window raster number Rs.

A signal selector or a data selector 27 selects one of the raster number RA and the window raster number Rs in accordance with a window selection signal WS fed from the window control circuit 25. The raster number selected by the selector 27 is outputted to the character generator 14. In the case where there are three windows, the raster numbers Rl, R2, and R3 are outputted from the selector 27.

The raster numbers Rl, R2, and R3 correspond to the raster numbers Rs for the respective windows, that is, the scroll numbers set in the register 23. Each of the raster numbers Rl, R2, and R3 is in the range of 0 to RMAX. As shown in Fig. 4, the raster numbers RA and RS vary in manners as the outputs of ring counters change. Specifically, the signal generator 22 includes a ring counter which generates the raster number RA by counting up the pulses of the display sync signal. When the raster number RA reaches the given number RMAX, a last raster signal LR is outputted from and the raster number RA is reset to 0. In addition, the signal generator 24 includes ring counters which correspond to the respective windows and which count up the pulses of the display sync signal to generate the respective window raster numbers Rs. As shown in Fig. 4, the window raster numbers Rs for the respective windows start from the respective scroll numbers Rl, R2, and R3 which are set in the register 23. When each of the window raster numbers Rs reaches the given number RMAX, the window raster number Rs is reset to 0.

The window control circuit 25 generates a signal representative of data of the position of a cursor on the basis of the display column xp and the display row yp. A data comparator 26 compares the cursor position data with the output data from the register 23 which represents the regions of windows. When the cursor position resides within one of the regions of the windows, the data comparator 26 outputs a cursor signal to the display circuit 15 so that a cursor is actually indicated on the screen 1. When the cursor position resides outside any of the regions of the windows, the data comparator 26 suspends the outputting of the cursor signal so that the cursor is not displayed on the screen 1.

As will be described hereinafter, the register 23 includes a section which holds data of the priorities of windows. The priorities of the windows relate to the display of the windows in a region where at least two of the windows overlap. The priority data are stored into the section of the register by a command of the keyboard 19A. The priority data can be changed by operations of the 5 keyboard 19A.

As will be made clear hereinafter, the window control circuit 25 executes significant part of the multi-window display operation.

A RAM interface (I/F) circuit 28 generates the signals RAS and CAS, and the signals WE and OE on the basis of outp ut signals from the window control circuit 25. As described previously, the signals RAS and CAS, and the signals WE and OE are fed to the display memory 12. The interface circuit 28 receives display address DAO-DA7 from the bus 9 and transmits them to the display memory 12.

As shown in Fig. 5, the unit area which is located at the left upper corner of the screen 1 is denoted by the column xp=O and the row yp=O. The unit area which is located at the right lower corner of the screen 1 is denoted by the column xp=xMAX and the row yp=yMAX. The column xp corresponds to an address of a unit area of the screen 1 in a column arrangement direction. The row yp corresponds to an address of a unit area of the screen 1 in a row arrangement direction. The unit area which is located at the left upper corner of a window W is denoted by the column xS and the row yS. The unit area which is located at the right lower corner of the window W is denoted by the column xE and the row yE. Since the window W is rectangulart the region of the window W is determined by the columns and rows xS, xE, yS, and yE. The column XS corresponds to a physical display start address of the window W in a column arrangement direction. The row yS corresponds to a physical display start address of the window W in a row arrangement direction. The column xE corresponds to a physical display end address of the window W in a column arrangement direction. The row yE corresponds to a physical display end address of the window W in a row arrangement direction. A column window signal X assumes a high level during a period corresponding to the column address range between xS and xE and assumes a low level during other periods. A row window signal Y assumes a high level during a period corresponding to the row address range between yS and yE and assumes a low level during other periods.

The physical display start addresses xS and yS of the window W, and the physical display end addresses xE and yE of the window W are given to the window control circuit 25 from the register 23. The addresses xS, yS, xE, and yE are changed by an instruction inputted by the keyboard 19A. Data comparators within the window control circuit 25 1 is - generate the column window signal X and the row window signal Y by comparing the column xp and the row yp with the window addresses xS,, yS,, xE, and yE.

Fig. 6 shows a portion of the window control circuit 25. As shown in Fig. 6, the window control circuit 25 includes an AND gate Al receiving a column window signal X1 and a row window signal Y1 for a window Wl, and an ON/OFF signal representing whether or not the window Wl is required to be displayed on the screen 1. When the window W1 is required to be displayed on the screen 1, the ON/OFF signal of the window Wl assumes a high level and thus the AND gate Al is open so that the column window signal Xl and the row window signal Yl are outputted from the AND gate Al. When the window Wl is required not to be displayed on the screen 1, the ON/OFF signal of the window W1 assumes a low level and thus the AND gate Al is closed so that the column window signal Xl and the row window signal Yl are blocked by the AND gate Al. The output signal from the AND gate Al represents whether or not the portion of the screen 1 which corresponds to the window 1 is currently scanned. The ON/OFF signal of the window W1 is transmitted from the register 23 and is changed by operating the keyboard 19A. An AND gate A2 receives a column window signal X2 and a row window signal Y2 for a window W2, and an ONIOFF signal representing whether or not the window W2 is required to be displayed on the screen 1. The AND gate A2 operates in a manner similar to the AND gate Al. The ONIOFF signal of the window W2 is transmitted from the register 23 and is changed by operating the keyboard 19A. An AND gate A3 receives a column window signal X3 and a row window signal Y3 for a window W3, and an ONIOFF signal representing whether or not the window W3 is required to be diPlayed on the screen 1. The AND gate A3 operates in a manner similar to the AND gate Al. The ON/OFF signal of the window W3 is transmitted from the register 23 and is changed by operating the keyboard 19A. An AND gate A4 receives a column window signal X4 and a row window signal Y4 for a window W4, and an ON/OFF signal representing whether or not the window W4 is required to be displayed on the screen 1.

The AND gate A4 operates in a manner similar to the AND gate Al. The ONIOFF signal of the window W4 is transmitted from the register 23 and is changed by operating the keyboard 19A.

A priority section 31 of the register 23 holds data representing the priorities of the windows W1-W4. The priority data are changed by operating the keyboard 19A. A switch 32 connected between the AND gates Al-A4 and an encoder 33 controls the connections between the AND gates Al-A4 and the encoder 33 in accordance with the priority data fed from the register section 31. Specifically, the output signals from the AND gates which relate to the windows having the highest priority, the second highest priority, the second lowest priority, and the lowest priority are transmitted to a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal of the encoder 33, respectively.

The encoder 33 outputs signals representing the priorities of the windows and also representing whether or not the portions of the screen 1 which correspond to the windows are currently scanned. These output signals from the encoder 33 are applied to a comparator 34. The encoder 33 also generates a signal WERA which represents whether or not at least one of the windows are currently scanned. The comparator 34 compares the output signals from the encoder 33 in accordance with the priority data fed from the priority section 31 and thereby generates signals (WSO, WS1,...) which select the highest- priority window in a region of the screen 1 where at least two windows overlap.

Fig. 7 shows another portion of the window control circuit 25. As shown in Fig. 7, the window control circuit 25 includes flip-flops 25A and 25B whose clock input terminals receive the display clock signal. Also, the clock input terminals of flip-flops (FFO, FF1,... ) receive the display clock signal. The signal WERA is applied to one input terminal of a NAND gate 25C, the data input - 181- terminal of the flip-flop 25A, and one input terminal of a NAND gate 25D. The NAND gate 25C is of the type having inverters at its input terminals. The inverted output signal from the flip-flop 25A is applied to the other input terminals of the NAND gates 25C and 25D. The output terminal of the NAND gate 25C is connected to the data input terminal of the flip-flop 25B via an AND gate 25E. The output terminal of the NAND gate 25D is connected to the data input terminal of the flip-flop 25B via an OR gate 10 25F and the AND gate 25E. The window selection signal WSO is applied to one input terminal of an exclusive OR gate XORO and the data input terminal of the flip-flop FFO. The non-inverted output signal from the flip-flop FFO is applied to the 15 other input terminal of the exclusive OR gate XORO. The output signal from the exclusive OR gate XORO is applied to a first input terminal of a NOR gate 25G. The window selection signal WS1 is applied to one input terminal of an exclusive OR gate X0R1 and the data input terminal of the 20 flip-flop FF1. The non-inverted output signal from the flip-flop FF1 is applied to the other input terminal of the exclusive OR gate X0Rl. The output signal from the exclusive OR gate X0R1 is applied to a second input terminal of a NOR gate 25G. The output terminal of the NOR 25 gate 25G is connected to the flip-flop 25B via the OR gate 25F and the AND gate 25E.

The flip-flop 25B generates a change requirement signal CGRQ in accordance with the signal WERA and the window selection signals (WS1, WS2,...). As shown in Fig.

8, the change requirement signal CGRQ includes pulsesr each of which is generated during the signal WERA being a high level and upon a change of the window selection signals. Accordingly, each of the pulses CGRQ is generated when the scanning spot moves from a non-window portion into one of the windows Wl-W4 of the screen 1 or when the scanning spot moves from one of the windows Wl-W4 to another of the windows Wl-W4.

The row window signal Y and the column window signal X for each of the windows, the signal WERA, the window selection signals (WS1, WS2,...), and the change requirement signal CGRQ are outputted from the window control circuit 25 to the interface circuit 28 and are used in determining a row address signal RAS, a column address signal CAS, a write enable signal WE, and an output enable signal OE.

The display memory 12 includes a RAM section and a SAM (serial access memory) section in a manner similar to a conventional dual-port dynamic RAM. A set of data are simultaneously transferred from the RAM section to the SAM section. The set of data are serially read out from the i i j J SAM section in response to the display clock signal. The change requirement signal CGRQ is used as a trigger signal for the data transfer from the RAM section to the SAM section.

Fig. 9W shows an actual or physical internal arrangement of the display memory 12. As shown in Fig. g(A), the display memory 12 includes sub display memories (HM1, HM2,...) corresponding to the respective windows (Wl, W2, _). Address tables (AD1, AD2,...) are prepared for the respective sub display memories (HM1, HM2, _). Fig. 9(B) shows logical pictures (RG1, RG2,...) of the respective windows W1, W2,...) which correspond to the respective pairs of the sub display memories (HM1, HM2, and the address tables (AD1, AD2, _).

Each of the address tables (ADJ, AD2,.) have segments corresponding to respective rows of the related logical pictures (RG1, RG2, _). In each of the address tables (AD1, AD2,...), the first segment has address data denoting display information 11111 which is stored in the sub memory and which is located in the first row of the logical picture, and the first segment has address data denoting display information "2" which is stored in the sub memory and which is located in the second row of the logical picture. Similarly, the third segment to the end segment have address data denoting display information "P to -display information "E" which are stored in the sub memory and which are located in the third row to the end row of the logical picture.

Fig. 10 shows an internal structure of the RAM interface circuit 28. The RAM interface circuit 28 includes row table counters TC (only one of which is shown) of the respective windows. The row window signal Y is applied to the row table counter TC as a count enable signal. The row table counter TC counts the last raster signal LR of each row of the related window as a clock signal. The table counter TC receives a setting value representing a logic start row of the related window. The output values of the table counter TC correspond to the address values (the line value LN, the column value CN) of the address table of the address memory 12, the address values of the address table are read out and stored in the register 23 of the display control circuit 11 for each of the windows during a period immediately before the row is actually displayed on the display screen, that is, during a horizontal blanking period where the last raster signal LR remains logic I'l". The line value LN is directly used as a row address Ty for the data transfer from the RAM section to the SAM section of the display memory 12.

An adder 90 generates a value TxD by adding the column value CN and a signal representing a logic start 1 column of the related window. The output value TxD from the adder 90 is fed to a window column counter 95 as a setting value. The column window signal X is applied to the windowcolumn counter 95 as a count enable signal. The window column counter 95 counts the display clock as a clock signal. The window column counter 95 outputs a column address Tx for the data transfer from the RAMsection to the SAM section of the display memory 12.

Fig. 11 is a timing chart showing the operation of changes of the window display. Fig. ll(A) shows the display contents of the windows Wl and W2. Figs. ll(B) and ll(C) show data transfer addresses for the windows Wl and W2. The column addresses Txl and Tx2 are incremented in response to the display clock signal. Figs. ll(D), ll(E), and ll(P) show the change requirement signal CGRQ, the window selection signal WS, and the display clock signal respectively. The window display is changed by a trigger formed by the change requirement signal CGRQ. The display data supplied from the host computer 10B and stored in the RAM section of the display memory 12 are transferred to the SAM section thereof accor ding to the column address Tx and the row address Ty, then serially outputted from the SAM section to the character generator 14 in response to the display clock fed to the display memory 12. The character generator 14 converts the diplay data into corresponding font to allow the display circuit 15 driving the display 15A.

1

Claims

CLAIMS v 1. A character display apparatus comprising:

control circuit; memory having sections corresponding to respective logical pictures, the memory.sections storing display data ito be included in the respective lc> gical pictures; a character generator connected to the memory for generating a signal representative of a character in accordance with a signal outputted from the memory; display device having a physical display screen; display circuit connected between the character generator and the display device for driving the display device in accordance with the character signal from the character generator; wherein the control circuit comprises a set of registers for holding preset addresses denoting physical display start and end points in a row direction, physical display start and end points in a column direction, a logic display start point in a row direction, and a logic display start point in a column direction for each of windows; wherein the control circuit comprises means for incrementing addresses from said preset addresses; and wherein the control circuit is to control a transfer of the display data from the memory to the character generator in accordance with said preset addresses and the incremented addresses and, to allow at least one window to be taken out from.the logical pictures and be actually displayed on the physical display screen at a position determined by said 5 preset addresses.
2. The apparatus of claim 1 wherein the control circuit includes a register storing priority data which determines which of windows is selected and is actually displayed on the physical display screen in a region where the selected window overshadows other.
3. The apparatus of claim 1 or 2 further comprising means for changing the preset addresses.
4. A character display apparatus for use in combination with an external host computer, the apparatus comprising: a control circuit; a memory having sections corresponding to respective logical pictures, the memory sections storing display datato be included in the respective logical pictures, wherein the display data of the logical pictures relate to different tasks executed in the external host computer respectively; means for controlling a transfer of the display data between the memory and the external host computer; RI 0 a character generator connected to the memory for generating a signal representative of a character in accordance with a signal outputted from the memory; display device having a physical display screen; display circuit connected between the character generator and the display device for driving the display device in accordance with the character signal from the character generator; wherein the control circuit comprises a set of registers for holding preset addresses denoting physical display start and end points in a row direction, physical display start and end points in a column direction, a logic display start point in a row direction, and a logic display start point in a column direction for each of windows; wherein the control circuit comprises means for incrementing addresses from said preset addresses; wherein the control circuit is to-control a transfer of the display data from the memory to the character generator in accordance with said preset addresses and the incremented addresses and to allow at least one window to be cut from the logic display screens and be actually indicated on the physical display screen at a position determined by said preset addresses; and wherein the control circuit can perform window control without assistance from the external host computer.

1 i 1
5. A character display apparatus constructed and arranged substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
6. A combination of a host computer and a character display apparatus according to any preceding claim.

Pubjished 1989 atThe Patent Office, State House, 65!71 High Holborn, London WC1R 4T?. Further copiesmaybe obtainedfrom The Patent Office. Wes Branch, St Mary Cray, Orpington, Kent BR5 3RD. Printed by Multiplex techniques Itd, St Mary Cray, Kent, Con. 1/87 1