JP2507352B2 - Video system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a video system including an imaging unit and a recording unit, and more particularly to a field allocation configuration.

(Prior Art) Conventionally, a device for identifying an odd field and an even field of an interlaced video signal is Japanese Patent Publication No. 60-513015.
There are many publicly known examples including the field identification device disclosed in the publication. However, in consumer video systems,
There is no azimuth head or −azimuth head fixed so as to always record corresponding to either the even or odd field. Therefore, in the conventional video system, the + azimuth head and the −azimuth head are assigned to record either an even number field or an odd number field depending on the timing at which the operation is started, and the above-mentioned phase relationship determined once stops the drum motor. Alternatively, it continues until the input of the composite sync signal is stopped. But,
When either the drum motor is stopped or the composite sync signal is stopped, it is uncertain whether the + and-azimuth heads are assigned to record even or odd fields at the start of the next operation.

Therefore, when the short-time recording, the stop, and the short-time recording are repeatedly performed by the video system as described above to perform the joint recording and the reproduction, the +,-azimuth head and the even number,
Since the relationship between the odd fields is not uniformly determined, there is a disadvantage that the skew becomes conspicuous at the joint where the same field is repeated during reproduction and the screen becomes visually unacceptable.

(Problems to be Solved by the Invention) In the conventional video system, the relationship between the + and-azimuth heads and the even-numbered and odd-numbered fields is not uniformly determined. Therefore, when the signal recorded by continuous shooting is reproduced, the same field is repeated. There was a disadvantage that the skew was conspicuous at the joint and the screen was visually unacceptable. SUMMARY OF THE INVENTION Therefore, the present invention eliminates the above-mentioned drawbacks, and an object of the present invention is to provide a video system in which the relationship between the +,-azimuth heads and the even and odd fields can always be uniformly set.

[Structure of the Invention] (Means for Solving Problems) The present invention is an image pickup unit for outputting a video signal including a composite sync signal, which is initialized to output the video signal for a predetermined period. An image pickup unit that stops and then outputs an image signal sequentially from either even or odd field, and two video heads that are driven by a motor and that record the image signal from the image pickup unit and have different azimuth angles And a rotation phase signal generating means for generating a signal indicating a rotation phase of the rotation body, and a vertical synchronization signal of the image signal from the image pickup unit when oscillated at a vertical frequency. An oscillator controlled to oscillate in synchronization with the synchronization signal and an output of the oscillator.
Reference signal creating means for creating a reference signal based on a signal divided in half, and the motor so that the phases of both the reference signal and the output of the rotation phase signal generating means are compared to have a constant relationship. And a phase control unit for controlling the rotation phase of the recording unit, wherein the recording unit further starts the operation of the recording unit at a recording start timing, and outputs the reference signal and the output of the rotation phase signal generation unit. When the phase becomes a predetermined relationship, it is detected to initialize the imaging unit,
A recording unit having a control unit for controlling to specify whether the vertical synchronizing signal of the video signal first supplied to the oscillator after the predetermined period is of an odd field or an even field. Consists of

(Operation) In the video system of the present invention, the control means is
When the video system operates and the drum servo system is servo-locked, a reset signal is output to the imaging unit after a predetermined time. As a result, the image pickup unit is initialized, and after a predetermined time from this initialization time, the image pickup unit is set to an even number together with the composite sync signal.
A recording video signal in which the fields are alternately changed from the recording video signal of one of the odd fields is output to the recording unit. As a result, the drum servo system rotates the drum while maintaining a constant phase relationship with the even and odd fields.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the image pickup section of the video system of the present invention. The image pickup unit is the reset signal generation unit 1
And the composite sync signal generator 2. The reset signal generating unit 1 delays the servo lock signal 100 of the drum motor for a predetermined time to generate a reset signal 200 for resetting the composite synchronizing signal generating unit 2, and the mono-multi (MM) 11, 12
Consists of The composite sync signal generator 2 passes the output signals of the frequency dividers 21 to 28 and the 1/2 frequency divider 24, which sequentially divide the clock 300 of 14.32 MHZ, at a fixed timing to generate the horizontal sync frequency signal 400. The output signal of the output gate 29, 1/7 frequency divider 28 is passed at a fixed timing, and the vertical sync frequency signal 50
A gate 30 for outputting 0, a shift register 31 for producing a plurality of signals obtained by delaying the horizontal synchronization frequency signal 400 appropriately little by little, and a shift for producing a plurality of signals obtained by appropriately delaying the vertical synchronization frequency signal 500 by a little little A horizontal sync cutout circuit 33 that cuts out a signal having a predetermined pulse width from the register 32 and the shift register 31 to obtain a horizontal sync signal 600, the shift register 3
Vertical sync signal 700
And a waveform synthesizing circuit 35 for synthesizing the horizontal synchronizing signal 600 and the vertical synchronizing signal 700 to produce a composite synchronizing signal 800.

FIG. 2 is a block diagram showing an embodiment of the recording unit of the video system of the present invention. 51 is a sync separation circuit for separating the vertical sync signal 710 from the input composite video signal 900, 52
Is a recording signal processing circuit for processing the composite video signal 900 into a recording video signal, 53 and 54 are for recording the recording video signal on a tape, + azimuth head, −azimuth head, and 55 is a vertical for generating a vertical reference signal 1000. Reference oscillating circuit, 56 is an internal reference signal generating circuit that generates an internal reference signal 1100 from the vertical reference signal 1000, 57 is a PG pulse generating circuit that generates a PG pulse signal corresponding to the phase of the drum motor 66, and 58 is the PG pulse An amplification delay circuit that outputs a phase detection signal 1200 that is generated by delaying the signal by amplifying it once per drum rotation. 59 compares the phases of the internal reference signal 1100 and the phase detection signal 1200, and the phase difference signal of these signals. Is a low-pass filter (LP) for removing unnecessary components from the phase difference signal.
F), 61 is an FG pulse generation circuit that outputs an FG pulse signal corresponding to the speed of the drum motor 66, 62 is an amplification circuit that amplifies the FG pulse, and 63 is a speed detection signal that frequency-detects the amplified FG pulse. 1300 is a frequency discriminating circuit, 64 is an adding circuit for adding a phase difference signal obtained from the speed detection signal 1300 and the LPF 60 to generate a motor speed phase control signal, and 65 is a speed of the drum motor 66 based on the motor speed phase control signal. And this drum motor so that the phase becomes a predetermined one.
A motor drive circuit that drives 66, and 66 is a drum motor that rotates a drum to which the heads 53 and 54 are attached.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. When the video system is started to start recording, each circuit of the recording unit starts operating,
The drum motor 66 is also driven, and its rotation phase stabilizes in a predetermined phase relationship with the internal reference signal 1100 after a predetermined time elapses. As a result, the servo lock signal 100 shown in FIG. 3 (A) becomes a high level at the timing of time t ₀ and is input to the terminal A of the mono-multi 11 of the reset signal generation unit 1, so that the terminal of the mono-multi 11 is the same. A high level signal 110 shown in FIG. 3 (B) is output from Q. Since this signal 110 is input to the mono-multi 12, a low-level reset signal 200 is output from the mono-multi 12 after T ₁ hours (time t ₁ ) from the time t ₀ . By the way, the composite sync signal generator 2
Then, when the clock 300 of 14.32MHZ is input, this clock 300 is sequentially applied to the frequency dividers 21, 22, 23, 24 by 1/7, 1/5, 1/3, 1/2.
It is divided into and input to the gate 29. Since the gate 29 is opened / closed by the frequency division signals of the frequency divider 21 and the frequency divider 23, the gate 29 eventually outputs the horizontal synchronizing frequency signal 400. The shift register 31 uses the horizontal sync frequency signal 40
Generate multiple signals by delaying 0 by an appropriate small amount. The horizontal sync cutout circuit 33 cuts out a signal from the shift register 31 so as to obtain a signal having an appropriate pulse width, and outputs this as a horizontal sync signal 600 to the waveform synthesis circuit 35. At the same time as the above operation, the clock 300 is divided by the frequency divider 21, 22, 23, 25, 26, 27, 28.
Are sequentially divided by 1/7, 1/5, 1/3, 1/5, 1/5, 1/3, 1/7 and input to the gate 30. The gate 30 is opened / closed by the frequency-divided signal of the frequency divider 23, and the gate 30 eventually outputs the vertical synchronizing frequency signal 500. The shift register 32 appropriately delays the vertical synchronizing frequency signal 500 little by little to generate a plurality of signals. The vertical sync cutout circuit 34 cuts out a signal from the shift register 32 so as to obtain a signal having an appropriate pulse width, and uses this as a vertical sync signal 700 as a waveform synthesis circuit 35.
Output to. The waveform synthesizing circuit 35 inputs the horizontal sync signal.
600 and the vertical synchronizing signal 700 are combined to output a composite synchronizing signal 800. The composite sync signal 800 is combined with a video signal obtained by controlling an image pickup circuit (not shown) to form a composite video signal 900, which is sent to the recording unit side.

Composite sync signal creation unit 2 performing the above operation
Reset signal 20 generated by the reset signal generator 1
When 0 is input at time t ₁ shown in FIG. 3 (C), the frequency divider 2
1 to 28, the gates 29 and 30, and the shift registers 31 and 32 are reset, and as shown in FIG. 3D, T ₂ hours after this reset, the composite sync signal 80 is again output from the odd field O.
0 is output. Therefore, as shown in FIG. 3 (E), the vertical synchronization signal 700 included in the composite synchronization signal 800 output from the composite synchronization signal generation unit 2 has the field shown in FIG. 3 (D) after the reset period T ₂ . It is output again from the odd field of the index. It should be noted that, when the image pickup unit is reset, it generates the video signal of the odd field after a fixed time (T ₂ hours), and thereafter outputs the video signal in the order of the odd field, the even field, and the odd field.

Here, the operation of the recording unit shown in FIG. 2 will be described. The composite video signal 900 input from the image pickup section becomes a recording video signal by the recording signal processing circuit 52, and this recording video signal is recorded on the tape (not shown) by the + and-azimuth heads 53 and 54. On the other hand, the sync separation circuit 51 separates the vertical sync signal 710 from the input composite video signal 900 and outputs it to the vertical sync reference circuit 55. The vertical synchronization reference circuit 55 synchronizes with the input vertical synchronization signal 710 and outputs the vertical reference signal 1000 shown in FIG.
When the vertical synchronizing signal 710 is not input, the vertical synchronizing signal 1000 is output to the internal reference signal generating circuit 56 by its own clock. The internal reference signal generation circuit 56 generates an internal reference signal 1100 as shown in FIG. 3 (I) in synchronization with the input vertical reference signal 1000 and outputs it to the phase comparison circuit 59. On the other hand, the PG pulse generation circuit 57 is a drum motor 66.
The PG pulse corresponding to the phase of is generated. This PG pulse becomes the phase detection signal 1200 by the amplification delay circuit 58 and is input to the phase comparison circuit 59. Phase comparator 59 is an internal reference signal
One of the edges of 1100, for example, the rising edge and the phase detection signal 1200 are compared to generate a phase difference signal. Known techniques can be applied to the phase comparison, for example, the rising edge of the internal reference signal 1100 and the phase detection signal.
The time difference between 1200s may be obtained by counting a clock of a predetermined frequency, and the count value may be PWM-modulated to obtain a phase difference signal. This phase difference signal is PWM by LPF60
The carrier component of is removed and then input to the adder circuit 64. On the other hand, the FG pulse generation circuit 61 generates an FG pulse signal corresponding to the speed of the drum motor 66. This FG pulse signal is amplified by the amplifier circuit 62 and then output as the speed detection signal 1300 by the frequency discriminating circuit 63 to the adding circuit 64.
The adder circuit 64 adds the phase difference signal to the speed detection signal 1300 to generate a motor speed phase control signal, and outputs this to the motor drive circuit 65. The motor drive circuit 65 controls the speed and phase of the drum motor 66 based on the input motor speed phase control signal so that the drum motor 66 is driven by a drum (not shown) to which the + and-azimuth heads 53 and 54 are attached. The rotation phase of) is controlled to be constant.

By the way, as shown in FIG. 3F, the drum motor 66 shown in FIG. 2 is reset when the composite synchronizing signal generator 2 is reset.
Servo system is in playback mode. This is because the composite sync signal 800 output from the composite sync signal generator 2 at the time of resetting becomes unstable and the operation of the servo system becomes unstable, so that the phase of the servo system does not depend on the composite sync signal 800. This is because the fixed reproduction mode is selected. This reproduction mode becomes the recording mode after a fixed time has elapsed since the reset of the composite sync signal generator 2. Therefore, when the vertical sync signal 710 is input from the sync separation circuit 51 to the vertical sync oscillator circuit 55 shown in FIG. 2 at time t ₃ shown in FIG. As shown, the vertical reference signal 1000 is generated in synchronization with the vertical synchronizing signal 710.

The internal reference signal generation circuit 56 receives the input vertical reference signal 10
An internal reference signal 1100 shown in FIG. 3 (I) is generated in synchronization with 00. Therefore, when the vertical reference oscillation circuit 55 is reset at time t _3, Figure 3 after a predetermined time from this point (I)
As shown in FIG.
00 is newly generated. After all, if the time T ₁ from the rising time t ₀ of the servo lock signal in FIG. 3 (A) to the falling edge of the reset signal 200 in FIG. 3 (C) is determined, the time t ₃ is uniformly determined. . Therefore, the relationship between the odd field scanning timing of FIG. 3 (D) and the internal reference signal 1100, which is also determined by the time T _1, is uniformly determined, and the rising edge of this internal reference signal 1100 and its phase are synchronized. Since the relationship between the phase detection signal 1200 and the odd field scanning timing is also uniformly set, the phase relationship with the switching pulse shown in FIG. 3 (J) is also uniformly set. After all, after the reset signal 200 is generated, the video signal of the even field is always recorded on the tape by the + azimuth head 53, and the video signal of the odd field is always recorded on the tape by the −azimuth head 54.

FIG. 4 is a timing chart when the phase difference between the internal reference signal 1100 and the field index differs by 180 degrees from the case of FIG. 3. In this case, the + azimuth head 53 causes the video signal of the odd field to change to −azimuth head 54. Thus, the video signal of the even field is fixed so that it is always recorded on the tape. The difference between the operations shown in the timing chart of FIG. 3 and the timing chart of FIG. 4 is that the output timing T _{1 of} the reset signal shown in FIG.
It is decided by either.

According to this embodiment, by a drum servo system shown in FIG. 2 resets the composite synchronizing signal generator 2 of the imaging unit shown in FIG. 1 from the lock after a predetermined time T _1, +,
The field of the video signal recorded by the azimuth heads 53 and 54 can be made uniform at all times. For this reason, it is possible to reproduce a good screen with no skew even when the joint shooting is performed.

[Effects of the Invention] As described above, according to the video system of the present invention,
By resetting and initializing the image pickup unit after a predetermined time from the time when the drum servo system is locked, there is an effect that the relationship between the +,-azimuth heads and the even and odd fields can always be uniformly set.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image pickup unit of the video system of the present invention, FIG. 2 is a block diagram showing an embodiment of a recording unit of the video system of the present invention, and FIG. FIG. 4 is an operation timing chart of the video system shown in FIGS. 2 and 3, and FIG. 4 is another operation timing chart of the video system shown in FIGS. 1 ... Reset signal creation unit 2 ... Composite synchronization signal creation unit 11, 12 ...... Mono-multi, 21, 28 …… Divider 29, 30 …… Gate 31, 32 …… Shift register 33 …… Horizontal sync cutting Circuit 34 …… Vertical sync cutout circuit 35 …… Waveform synthesis circuit 51 …… Sync separation circuit 56 …… Internal reference signal creation circuit 57 …… PG pulse generation circuit 59 …… Phase comparison circuit 61 …… FG pulse generation circuit 64 …… Addition circuit, 66 …… Drum motor

Claims (1)

(57) [Claims] 1. An image pickup unit for outputting a video signal including a composite sync signal, which is initialized to stop the output of the video signal for a predetermined period of time, and after that, always outputs either an even number or an odd number. An image pickup unit that sequentially outputs a video signal from a field, a rotating body that is provided with two video heads that are driven by a motor and that record the image signal from the image pickup unit and have different azimuth angles, and a rotation phase of the rotating body. Rotation phase signal generating means for generating a signal shown below, and an oscillator oscillated at a vertical frequency and controlled so as to oscillate in phase synchronization with the vertical synchronizing signal of the video signal from the image pickup section when added. And the output of the oscillator is 1/2
The reference signal generating means for generating a reference signal based on the frequency-divided signal and the reference signal and the output of the rotation phase signal generating means are phase-compared to each other so that the phases of both are in a constant relationship. And a phase control means for controlling the phase of the output of the reference signal and the rotation phase signal generating means to a predetermined value. Is detected, the image pickup unit is initialized, and the vertical synchronizing signal of the video signal first supplied to the oscillator after the predetermined period is of an odd field or an even field. A video system, comprising: a recording unit having a control means for controlling so as to specify whether or not the video system is a video system.