JPS6242434B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention particularly relates to a color video signal recording system and a recording/reproducing system suitable for use in magnetic recording/reproducing devices, video disks, etc., in which a plurality of delay times different for each track are sequentially set at a scanning time period that is an integral multiple of the track. The delayed carrier color signal is recorded so that horizontal synchronization sections are lined up between adjacent tracks, and during playback, the delay amount during recording and playback is applied to the delayed carrier color signal regardless of the track. When reproducing by giving a delay time such that the sum becomes a constant value, the delay time is obtained by switching the clock pulse frequency of a memory such as a charge transfer element or a random access memory (RAM), and the color video signal is recorded. The purpose is to provide a method for reproducing this information. Figures 1 A and B were previously published by the present applicant in Japanese Patent Application Laid-Open No. 54-
This figure shows a block system diagram of an example of the recording system and playback system of the SECAM color video signal recording and playback system proposed in No. 37426. In the recording system shown in A of the same figure,
The SECAM color video signal that enters the input terminal 1 is supplied to a low-pass filter 2 and a band filter 3, respectively.The low-pass filter 2 separates the luminance signal, and the band filter 3 separates the carrier color signal. . The luminance signal is supplied to a frequency converter 5 via an AGC circuit 4, where it is converted into a frequency-modulated luminance signal in a predetermined band, and then supplied to a recording amplifier 7 via a high-pass filter 6 that removes unnecessary components.
On the other hand, as is well known, the carrier color signal is a first frequency modulated wave obtained by frequency modulating the color subcarrier frequency _fOB with the color difference signal B-Y, and a color subcarrier frequency with the color difference signal R-Y. The second value obtained by frequency modulating f _OR
The frequency modulated wave of 1 horizontal scanning period (1H)
This carrier color signal, which is a signal that is synthesized alternately and in time series, and has a carrier frequency of 3.9MHz to 4.75MHz, is supplied to the 1/4 frequency divider circuit 8, where the frequency is divided into 1/4. At the same time, the carrier frequency is changed from 0.97MHz to 0.97MHz.
It is within the range of 1.19MHz, that is, the frequency deviation is reduced to 1/4. The low-pass converted carrier color signal is supplied to a recording amplifier 7 through a low-pass filter 9 that removes unnecessary components, where it is frequency division multiplexed and amplified with the frequency modulated luminance signal to produce a composite color video signal. Magnetic heads 1 with mutually different azimuth angles
0a and 10b. As a result, the composite color video signal is alternately transmitted to the magnetic head 10a, for example, one field by the magnetic head 10a, the next field by the magnetic head 10b, and the next field by the magnetic head 10a. 10b, one video track for each field is sequentially formed and recorded on a magnetic tape (not shown), which is inclined in the longitudinal direction. Therefore, SECAM color video signals can be recorded in a relatively narrow band. Next, to explain the operation of the recycled yarn, see Figure 1 B.
The composite color video signal recorded on a magnetic tape (not shown) is transferred to the magnetic heads 10a, 10.
b is played alternately. The signal obtained by amplifying the output of the magnetic head 10a by the regenerative amplifier 11a and the signal obtained by amplifying the output of the magnetic head 10b by the regenerative amplifier 11b are alternately switched by the switching circuit 12 to form a continuous signal, and then passed through the high-pass filter 13. and low-pass filter 14, respectively. After the frequency-modulated luminance signal in the reproduced and synthesized color video signal is separated by the high-pass filter 13, the demodulation circuit 15
It is demodulated into a luminance signal. On the other hand, after the carrier color signal in the low frequency band in the reproduced composite color video signal is separated by the low pass filter 14, it is supplied to the quadrupling circuit 16, where the carrier frequency is returned to its original value. A predetermined band is extracted by a band filter 17. The reproduced carrier color signal from the band filter 17 and the reproduced luminance signal from the demodulation circuit 15 are each supplied to a synthesis circuit 18, where they are synthesized into a reproduced SECAM color video signal, which is then outputted from an output terminal 19. Ru. The tape patterns on the magnetic tape recorded and reproduced by the above-mentioned recording and reproduction method proposed by the present applicant are usually 1R, 2R,
3R, ..., 312B, 313R track, 3
13R, 314B, ..., 624B, 625R tracks, 1B, 2R, 3B, ..., 312R,
313B track, 313B, 314R,...
..., 624R, 625B tracks, 1R, 2
It is assumed that the tracks B, 3R, . Here, 1R is a carrier color signal recording section where the first 1H color difference signal R-Y is frequency modulated, 2B is a carrier color signal recording section where the next 1H color difference signal B-Y is frequency modulated, and 3R but
The number indicates the order of horizontal scanning lines in one frame, such as the carrier color signal recording section in which the 3H color difference signal R-Y is frequency modulated, and R and B are the carrier color signals (here, the regular carrier frequency). The modulation signal component of 1/4) is the color difference signal R-Y,
Indicates B-Y. In the case of the tape pattern shown in FIG. 2, the parallel synchronization signal recording positions are recorded in alignment (so-called H alignment) in the direction perpendicular to the longitudinal direction of the track, and, for example, in the adjacent track of 1R. In the next track after 315R, the modulation signal component of the carrier color signal converted to a lower frequency and recorded is the same as 4R, so the carrier color signal of the lower frequency is the same. The influence of crosstalk between adjacent tracks is small. This is because in the color video signal to be recorded, there is usually a correlation between the signal components at one field interval, for example, 1R and 315
Since the difference in frequency between R and B is small, the crosstalk between R and B is almost zero beat.
There is almost no influence on the demodulated color signal. Therefore, in a magnetic recording and reproducing apparatus that forms the tape pattern shown in the second diagram above, in order to perform recording and reproducing for a longer time, only the tape running speed is changed without changing the drum diameter, tape width, drum rotation speed, and number of horizontal scanning lines. When the tape pattern is reduced to 1/2 of that shown in FIG. 2, the tape pattern becomes as shown in FIG. 3. In the tape pattern shown in Figure 3, since the horizontal synchronizing signal recording positions are not lined up on adjacent tracks, there is no correlation between adjacent tracks, and the carrier wave frequency of the low frequency carrier color signal is different from that of the adjacent tracks. It will be different depending on the oshi. In this case, since adjacent recording tracks are recorded using magnetic beds with different azimuth angles, the azimuth loss of the frequency-modulated luminance signal at high frequencies is large, and the influence of crosstalk from adjacent tracks is extremely small. On the other hand, the recorded carrier color signal has a low frequency, so there is little azimuth loss, and since the carrier color signals recorded side by side in adjacent tracks have different carrier frequencies, there is no crosstalk from adjacent tracks. There was a problem that the effect was large and caused beat problems. The present invention solves the above problems,
Each embodiment will be described below with reference to FIGS. 4 to 16. The present invention delays only the carrier color signal that is affected by crosstalk using a memory, records the carrier color signal in adjacent tracks so that the horizontal synchronization sections of the carrier color signal line up, and delays the delayed carrier color signal during playback. By delaying playback using memory so that the time is constant, the influence of crosstalk from adjacent tracks is reduced. Third
To explain the case of a tape pattern with 0.75H increments as shown in the figure, first, in order to record the carrier color signals so that the same modulation signal components are adjacent to each other on adjacent tracks, it is necessary to As shown in Figure 4, the delay amount of the carrier color signal is 0 on a certain arbitrary track, that is, there is no delay, and on the next track there is a delay of 1.25H, and then on each track sequentially 0.5H,
This is possible by applying delay amounts of 1.75H, 1.0H, 0.25H, 1.5H, and 0.75H, that is, changes in the delay amounts with 8 tracks as one cycle, to the carrier color signal. These tracks are sequentially t ₁ , t ₂ , t ₃ , t ₄ ,
Let t ₅ , t ₆ , t ₇ , and t ₈ . Next, during reproduction, the carrier color signals must be returned to their original time relationships at the time of recording. Therefore, the reproduced carrier color signal from track t ₁ is delayed by 2H, and t ₂ is delayed by 0.75H.
The following sequential tracks t ₃ , t ₄ , t ₅ , t ₆ , t ₇ ,
The reproduced carrier color signal from _t8 is 1.5H, 0.25H, 1.0H,
Delays occur as follows: 1.75H, 0.5H, 1.25H. This means that for the same track, the sum of the delays during recording and playback is 2H. However, when forming and recording the tape pattern shown in FIG. 4 and reproducing it, the amount of delay of the conveyed color signal must be changed for each track (scanning time), so only one delay element is required. A charge transfer device such as a charge coupled device (CCD) or a bucket brigade device (BBD), or a memory such as a RAM, whose delay amount is varied depending on the clock pulse frequency so that it can be shared, is used. Now, using a CCD as an example, the number of stages is N, the clock pulse frequency is f _C (Hz),
If the delay time is τ(s), then τ=N/ _fC . Commercially available CCDs usually have 45 stages.
Since it is a stage, in order to delay by 1H when using it, the clock pulse frequency f _C must be 7109375 (Hz) from the above equation. As explained later, the duty cycle of the clock pulse is set to 50.
Since we use a 1/2 divider to convert it into %, the frequency created by the clock generator is 2f _C = 14218750 (Hz)
becomes. The above is for a 1H delay, so 0.25H
2f _C at the time of delay is 56875000 (Hz), which is four times that value. Therefore, at this time, the frequency used by the clock generator becomes too high, making the CCD unable to transmit information. Therefore, in order to obtain the tape pattern shown in FIG. 4, a delay amount of 0.25H is required, making it difficult to obtain the tape pattern shown in FIG. The characteristics of a CCD with a delay amount of 0.5H or more are shown in Figures 15 and 16, respectively.
The characteristics shown in the figure are when the CCD input signal frequency is 1 MHz, and the characteristics shown in FIG. 16 are when the CCD input signal frequency is 1.5 MHz. In addition, in each figure,
shows the characteristics of the low-pass filter next to the CCD. CCD
Even when the input is 1.5MHz, the delay amount is from 0.5H
Since there is a 3 dB difference up to 2.5H, the carrier color signal converted to a low frequency can sufficiently pass through. Furthermore, in order to obtain the tape pattern shown in FIG. 4, there is a track in which the amount of delay during recording is set to 0H, but for this reason a switch is required to determine whether or not to delay the conveyed color signal. Therefore, although the tape pattern shown in the fourth diagram may be used, in this embodiment, the case where the tape pattern shown in the fifth diagram is recorded and reproduced will be described as an example. As shown in FIG. 5, the amount of delay given to the conveying color signals recorded on tracks t ₁ to t ₈ is t ₁
2.0H for t 2, 1.25H for t ₂ , and 0.5H for t 2,
1.75H, 1.0H, 2.25H, 1.5H, 0.75H, and this is repeated in 8 track (scanning time) cycles.
When reproducing a magnetic tape having _the tape pattern shown _{in FIG} . H, 2.0H, 0.75H, 1.5H,
It will be 2.25H. That is, the sum of the delay amounts during recording and reproduction is set to be 3H. If such a delay amount is set in the recording and playback system, the conveyed color signal will always be delayed, so there is no need for a switch to select whether or not to delay it, and the necessary delay amount is
All can be obtained by CCD. Furthermore, the present invention adjusts the amount of delay during recording in order to determine the amount of delay during playback so that the sum of the delay amounts during recording and playback becomes a predetermined delay amount (3H in the case of FIG. 5). The discrimination signal shown is multiplexed and recorded on the frequency-modulated luminance signal and the carrier color signal converted to a low frequency and delayed. Also, during playback, the determination signal is detected and the amount of delay is determined. Furthermore, for variable speed playback, in the first embodiment, the discrimination signal is recorded over the entire length of all tracks. FIG. 6 is a block diagram of an embodiment of the recording system of the present invention, and FIG. 7 is a block diagram of an embodiment of the reproduction system of the invention. In each figure, Figure 1 A, B
The same components are given the same reference numerals and their explanations will be omitted. In FIG. 6, reference numeral 20 denotes a discrimination signal oscillation circuit, which has a configuration, for example, as shown in FIG. One track scanning time from this time forms a track _t1 shown in FIG. 5, while a discrimination signal for discriminating the amount of delay is supplied to the recording amplifier 7'. Reference numeral 21 denotes a variable delay circuit that sequentially applies a predetermined amount of delay to the conveyed color signal from the low-pass filter 9 using a drum pulse and a pulse with an 8-track scanning time period from the discrimination signal generation circuit 20, and outputs the resultant signal. As will be described later, the configuration is shown in FIG. 11. A composite color video signal obtained by frequency-division multiplexing the frequency-modulated luminance signal extracted from the recording amplifier 7', the carrier color signal converted to a low frequency, and the discrimination signal is sent to the magnetic heads 10a and 10b.
A tape pattern is formed in which the frequency-modulated luminance signals are not arranged in an H-line, but only the carrier color signals are arranged in an H-line as shown in FIG. 5. Here, the recorded waveform of the discrimination signal is a sine wave, and the frequencies are 2n×f _H /2 and (2n-1) f _H /2
(n is a self-number, f _H is a horizontal scanning frequency) are the discrimination signal frequencies for adjacent tracks, respectively, and in this embodiment, as will be described later, 10f _H , 10.5f _H , 12f _H ,
Select 12.5f _H , 14f _H , 14.5f _H , 16f _H , and 16.5f _H in this order. In other words, in this embodiment, the frequency of this discrimination signal is determined by the frequency deviation of the frequency-modulated luminance signal.
3.4MHz to 4.4MHz, the frequency shift of the carrier color signal (frequency modulated wave) converted to a low frequency is
Considering that the range is from 0.97MHz to 1.19MHz, a low band slightly away from the carrier color signal converted to a low frequency is selected. Therefore, in a two-head helical scan type magnetic recording and reproducing apparatus using an azimuth recording and reproducing method as in this embodiment, if tracks are recorded closely together without providing a guard band between the tracks, the discrimination signal will be low during reproduction. Since the frequency is within the range, the azimuth loss is small, so the amount of crosstalk from adjacent tracks is large. Therefore, in Figure 7, 23
In the reproduction of the discrimination signal by the discrimination signal detection circuit shown in , the delay time of the carrier color signal currently being reproduced is determined from the discrimination signal from which crosstalk has been removed using a comb filter, as will be described later. Further, during reproduction, as shown in FIG. 7, after the variable delay circuit 24 gives a delay amount such that the sum of the recording and reproduction delay amounts is constant to the low frequency reproduction carrier color signal from the band filter 25. The signal is supplied to the quadrupling circuit 16. Here, the delay time of the variable delay circuit 24 is:
Based on the output discrimination signal of the discrimination signal detection circuit 23
It is sequentially switched every 1H to achieve a predetermined delay amount.
As a result, each reproduced carrier color signal from the variable delay circuit 24 is delayed by a certain amount of time. Next, the main parts of the recording system of this embodiment will be explained in more detail. FIG. 8 shows a circuit diagram of one embodiment of the discrimination signal generation circuit 20. In the same figure, input terminal 2
Drum pulse a as shown in FIG. 9A entered at 6
is applied to the clock input terminal CK of the presettable down counter 27, where it is subtracted and counted. The positive polarity period of this drum pulse a is equal to the period in which one of the magnetic heads 10a, 10b is scanning the track, and the negative polarity period is equal to the period in which the other magnetic head is scanning the track. The presettable down counter 27 always outputs “1”, “1”, “0”, and “1” to the preset input terminals A, B, C, and D.
The data ("1011" in binary) is input,
This preset input data is loaded at the rising edge of the output of the 3-input AND circuit 28, and the output terminals Q _A ,
Output from Q _B , Q _C , and Q _D. Here, 3 inputs
Since the three input terminals of the AND circuit 28 are connected to the output terminals Q _B and Q _C of the counter 27 and the drum pulse input terminal 26 via the inverter 29, the drum pulse a is at a low level and the presettable When the _QB output d shown in FIG. 9D and the _QC output e shown in FIG. 9E of the down counter 27 reach a high level, a high level signal is output.
As a result, the presettable down counter 2
7's Q _A ~ Q _D output becomes preset data, and Q
Since _C output e becomes low level, AND circuit 28
The output immediately goes low. Yotsuteko
The output of the AND circuit 28 becomes a positive polarity pulse g with an extremely narrow pulse width as shown in FIG. 9G. This pulse g is divided into two parts, one being supplied to the load terminal of the counter 27 and the other being supplied from the output terminal 30 to the variable delay circuit 21 shown in FIG. 11, which will be described later. The counter 27 then uses the preset input data 101 until the next clock, that is, drum pulse a, enters the presettable down counter 27.
1, and therefore its Q _A , Q _B , Q _C ,
The output of Q _D is c, d, e, in Figure 9 C, D, E, F.
As shown by f, high level, high level, low level, and high level are held. In the embodiment, the presettable down counter 27 is configured to perform subtraction counting at the rising edge of the clock. Q of the above presettable down counter 27
The output terminals _A , Q _B , Q _C , and Q _D are the 3rd bit, 4th bit, 5th bit, and 6th bit of the presettable up counter 31.
D, E, and F, and the 1st and 2nd bit input terminals A and B of the up counter 31 are connected to the drum pulse input terminal 26, so the drum pulse when the pulse g is output is pulse a
During the negative polarity period (one track scanning period, for example, one field period), the up counter 3
1 preset data input terminals A, B, C, D,
E and F have logic “0”, “0”, “1”, “1”, respectively.
Inputs of "0" and "1"("101100" in binary notation) will continue to be applied. up counter 31
is a 6-bit binary counter, and the output signal of a voltage controlled oscillator (VCO) 36 is applied to its clock input terminal CK to perform addition counting. The output signal frequency of the VCO 36 is approximately _20fH to _33fH , and has a waveform as shown in FIG. 10A.
When the 36 output signals reach a predetermined value, a low level pulse is output to a monostable multivibrator (hereinafter referred to as "mono multi") 32 to trigger it. By this trigger, the monomulti 32 applies a pulse with a narrow pulse width to the phase comparator 35 to load the input data at that time (the above-mentioned "101100" in binary notation). At this time, the output of the monomulti 32 is as shown by _h1 in Fig. 10H, and the up counter 31 is
When the clock from 6 is counted 20 times and all bit outputs of the up counter 31 become low level, the output of the monomulti 32 is taken out as shown by _h0 in FIG. 10, and the up counter 31 returns to the original h. Returns to input data loading state when set to ₁ . The above operations are repeated. In this way, the presettable up counter 31 reduces the output of the VCO 36 by 1/2.
The frequency will be divided to 0. On the other hand, the input terminal 33 should record
A horizontal synchronizing signal in the SECAM color video signal is input and triggers the monomulti 34. The 1H cycle output pulse of this monomulti 34 is phase-compared with the pulse from the monomulti 32 whose frequency has been divided by 1/20 above in a phase comparator 35, and the oscillation frequency of the VCO 36 is set at a voltage according to their phase difference. control. Therefore, a phase comparator 35 including a low-pass filter, a VCO 36, an up counter 31,
The mono multi 32 constitutes a so-called phase locked loop (PLL), and the two inputs of the phase comparator 35, that is, the output of the mono multi 32, are set to be equal to the output frequency of the mono multi 34.
VCO 36 is caused to oscillate. Therefore, since the input to the monomulti 34 is a horizontal synchronizing signal, when the frequency division ratio of the up counter 31 is 1/20 as described above, the oscillation frequency of the VCO 36 becomes _20fH . Next, when the drum pulse a shown in FIG. 9A rises as shown by _a1 , the presettable down counter 27 subtracts one count and becomes "1010" in binary notation, that is, FIG. Of the Q _A to Q _D outputs of the down counter 27 shown in FIG. 1, only the Q _A output becomes low level as shown in FIG. Note that FIG. 9B shows the output pulse b of the inverter 29. Therefore, the input data of the presettable up counter 31 becomes "101011" in binary notation, which is also decreased by 1 in binary notation. At this time, the presettable up counter 31 starts from the time of the input data ("101011" in binary notation), that is, from the time shown by _h2 in FIG. 10H, the VCO 36
Start addition counting of the output signals of h ₀ and perform addition counting until the time when each bit output of the counter 31 shown in FIG. 10 B to G becomes low level, as shown by h ₀ Monomulti 32 at the moment
By the output of , each bit output of the counter 31 is returned to the same state as the input data, that is, the state at the time point _h2 in H in the figure, and the same operation is repeated thereafter. As a result, the frequency division ratio by the presettable up-counter 31 becomes 1/21, and the oscillation frequency of the VCO 36 becomes _21fH . Then, the drum pulse a falls as shown by _a2 in FIG. 9A, but the output of the presettable down counter 27 does not change at the fall of the clock as described above. However, drum pulse a
becomes a low level, so both input terminals A and B of the presettable up counter 31 become "0", and the input data becomes "101000" in binary notation, and only 3 is input from the previous "101011". Data value decreases. As a result, the counter 31 moves from the position indicated by _h3 in FIG. 10 to VCO3.
After counting the output signals of step 6, the VCO 36 is counted again at the position shown by h ₀ using the output of the monomulti 32 (shown by h ₃ and h ₀ in H in the same figure) from the position shown by h ₃ in H in the figure.
The output signals of are counted. Drum pulse a below
The above counting operation is repeated during one track scanning period until the next rise (point _a3 in FIG. 9A), and the output signal of the VCO 36 is sent to the counter 31.
The frequency will be divided by 1/24, so the VCO
The output oscillation frequency of 36 is _24fH . Similarly, every half period of drum pulse a,
That is, for each one track scanning period of the two rotating magnetic heads, the counter 31 changes h ₄ to h ₀ in H of FIG.
VCO36 between h ₅ ~ _{h 0} , h ₆ ~ h ₀ , h ₇ ~ h ₀ , h ₈ H ~ h ₀
By repeating the counting of the output signal, the output of the VCO 36 is divided in the order of 1/25, 1/28, 1/29, 1/32, and 1/33, so the output oscillation frequency of the VCO 36 is one track scan. 25f _H , 28f _H , 29f _H , 32f _H , 33f _H for each period
It is changed in the following order. Furthermore, Figure 10G is
The waveform of the output signal applied from the counter 31 to the monomulti 32 when the output oscillation frequency of the VCO 36 is _33fH is shown. Here, the counter 31 and the monomulti 3
The output signal frequency of No. 2 is always the horizontal scanning frequency f _H regardless of the drum pulse a, and is shown in Fig. 10 A to H.
are respectively VCO 36, counter 31, mono multi 3
Since the two output signal waveforms are the same, they are shown in common for convenience of illustration, but it must be noted that the time axes are therefore different for each track scan. In other words, when scanning (recording) the first track _t1 ,
The output waveforms of the monomulti 32 are only h ₁ and h ₀ in H in FIG. 4, and there is 1H between them. Similarly _{, the} output waveforms _{of the} monomulti _{32 shown} in _{FIG . 0} , _h3 and _h0 , _h4 and _h0 , _h5 and _h0 , _h6
and h ₀ , h ₇ and h ₀ , and h ₈ and h ₀ , and the time interval between them is 1H. When the output oscillation frequency of VCO36 is 33f _H ,
Since the binary value of the output of the counter 27 is "0111", among the three inputs applied from the counter 27 to the AND circuit 28, the Q _B output d and the Q _C output e are both high level ("1"). However, the output b of the remaining one inverter 29 is at low level (“0”). In this state, the drum pulse a then falls as shown by _a8 in FIG. are all at high level, and at this time AND circuit 2
The output g of 8 becomes high level as shown in FIG. As a result, among the three inputs of the AND circuit 28, only the Q _C output e becomes a low level as shown in FIG. 9E, so the output g of the AND circuit 28
immediately becomes a low level as shown in G in the figure. By loading the preset input data of the counter 27, the output oscillation frequency of the VCO 36 becomes _20fH as described above. Thereafter, the same operation as above is repeated. The output signal of the VCO 36 is counted by the presettable up counter 31, and the frequency is divided by 1/2 by the 1/2 frequency divider circuit 37 and converted into a rectangular wave with a duty cycle of 50%. The signal is output as a discrimination signal from an output terminal 39 through a low-pass filter 38 that generates a sine wave. In this way, the frequency of the discrimination signal output from the output terminal 39 is 10f _H for each track scanning time.
10.5f _H , 12f _H , 12.5f _H , 14f _H , 14.5f _H , 16f _H ,
16.5f _H is sequentially repeated, and this is applied to the recording amplifier 7' shown in FIG. Next, the operation of one embodiment of the variable delay circuit 21 shown in FIG. 6 in the recording system will be explained in detail with reference to the block diagram shown in FIG. 11. In FIG. 11, the low frequency carrier chrominance signal to be recorded which enters the input terminal 40 is applied to a charge coupled device (CCD) 41, which is identical for the same track, as will be explained below. In addition, different delay times are given to adjacent tracks.
The delay amount τ of the CCD 41 is expressed by the following equation. τ=N×1/f _C =N/f _C However, in the above equation, f _C is the clock pulse frequency of the CCD, and N is the number of stages of the CCD. Therefore, the fifth
Delay amount to obtain the tape pattern as shown in the figure.
0.5H, 0.75H, 1.0H, 1.25H, 1.5H, 1.75H,
To obtain 2.0H and 2.25H, from the above formula, Nf _H /0.5,
Nf _H /0.75, Nf _H /1.0, Nf _H /1.25, Nf _H /1.5,
It is necessary to create a total of eight different clock frequencies f _C : Nf _H /1.75, Nf _H /2.0, and Nf _H /2.25. The duty cycle of the clock pulse is set to 50 using the 1/2 frequency divider circuit 47.
% and divide the frequency by 1/2. Therefore, the output frequency of data selector 44 must be _2fC . In addition, in order to generate eight types of clock pulses from one clock generator 45, the oscillation frequency of the clock generator 45 is changed.
Select 8Nf _H and set the frequency divider circuit 46 to 1/2, 1/2, 1/2, 1/
5, 1/7, 1/3, 1/3, 1/3 frequency dividers 46a to 46
h, and each data input terminal D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , D ₇ of the data selector 44 has
Nf _H , 8/5Nf _H , 4Nf _H , 8/7Nf _H , 2Nf _H , 8/
Frequency signals of 9Nf _H , 4/3Nf _H , and 8/3Nf _H are applied from the frequency dividing circuit 46 . On the other hand, the select terminal S ₀ of the data selector 44,
Of S ₁ and S ₂ , the drum pulse from the input terminal 42 is applied to S ₀ , the pulse obtained by dividing the drum pulse by 1/2 from the frequency dividing circuit 43 is applied to S ₁ ,
Furthermore, a pulse obtained by frequency-dividing the drum pulse by 1/4 by a frequency dividing circuit 43 is applied to _S2 . The frequency dividing circuit 43 is reset by the pulse g from the output terminal 30 of the discrimination signal generating circuit 20 shown in FIG. The data selector 44 has the above select terminals S ₀ ,
Data input terminal D ₀ ~ according to the input to S ₁ and S ₂
D Output one of the input data of ₇ to output terminal Y
Make more output. The signal output from this output terminal Y is a 1/2 frequency divider circuit 47, a pulse shaping circuit 48,
The signal is sequentially passed through the amplifier circuit 49 and applied to the CCD 41 as a clock pulse for controlling the delay amount τ. Here, the inputs of _S0 to _S2 , the data input terminal of the signal selected and output from the output terminal Y of the data selector 44, the clock pulse frequency f _C of the CCD 41, the CCD
The delay amounts τ of 41 have the relationships shown in Table 1.

[Table] S ₂ S ₁ S ₀ in Table 1 is the track number expressed in binary (binary 0 is track t ₁ , 1 is track number
_{t2 , .} shall be. In this way, 2.0H, 1.25H,
It is switched every track scanning time in the order of 0.5H, 1.75H, 1.0H, 2.25H, 1.5H, 0.75H, and
A conveyed color signal having a delay time given every 8 track scanning periods is taken out and sent to an output terminal 51 through a low-pass filter 50 for removing clock pulse components.
The signal is then supplied to a recording amplifier 7' shown in FIG. As a result, in a recording system in which the tape pattern shown in FIG. 3 would be formed if the conveyed color signal is not delayed, the conveyed color signal of low frequency is passed through the variable delay circuit 21 shown in FIG. , as shown in FIG. 5, the same modulation signal components (color difference signals) are recorded side by side in adjacent tracks, and the discrimination signals with different frequencies depending on the delay time are also continuous over the entire length of the track. recorded. Next, the main parts of the reproduction system, that is, the discrimination signal detection circuit 23 and variable delay circuit 24 shown in FIG. 7 will be explained in more detail. FIG. 12 shows a circuit diagram of one embodiment of the discrimination signal detection circuit 23. In the figure, continuous reproduced and synthesized color video signals from the switching circuit 12 shown in FIG. Here, it is amplified to the amplitude required by the 1H delay circuit 56. Since the output reproduction discrimination signal of the amplifier 55 has a low frequency with little azimuth loss, it includes the discrimination signal reproduced as crosstalk from the adjacent track in addition to the original discrimination signal from the track being reproduced. , are supplied to the next-stage 1H delay circuit 56 and adder 57 to eliminate this crosstalk, while being phase-inverted by an inverter 58 and supplied to an adder 59. The adder 57
The 1H delay circuit 56 outputs the sum of the 1H delayed signal and the 1H non-delayed signal, and the adder 59 outputs the sum of the 1H delayed signal and the 1H non-delayed signal with phase inversion, that is, 1H. Outputs the signal obtained by subtracting the 1H non-delayed signal from the delayed signal. Now, if the signal frequency input to the 1H delay circuit 56 is 2n×f _H /2, the adder 57 outputs a signal with twice the amplitude, and the adder 59 outputs the two input signals input to it. cancel each other, so no signal is output. Further, when a signal with a frequency of (2n-1)f _H /2 is input to the 1H delay circuit 56, the output of the adder 57 becomes zero, and the output of the adder 59
The output becomes a signal with twice the amplitude of the input. In other words, a signal with frequency 2n×f _H /2 and a signal with frequency (2n-1) f _H
/2 signals are mixed, the adder 57 outputs 2n signals.
Only the signal with a frequency of ×f _H /2 is separated and output, and only the signal with a frequency of (2n-1)f _H /2 is separated and output from the adder 59. However, as mentioned above, the frequency of the discrimination signal is
2nf _H /2 or (2n - 1) f _H /2, and when the discrimination signal frequency of one track is 2nf _H /2, the discrimination signal frequencies recorded in the adjacent tracks on both sides are (2n-1) f _H /2. Also, when recording the discrimination signal, _the drum pulse is at a low level (or high level) and the frequency (2n-
1) On the f _H /2 track, the drum pulses have a constant relationship such that they are at high level (or low level). Therefore, the drum pulse from the input terminal 61 is used as the switching signal for the switch 60 that switches the outputs of the adders 57 and 59, and when the drum pulse is at a low level, the switch 60 is connected to the adder 57. When the drum pulse is at a high level, by connecting it to the adder 59, only the discrimination signal from the track being played, from which crosstalk from adjacent tracks has been removed, is always taken out from the movable contact of the changeover switch 60. It turns out. The reproduction discrimination signal from which crosstalk has been removed is converted into a rectangular wave a by a limiter 62 as shown in FIG. A negative polarity pulse b as shown in FIG. 13B is further applied to the clock input terminal of the 4-bit binary counter 64,
It is counted here. As a result, the counter 64
The outputs of Q ₀ , Q ₁ , Q ₂ and Q ₃ are shown in Figure 13 C, D,
As shown in E and F, the Q ₂ and Q ₃ outputs are temporarily stored in the latch 65 at the rising edge of the Q ₁ output. As a result, the output of the latch 65 becomes the 13th
It is as shown by g and h in Figures G and H. On the other hand, a horizontal synchronization signal obtained by removing the equalization pulse and the vertical synchronization signal from the composite synchronization signal is applied to the input terminal 67 at the lower left of FIG. multi 6
Trigger 8. The monomulti 68 generates a positive polarity pulse i ₀ shown in FIG. 13I, which has a time width considerably shorter than the half cycle of the rectangular wave a shown in FIG. 66
and applied to the monomulti 69. mono multi 69
generates a positive pulse j ₀ shown in FIG. 13J, which has a time width considerably shorter than the half cycle of the rectangular wave a, at the moment the input pulse i ₀ becomes low level. Pulse i ₀ latches output signals g, h of latch 65
The information on whether the signals g and h at that time are high level or low level is output to terminals 71 and 72, respectively. Immediately thereafter, pulse _j0 resets counter 64. Here, the period of the output pulses of the monomultis 68 and 69 is a constant horizontal scanning period regardless of the track being reproduced, and on the other hand, the waveforms shown in FIGS. 13A to 13H are the same, so for convenience of illustration, It should be noted that the time axes of the timing charts shown in FIGS. A to J differ for each track reproduction scan. That is _, when reproducing track _t1 in FIG.
4 repeats the operation of counting 20 pulses b, so at this time, the monomulti 68, 6
The output pulses of 9 are i ₀ , i ₁ , j ₀ , j ₁ in Fig. 13 I and J.
and the period of i ₀ to i ₁ and j ₀ to _{j 1} is as shown in
It is 1H. However, when playing the next track t ₂ , the determination signal frequency is changed to determine the delay amount of 1.25H.
Since it is 10.5f _H , the mono multi 68 at this time,
The output pulses of 69 are shown in Fig. 13 I, J as i ₀ , i ₂ ,
j ₀ and j ₂ , and the period of i ₀ to i ₂ and j ₀ to j ₂ is 1H. Below, similarly, when the discrimination signal frequencies are 12f _H , 12.5f _H , 14f _H , 14.5f _H , 16f _H , 16.5f _H , the 1H period output pulses of the monomulti 68 and 69 are the above i ₀ , j ₀ In addition, i ₃ , j ₃ , i ₄ in Figure 13 I, J
and j ₄ , i ₅ and j ₅ , i ₆ and j ₆ , i ₇ and j ₇ , i ₈ and j ₈ , and when 16.5f _H , from i ₀ to i ₈ and from j ₀ to j ₈ Each of the up and down represents 1H. In FIG. 12, the outputs of the latch 66 are led to terminals 71 and 72, respectively, and their levels are the same when the discrimination signal frequencies are 10f _H and 10.5f _H , and are the same when the discrimination signal frequencies are 12f _H , 12.5f _H , and 14f _H. 4.5f _H , 16f _H and 16.5f _H show the same state. However, when the frequency 2nf _H /2 and the frequency (2n-1)f _H /2 are input, the state of the drum pulse is different, so 10f _H , 10.5f _H , 12f _H
and 12.5f _H , 14f _H and 14.5f _H , and 16f _H and 16.5f _H . Therefore, by connecting the terminals 70, 71, and 72 to the select terminals S ₀ , S ₁ , and S ₂ of the data selector 77 shown in FIG. The signal is outputted from the terminal 70, and the delay amount of the variable delay circuit 24 is variably controlled according to the discrimination signal frequency. In this case, since the frequency of the discrimination signal is determined based on the delay amount of the carrier color signal converted to a low frequency during recording, the recording of the carrier color signal depends on the states of S ₀ , S ₁ , and S ₂ during playback. The data selector 77 adjusts the output of the frequency divider 76 so that the sum delay amount throughout the reproduction is constant (3H in the embodiment), in other words, the difference in relative delay amounts is zero in the reproduction system. choose. Since the discrimination signal is multiplexed over the entire length of the track, it is possible to detect the discrimination signal even during variable speed playback, and it is possible to set the amount of delay so that the time relationship of the carrier color signals is normal. . Next, to explain the operation of the variable delay circuit 24 of the reproduction system shown in FIG. 7, FIG.
4 shows a block system diagram of one embodiment of No. 4. In the same figure,
Reference numeral 73 designates an input terminal for a reproduced carrier color signal of a low frequency separated by the band filter 25 shown in FIG. The variable delay circuit 24 is the variable delay circuit 2
1, and as shown in FIG. 14, it has a CCD 74, a clock generator 75 that outputs oscillation at a frequency of _8NfH , a frequency dividing circuit 76, a data selector 77, a 1/2 frequency dividing circuit 78, and a pulse generator. It consists of a shaping circuit 79, an amplifier circuit 80, and a low-pass filter 81 for removing the clock frequency. Here, frequency dividers 76a to 76a forming the data selector 77 and the frequency dividing circuit 76
All the circuits other than 76i among 76i can share the recording system circuit corresponding to No. 11 shown in FIG. However, the output of the frequency divider 46a used during recording is not connected to the data selector 77 because the delay amount of 0.5H is not used during reproduction. Other 7 frequency dividers 76
b, 46b, 76c, 46c, 76d, 46d,
76e, 46e, 76f, 46f, 76g, 46
The outputs of g, 76h, and 46h are data selector 77.
and 44. In fact, the input terminal of the 1/2 frequency divider circuit 78 is connected to the output terminal Y of the data selector 44 during recording, and to the output terminal of the data selector 77 by an electronic switch (not shown) during reproduction. Furthermore, the frequency divider 76i has a delay amount
It is for obtaining 2.5H and cannot be shared with the recording system. Data input terminals D ₀ to _{D 7} of data selector 77
is the output signal frequency of the clock generator 75.
_A signal obtained by _{dividing 8Nf H} by a frequency dividing circuit ₇₆ is applied, _{and 2Nf H} , _{8 /} 7Nf _H , 4/5Nf _H , 8/5Nf _H ,
Signals with frequencies of Nf _H , 8/3Nf _H , 4/3Nf _H , and 8/9Nf _H are applied, and the selection terminals S ₀ , S ₁ , and S ₂ of the data selector 77 detect the discrimination signal shown in FIG. Detection outputs of discrimination signals from output terminals 70, 71, and 72 of the circuit 23 are applied. This results in
The relationship among the inputs of the select terminals S ₀ to _{S 2} of the data selector 77, the data input terminal of the signal selected and output from its output terminal Y, the clock pulse frequency f _C of the CCD 74, and the delay amount τ of the CCD 74 is shown in Table 2.
It will look like this.

[Table] S ₂ S ₁ S ₀ in Table 2 is the track number expressed in binary (binary 0 is track t ₁ , 1 is track number
t ₂ , 2 is t ₃ , ..., 7 is t ₈ ). Therefore, the carrier color signal with a delay time of 2.0H reproduced from track _t1 of the tape pattern shown in FIG.
As shown in the figure, the carrier color signal with a delay time of 1.25H is given a delay time of 1.0H and is output through the low-pass filter 81 to the output terminal ₈₂ , and reproduced from the track t2. output terminal 8 through a low-pass filter 81
Output to 2. Similarly, as is clear from Table 2, the tracks t ₃ , t ₄ , t ₅ , t ₆ ,
Delay time 0.5H played sequentially from t ₇ and t ₈ ,
The carrier color signals of 1.75H, 1.0H, 2.25H, 1.5H, 0.75H are processed by the variable delay circuit 24 shown in FIG. 14 as shown in Table 2.
A delay time of 2.25H is given sequentially. The above-mentioned variable delay circuit 24 applies the above-mentioned predetermined delay time, and as a result, throughout recording and playback, the reproduced carrier color signal of the low frequency from all the tracks of the tape pattern shown in the fifth diagram is uniformly 3H (4th
In the case of the illustrated tape pattern, the signal is given a delay time of 2H) and is supplied to the quadrupling circuit 16 shown in FIG. 7, where it is returned to the original band. By performing the above signal processing and giving a predetermined delay time, the carrier color signals recorded in H array are reproduced with the relative delay time difference zeroed out, and cross signals from adjacent tracks are reproduced. It is possible to obtain high-quality color images with almost no influence from talk. However, the reproduced transport color signal lags behind the reproduced luminance signal by 3H when the fifth illustrated tape pattern is reproduced, and by 2H when the fourth illustrated tape pattern is reproduced. This time delay of the reproduced carrier color signal with respect to the reproduced luminance signal may result in some television receivers not being able to accurately reproduce colors, such as lack of color. This is SECAM
A discrimination signal for discriminating whether the modulation signal component of the carrier color signal is R-Y or B-Y is multiplexed in the color video signal, but the circuit that separates and extracts this signal is delayed due to the above-mentioned time delay. This may cause malfunctions due to overloading. Therefore, in such a case, a delay circuit 22 is inserted in the luminance signal transmission path between the low-pass filter 2 and the AGC circuit 4 as shown in FIG. 6 in the recording system, and a delay circuit 22 is inserted in the reproduction system as shown in FIG. 7. Gotoku demodulation circuit 1
A delay circuit 98 is inserted in the demodulated luminance signal transmission line between the demodulated luminance signal 5 and the synthesis circuit 18 to reduce or eliminate the relative time difference between the reproduced luminance signal and the reproduced carrier color signal. When the delay times of the delay circuits 22 and 98 are each set to 1H, both delay circuits can be used in common. Further, it is also possible to provide only one of the delay circuits 22 and 98 to provide a delay time of 2H or 3H. Note that the variable delay circuits 21, 2
4 is configured to delay the carrier color signal in the low frequency band by taking into account the transmission bands and clock frequencies of the CCDs 41 and 74. It is also possible in principle to delay the carrier color signal in a predetermined high frequency band. In each of the above embodiments, the color video signal to be recorded and reproduced has been described as being of SECAM format, but may be of PAL format. In addition to CCDs, other charge transfer devices such as bucket brigade devices (BBDs) may be used as variable delay devices, and even random access memories (RAMs) can be used to change the frequency of each clock pulse for writing and reading. (However, it is assumed that both frequencies are always the same). Further, the delay time does not need to be eight, and the point is that the carrier color signal recorded in at least a predetermined band is so-called H.
Any number of types may be used as long as they are recorded in sequence. Furthermore, it goes without saying that the deviation between horizontal synchronization sections on adjacent tracks is not limited to 0.75H. The recording medium may be a magnetic disk, a video disk, a card, or the like, and the recording means may be a light beam or other converter depending on the recording medium. As mentioned above, the color video signal recording method and recording/reproducing method according to the present invention utilizes charge transfer elements and RAM.
The scanning time period is set to be an integer multiple of the track so that the delay time is the same when the converter on the recording medium is scanning the same track for the conveyed color signal, and the delay time is different for adjacent tracks. A plurality of delay times are given by sequentially switching the clock pulse frequency of the memory, and the delayed carrier color signal converted into a predetermined signal form is recorded on a recording medium together with the luminance signal converted into a predetermined signal form. During playback, the sum of the delay times given to the carrier color signals during recording and playback is constant regardless of the track, so one memory can be shared by simply switching the clock pulse frequency, and multiple By selecting the delay time and the period of the delay time to predetermined values, it is possible to easily convert the carrier color signals recorded on adjacent tracks into a desired carrier color signal (for example, SECAM).
The same color difference signal in a PAL color video signal, the same signal for alternating color bursts in a PAL color video signal, and the same color difference signal in a PAL color video signal. When used in a helical scan VTR, the tape can be run at different speeds when recording in so-called H-line format without changing the guide drum diameter, tape running angle on the drum circumference, etc. In some cases, the horizontal synchronization sections of the carrier color signals can be easily aligned and recorded between adjacent tracks, thereby obtaining a high quality reproduced color image, and at least one of the recording system and the reproduction system can be recorded. Since a means for delaying the luminance signal by a delay amount near the fixed value of the delay amount of the reproduced delayed carrier color signal is provided in the apparatus, the relative time difference between the reproduced delayed carrier color signal and the reproduced luminance signal can be made zero or small; Therefore, it has many features such as being able to reproduce normal color images on a monitor.

[Brief explanation of the drawing]

Figures 1A and 1B are block system diagrams showing an example of the recording system and reproduction system of the color video signal recording and reproduction system previously proposed by the present applicant, and Figure 2 is a block system diagram showing an example of the recording system and reproduction system of the color video signal recording and reproduction system proposed earlier by the present applicant, and Figure 2 is a block system diagram showing recording using the recording system of Figure 1A. Figure 3 shows a tape pattern of an example of a formed SECAM color video signal.
The figure shows an example tape pattern when a SECAM system color video signal is recorded using the recording system shown in Figure 1A, with only the tape running speed being changed.
5 and 5 are diagrams showing respective examples of tape patterns showing the recording arrangement of carrier color signals of SECAM color video signals recorded in H array according to the method of the present invention, and FIG. FIG. 7 is a block system diagram showing an embodiment of the recording and reproducing method of the present invention, and FIGS. 8 and 11 respectively show the main parts of FIG. 6. 9A-G and 10A-H are respectively signal waveform diagrams for explaining the operation of FIG. 8, and FIGS. 12 and 14 are respective circuit system diagrams of FIG. A circuit diagram showing an embodiment of the section, FIG. 13A~
J is the signal waveform diagram for explaining the operation in FIG. 12, and
5 and 16 are diagrams respectively showing examples of input/output characteristics of a CCD as an example of a variable delay element according to the present invention. 1... Color video signal input terminal, 8... 1/4 frequency dividing circuit, 10a, 10b... Magnetic head, 16...
... Quadruple multiplier circuit, 19... Reproduction color video signal output terminal, 20, 23... Discrimination signal detection circuit, 21,
24...Variable delay circuit, 22,98...Delay circuit, 26,42,61...Drum pulse input terminal, 33,67...Horizontal synchronization signal input terminal, 39
...Discrimination signal output terminal, 41,74...Charge coupled device (CCD), 44,77
...Data selector, 46, 76... Frequency dividing circuit.

Claims (1)

[Claims] 1. A color system in which a luminance signal (including a synchronization signal) and a carrier color signal are separated from a color video signal, and both signals are converted into predetermined signal formats, mixed and multiplexed, and recorded on a recording medium. In the video signal recording method, when a converter on the recording medium scans the same track using a memory such as a charge transfer element or a random access memory, it is possible to detect signals with the same delay time and adjacent to each other while the converter on the recording medium scans the same track. The delayed carrier chrominance signal converted into the predetermined signal form is given by sequentially switching the clock pulse frequency of the memory so that the track has a different delay time with a scanning time period that is an integral multiple of the track. A color video signal recording method characterized in that the luminance signal is mixed and multiplexed into the luminance signal converted into the predetermined signal format and recorded on a recording medium. 2. The color video signal recording system according to claim 1, wherein the delay time given to the conveyed color signal by the memory is a delay time obtained by adding one horizontal scanning period to the minimum required delay time. 3 Separate the luminance signal and carrier color signal from the color video signal, convert both signals into predetermined signal formats, mix and multiplex them, record on a recording medium, and when playing back, record from the playback signal played from the recording medium. In a color video signal recording and reproducing method in which a reproduced color video signal is obtained by separating and reproducing a luminance signal and a carrier color signal, and then mixing and multiplexing them, memories such as charge transfer elements and random access memories are used during recording and reproduction. The transducer on the recording medium has a scanning time period that is an integral multiple of the track so that the delay time is the same when scanning the same track, and the delay time is different between adjacent tracks. A plurality of delay times are given by sequentially switching the clock pulse frequency of the memory, and furthermore, during playback, a playback delayed carrier color signal separated from the playback signal is used, regardless of the track, so that the sum of the delay amounts during recording and playback is constant. A color video signal recording and reproducing method that is characterized by delaying and reproducing the video signal so as to obtain the desired value. 4 Separate the luminance signal and carrier color signal from the color video signal, convert both signals into predetermined signal formats, mix and multiplex them, record on a recording medium, and when playing back, record from the playback signal played from the recording medium. In a color video signal recording and reproducing method in which a reproduced color video signal is obtained by separating and reproducing a luminance signal and a carrier color signal, and then mixing and multiplexing them, memories such as charge transfer elements and random access memories are used during recording and reproduction. The transducer on the recording medium has a scanning time period that is an integral multiple of the track so that the delay time is the same when scanning the same track, and the delay time is different between adjacent tracks. A plurality of delay times are given by sequentially switching the clock pulse frequency of the memory, and furthermore, during playback, a playback delayed carrier color signal separated from the playback signal is used, regardless of the track, so that the sum of the delay amounts during recording and playback is constant. and delay the luminance signal to the luminance signal transmission path of at least one of the recording and reproduction systems by a delay amount near the delay amount of the fixed value of the reproduced carrier color signal. A color video signal recording and reproducing method characterized in that a luminance signal is recorded and reproduced by providing a means for recording and reproducing a luminance signal.