JP2507310B2 - Clock reproduction circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit provided on the receiving side of a TDMA communication system.

[Technical background of the invention and its problems]

In recent years, in fields such as sanitary communication and mobile communication, TDMA
(Time Division Multiple Access) has been attracting attention. On the receiving side of the TDMA-based communication system, burst signals from each transmitting station, which are sequentially received in time series, are sequentially processed to extract demodulated data.

When receiving and demodulating in such a TDMA system, the burst signals received in time series from each transmitting station are not phase-synchronized with the carrier and the clock, so the receiving / demodulating unit receives the burst signals. It is necessary to regenerate the carrier and clock each time. Signals such as a carrier preamble and a BTR preamble are inserted at the beginning of the burst signal to establish synchronization in the carrier and clock reproduction. Since these preambles significantly reduce the amount of data that can be sent by the transmission line, it is desirable that they be as short as possible in time.

Here, looking at the clock signal included in the burst signal from each transmitting station, the frequency of the clock signal is often almost the same between each station, and therefore, the requirements for the BTR preamble period are: , Phase synchronization based on the distance between stations is considered to be the main one. What is required for the phase synchronization of this clock signal is to quickly establish synchronization within the shortest possible BTR period, and to operate as stably as possible once synchronization is established.

However, it is generally difficult to achieve both high-speed operation and stable operation in a clock recovery circuit using a phase-locked loop circuit, resulting in an increase in the BTR preamble period and a large decrease in the amount of transmission data. There was a problem of inviting.

[Object of the Invention]

The present invention has been made to solve such a conventional problem, and at the time of reproducing a clock signal from a burst signal transmitted from a plurality of transmitting stations in a time division multiple access system, establishes synchronization at high speed. It is an object of the present invention to provide a clock recovery circuit capable of achieving stable operation.

[Structure of Invention]

According to the present invention, in a clock regeneration circuit for regenerating a clock signal from a burst signal transmitted from a plurality of transmitting stations in a time division multiple access system in a predetermined transmission order, following reception of the burst signal from the first transmitting station, , When receiving a burst signal from the second transmitting station, the phase of the clock signal of the burst signal previously transmitted from the first transmitting station and the second transmission transmitted subsequent to the burst signal. The phase of the recovered clock signal synchronized with the burst signal from the first transmitting station is phase-shifted according to the information on the phase difference between the phase of the burst signal from the station and the phase of the clock signal of the second transmitting station. From the second transmitting station, the phase of the newly received clock signal from the second transmitting station is approximately the same as the phase of the new recovered clock signal. As match, further phase shifting the phase of the new regenerated clock signal, characterized by reproducing the clock signal of the burst signal from the second transmitting station.

〔The invention's effect〕

According to the present invention, each time a new burst signal is received, the reproduced clock signal is phase-shifted by an amount corresponding to the phase difference from the clock signal reproduced from the immediately preceding received burst signal, whereby the reproduced clock signal is reproduced. The phase of the clock signal is controlled so as to instantly approach the phase of the clock signal included in the reception burst signal. Therefore, when the burst signal is newly received, it is possible to establish the synchronization of the reproduced clock signal at a very high speed.

Further, in the past, in order to speed up the establishment of synchronization, it was necessary to increase the loop gain of the phase-locked loop for clock recovery, and there was the problem that the stability was reduced by that amount. Stable operation can be expected because high-speed synchronization establishment is achieved without raising the speed.

Example of Invention

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention.

In FIG. 1, a burst signal transmitted by the TDMA method and received by the receiving side is input to the input terminal 1 and supplied to the phase difference detection circuit 2. As shown in FIG. 2, the phase difference detection circuit 2 includes a phase comparator 23 for comparing the phases of the burst signal input to the first input terminal 21 and the reproduced clock signal input to the second input terminal 22. And this phase comparator 23
Filters 24 and 25 that receive the output signal of
And an A / D converter 26 for converting the output of the digital signal into a digital signal, the output of the filter 24 is output from the first output terminal 27, and the output signal of the A / D converter 26 is output to the second output terminal 28. Output more. The filters 24 and 25 may be low-pass filters in general, but the characteristics, especially the time constant, of the filter 24 is sufficiently long and the filter 25 is short. That is, the time constant of the filter 24 is selected so as to correspond to, for example, the frequency drift + α of the clock, but since the frequency stability of the clock is generally extremely high, the time constant of the filter 24 may be sufficiently long. On the other hand, when the burst signal is input to the filter 25, the time constant needs to be sufficiently short in order to establish synchronization within a short period, and its value depends on the length of the BTR preamble.

An output signal from the first output terminal 27 of the phase difference detection circuit 2 is supplied to a VCO (voltage controlled oscillator) 3 as a control voltage, and a reproduction clock signal is output from this VCO 3. The reproduced clock signal is phase-shifted by the phase shifter 4 and then supplied to the second input terminal 22 of the phase difference detection circuit 2 and also sent to the output terminal 5.

On the other hand, the memory circuit 7, based on the address signal from the address designation terminal 6, outputs the information of the phase difference between the reproduced clock signals reproduced from the burst signal from each transmitting station to the corresponding two transmitting stations and the two transmitting stations. It is stored in the address determined by the transmission order from the transmitting station. However, in this embodiment, the phase difference information read from the memory circuit 8 by the adder 8 is
A value obtained by adding the phase difference information output as a digital signal from the second output terminal 28 of the phase difference detection circuit 2 is written in the storage circuit 7. Then, based on the address signal from the addressing terminal 6, the phase difference information is read from the two transmitting stations that have transmitted the burst signals one after another and the addresses corresponding to the transmission order, and the phase shifter 4 controls the phase shift amount. It is supplied as a signal.

The phase shifter 4 is configured, for example, as shown in FIG. In FIG. 3, the reproduced clock signal from the VCO 3 of FIG. 1 input to the terminal 31 is branched into two, one is input to the first multiplier 33 via the 90 ° phase shifter 32, and the other is input to the first multiplier 33. 2 multiplier
Entered directly into 34. The output signals of the multipliers 33 and 34 are the adder 3
It is combined in 5, and output from the terminal 36. The first at terminal 37
The phase difference information read out from the memory circuit 7 in the figure is input as a control signal, and the cosine ROM 4 is passed through a cumulative adder 40 including an adder 38 and a latch circuit 39 (D-type flip-flop).
1 and sign ROM 42.

From the ROMs 41 and 42, the cosine- and sine-converted waveforms of the cumulatively added phase difference information are output. These rom 4
The output signals of 1, 42 are converted into analog signals by D / A converters 43, 44, and then supplied to multipliers 33, 34, where they are respectively multiplied by the sine component and cosine component of the reproduced clock signal. With such a configuration, it is possible to obtain a reproduced clock signal that is phase-shifted from the terminal 36 to the terminal 37 by an amount corresponding to the phase difference information.

Next, the operation of the clock recovery circuit of this embodiment will be described. Assuming two transmitting stations A and B, from the first station _A C = cos
_A burst signal is transmitted according to the clock signal of (ω _A t + Δφ _A ), and then from station _B C _B = cos (ω _B t + Δφ A
Consider the case where a burst signal is transmitted according to a clock signal called _B ) and is received.

As described above, generally, Δφ _A ≈ Δφ _B , but since an oscillator with a very high frequency accuracy such as a crystal oscillator or an atomic oscillator is used as a clock source on the transmission side, 10 ⁻⁶ to 10 −10
Ω _A ≈ ω _B holds with an accuracy of ^-10 . Therefore, td = (2
Within the period of π / ω _B ) × 10 ⁴ to (2π / ω _B ) × 10 ⁶ ,
φ _A + Δφ _B is stored with an accuracy of at most several degrees, and Δφd = Δφ _A −Δφ _B is also stored. Therefore, when the burst signals from the A station and B station are continuously received again within the time of about td, the clock recovery system (the phase difference detection circuit 2,
VCO3, phase shifter 4, etc.) operate almost the same.

In such a case, the phase difference Δφd between the reproduced clock signals reproduced from the burst signals from both stations A and B is stored in the storage circuit 7, and immediately after the burst signal from station A is received, station B is received. When it is predicted that the burst signal from the station will be received or it is known in advance, the information of the phase difference Δφd is read from the memory circuit 7 immediately before the burst signal from the station B is received and the phase shifter is read. 4 to supply the recovered clock signal output from VCO3 to Δφ
d only phase shift, a reproduction clock C _BP = cos (ω _A t
+ Δφ _A −Δφd) = cos (ω _B t + Δφ _B ′) (where Δ
φ _B ≈Δφ _B ′) can be brought into a state almost in synchronism. Thereby, the synchronization of the clock recovery circuit can be established in an extremely short time.

FIG. 4 is a block diagram of a clock recovery circuit according to another embodiment of the present invention, in which a switch 10 which is switched by a control signal from a terminal 9 is inserted in the control input side of the phase shifter 4. The switch 10 outputs the phase difference information read from the storage circuit 7 to the phase shifter 4 immediately before the burst signal is input to the input terminal 1.
As a control signal so that the reproduced clock signal can be easily synchronized with the burst signal, and from the second output terminal 28 of the phase difference detection circuit 2 during the preamble period after the burst signal is next input. By supplying the phase difference information to the phase shifter 4 as a control signal, the phase shift amount is corrected again. With such a configuration, the preamble period can be significantly shortened, and the data transmission efficiency can be further improved.

[Brief description of drawings]

1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing details of a phase difference detection circuit, FIG. 3 is a block diagram showing details of a phase shifter, and FIG. FIG. 9 is a block diagram of a clock recovery circuit according to another embodiment of the present invention. 1 ... Burst signal input terminal, 2 ... Phase difference detection circuit,
3 ... Voltage controlled oscillator, 4 ... Phase shifter, 5 ... Reproduced clock signal output terminal, 6 ... Addressing terminal, 7 ... Memory circuit, 8 ... Adder, 9 ... Control signal input terminal, Ten…
... Control input switching terminal of phase shifter.

Claims (1)

(57) [Claims] 1. A clock regenerating circuit for regenerating a clock signal from a burst signal transmitted from a plurality of transmitting stations in a time division multiple access system according to a predetermined transmission sequence, and receiving a burst signal from a first transmitting station. Second
When receiving the burst signal from the first transmitting station, the phase of the clock signal of the burst signal previously transmitted from the first transmitting station and the second signal transmitted subsequent to the burst signal.
The phase of the reproduced clock signal synchronized with the burst signal from the first transmitting station is phase-shifted according to the information on the phase difference between the burst signal from the transmitting station of A new regenerated clock signal that is substantially synchronized with the burst signal from the transmitting station is obtained, and the phase of the newly received burst signal from the second transmitting station and the phase of the new regenerated clock signal substantially match, Further, the clock regenerating circuit is characterized in that the phase of the new regenerated clock signal is phase-shifted to regenerate the clock signal of the burst signal from the second transmitting station.