JP2507287B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2507287B2 JP2507287B2 JP56088999A JP8899981A JP2507287B2 JP 2507287 B2 JP2507287 B2 JP 2507287B2 JP 56088999 A JP56088999 A JP 56088999A JP 8899981 A JP8899981 A JP 8899981A JP 2507287 B2 JP2507287 B2 JP 2507287B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- input terminal
- wiring
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Description
【発明の詳細な説明】 本発明は半導体集積回路に関する。The present invention relates to semiconductor integrated circuits.
以下は、説明の便宜上Ｎ−チャンネルMOSFETを用いた
回路について話を進める。Hereinafter, for convenience of description, a circuit using an N-channel MOSFET will be described.
従来の半導体集積回路における、入力回路保護用の入
力保護回路のレイアウト図を第１図に、第１図の入力ド
ライバーから入力回路までを集中定数を用いて表わした
等価回路図を第２図に示す。従来は、入力端子11に規定
電圧以上の電圧が印加された場合、入力回路13のみなら
ず、入力端子11の周辺に存在する他の回路に与える影響
を小さいものとするため、入力保護回路12は入力端子11
にできるだけ近い位置に設けられていた。しかし、この
構成では、入力保護回路12が入力端子11側に置かれてい
るため、入力保護回路12と、入力回路13間の配線14が長
くなり、配線抵抗及び配線容量が付加する。A layout diagram of an input protection circuit for protecting an input circuit in a conventional semiconductor integrated circuit is shown in FIG. 1, and an equivalent circuit diagram in which the input driver to the input circuit of FIG. 1 are expressed by using lumped constants is shown in FIG. Show. Conventionally, when a voltage higher than a specified voltage is applied to the input terminal 11, the input protection circuit 12 has a small influence on not only the input circuit 13 but also other circuits existing around the input terminal 11. Is the input terminal 11
It was located as close as possible to. However, in this configuration, since the input protection circuit 12 is placed on the input terminal 11 side, the wiring 14 between the input protection circuit 12 and the input circuit 13 becomes long, and wiring resistance and wiring capacitance are added.
第２図において、Zoは入力ドライバーの内部抵抗、12
は入力保護回路、Ｒ1は入力保護抵抗,Q1は入力保護トラ
ンジスター、Ｒ2,C2はそれぞれ配線14による抵抗分と容
量分、Ｃ3は入力回路の容量である。ここで、一般に入
力保護抵抗Ｒ1は保護効果を得るために数ｋΩ、また配
線抵抗Ｒ2は数Ωのオーダーで、入力ドライバーの内部
インピーダンスZoは入力保護抵抗Ｒ1と比較すると十分
に小さいので、第２図は第３図に近似できる。よって第
３図において、入力端子11と入力回路間13の時定数τ1
はτ1＝Ｒ1（Ｃ2＋Ｃ3）となり、配線容量Ｃ2が付加す
る分だけ信号の伝搬が遅くなる。In Fig. 2, Zo is the internal resistance of the input driver, 12
Is an input protection circuit, R 1 is an input protection resistor, Q 1 is an input protection transistor, R 2 and C 2 are the resistance and capacitance of the wiring 14, and C 3 is the capacitance of the input circuit. Here, in general, the input protection resistor R 1 is on the order of several kΩ to obtain a protection effect, and the wiring resistance R 2 is on the order of several Ω, and the internal impedance Zo of the input driver is sufficiently small compared with the input protection resistor R 1 . , FIG. 2 can be approximated to FIG. Therefore, in FIG. 3, the time constant τ 1 between the input terminal 11 and the input circuit 13 is
Becomes τ 1 = R 1 (C 2 + C 3 ), and the signal propagation is delayed by the amount of the wiring capacitance C 2 added.
本発明の目的は、時定数の小さい、すなわち信号伝搬
を高速化する半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit having a small time constant, that is, speeding up signal propagation.
本発明では、入力保護回路を、入力端子と入力回路間
の入力回路側に設ける。この入力保護回路のレイアウト
図を第４図に、第４図を集中定数を用いて等価回路化し
た図を第５図に示す。従来回路図、第２図と比較対応し
やすいように、各定数、記号は第２図のそれと対応して
いるものとする。前述したように、Ｒ1＞＞Ｒ2,R1＞＞Z
oであるので、第５図は第６図のような等価回路に書け
る。第６図において、入力端子と入力回路間の時定数τ
2はτ2＝Ｒ1Ｃ3となる。従来回路の入力端子、入力回路
間の時定数τ1＝Ｒ1（Ｃ2＋Ｃ3）と比較するとτ′＝τ
1−τ2＝Ｒ1Ｃ2だけ時定数が小さくなる。ここでＲ1は
数ｋΩ,C2は数PFのオーダーであるので、本発明で数NS
の信号伝搬速度の短縮が期待できる。In the present invention, the input protection circuit is provided on the input circuit side between the input terminal and the input circuit. A layout diagram of this input protection circuit is shown in FIG. 4, and FIG. 5 is an equivalent circuit diagram of FIG. 4 using lumped constants. It is assumed that the constants and symbols correspond to those in FIG. 2 so as to facilitate comparison with the conventional circuit diagram and FIG. As mentioned above, R 1 >> R 2 , R 1 >> Z
Since it is o, FIG. 5 can be written in an equivalent circuit as shown in FIG. In Fig. 6, the time constant τ between the input terminal and the input circuit
2 becomes τ 2 = R 1 C 3 . Compared with the time constant τ 1 = R 1 (C 2 + C 3 ) between the input terminal and the input circuit of the conventional circuit, τ ′ = τ
The time constant becomes smaller by 1− τ 2 = R 1 C 2 . Here, R 1 is on the order of several kΩ and C 2 is on the order of several PF, so in the present invention several NS
The signal propagation speed can be expected to be shortened.
第１図は従来の半導体集積回路における入力保護回路の
レイアウト図、第２図は、第１図の入力ドライバーと入
力回路間の配線及び回路を集中定数を用いて表わした等
価回路、第３図は、Ｒ1＞＞Ｒ2,R1＞＞Zoの条件のもと
に第２図を書き改めた等価回路である。また、第４図は
本発明における入力保護回路のレイアウト図、第５図
は、第４図の入力ドライバーと入力回路間の配線及び回
路を集中定数を用いて表わした等価回路、第６図はＲ1
＞＞Ｒ2,RR1＞＞Zoの条件のもとに第５図を書き改めた
等価回路図である。 11……入力端子、12……入力保護回路、13……入力回
路、14……配線。FIG. 1 is a layout diagram of an input protection circuit in a conventional semiconductor integrated circuit, and FIG. 2 is an equivalent circuit showing wiring between the input driver and the input circuit of FIG. 1 and a circuit using lumped constants. Is an equivalent circuit obtained by rewriting FIG. 2 under the conditions of R 1 >> R 2 and R 1 >> Zo. Further, FIG. 4 is a layout diagram of an input protection circuit according to the present invention, FIG. 5 is an equivalent circuit showing wiring between the input driver and the input circuit of FIG. 4 and a circuit using lumped constants, and FIG. R 1
5 is an equivalent circuit diagram obtained by rewriting FIG. 5 under the condition of >> R 2 , RR 1 >> Zo. 11 …… input terminal, 12 …… input protection circuit, 13 …… input circuit, 14 …… wiring.
Claims (1)
回路、および前記入力端子から前記入力回路への信号路
に直列に挿入された所定の抵抗値の抵抗を有する入力保
護回路であって前記所定の抵抗値に比して無視できる程
度の抵抗値の配線により前記入力端子と前記入力回路と
の間に接続された入力保護回路を備える半導体集積回路
において、前記入力回路は前記半導体チップの一つの辺
に沿って設けられ、前記入力端子は前記半導体チップの
前記一つの辺とは異なる他の辺に沿って設けられ、か
つ、前記入力保護回路を前記半導体チップの前記一つの
辺に沿って前記入力回路に近接して配置して、前記入力
回路と前記入力保護回路間の配線を、前記入力端子と前
記入力保護回路間の配線よりも短くして、前記入力端子
と前記入力回路間の時定数を前記抵抗の抵抗値と前記入
力回路の入力容量とで実質的に決定したことを特徴とす
る半導体集積回路。1. An input protection circuit having an input terminal, an input circuit, and a resistor having a predetermined resistance value, which is inserted in series in a signal path from the input terminal to the input circuit on a rectangular semiconductor chip. In a semiconductor integrated circuit including an input protection circuit connected between the input terminal and the input circuit by a wiring having a resistance value that is negligible as compared with the predetermined resistance value, the input circuit is the semiconductor chip. The input terminal is provided along one side, the input terminal is provided along another side different from the one side of the semiconductor chip, and the input protection circuit is provided along the one side of the semiconductor chip. Between the input terminal and the input circuit by making the wiring between the input circuit and the input protection circuit shorter than the wiring between the input terminal and the input protection circuit. of The semiconductor integrated circuit being characterized in that substantially determined by the constant and the resistance value of the resistor and the input capacitance of the input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56088999A JP2507287B2 (en) | 1981-06-10 | 1981-06-10 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56088999A JP2507287B2 (en) | 1981-06-10 | 1981-06-10 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57204167A JPS57204167A (en) | 1982-12-14 |
| JP2507287B2 true JP2507287B2 (en) | 1996-06-12 |
Family
ID=13958499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56088999A Expired - Lifetime JP2507287B2 (en) | 1981-06-10 | 1981-06-10 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2507287B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0616558B2 (en) * | 1987-01-28 | 1994-03-02 | 三菱電機株式会社 | Input protection device for semiconductor device |
| US5808343A (en) * | 1996-09-20 | 1998-09-15 | Integrated Device Technology, Inc. | Input structure for digital integrated circuits |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5510149A (en) * | 1978-07-05 | 1980-01-24 | Ntn Toyo Bearing Co Ltd | Resilient roller |
| JPS57152160A (en) * | 1981-03-13 | 1982-09-20 | Mitsubishi Electric Corp | Protective circuit for input |
-
1981
- 1981-06-10 JP JP56088999A patent/JP2507287B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57204167A (en) | 1982-12-14 |
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