JP2507062B2 - Substrate for optical element, manufacturing method thereof and display device - Google Patents

Substrate for optical element, manufacturing method thereof and display device

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Publication number
JP2507062B2
JP2507062B2 JP16300889A JP16300889A JP2507062B2 JP 2507062 B2 JP2507062 B2 JP 2507062B2 JP 16300889 A JP16300889 A JP 16300889A JP 16300889 A JP16300889 A JP 16300889A JP 2507062 B2 JP2507062 B2 JP 2507062B2
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JP
Japan
Prior art keywords
optical element
substrate
manufacturing
electrode
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP16300889A
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Japanese (ja)
Other versions
JPH0327020A (en
Inventor
強 上村
哲 木村
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Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Priority to JP16300889A priority Critical patent/JP2507062B2/en
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Description

【発明の詳細な説明】 産業上の利用分野 本発明は表示素子、光シャッターなどの光学素子に係
わり、特に其の光学素子用基板とその製造法および表示
装置に関わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical element such as a display element and an optical shutter, and more particularly to a substrate for the optical element, a manufacturing method thereof and a display device.

従来の技術 従来の技術を以下、図面を用いて説明する。現在、光
学素子としての応用分野はプリンタ用シャッター、等の
高密度なもの、またはOA用端末としてのワープロ、パソ
コン、テレビ等が挙げられる。
Conventional Technology Conventional technology will be described below with reference to the drawings. Presently, the applied fields as optical elements include high-density ones such as shutters for printers, word processors as OA terminals, personal computers, televisions and the like.

これらの用途は非常に平面化としてのニーズが高いも
のが多く、特に大型表示装置に対してはフラット化が望
まれている。
Many of these applications have very high planarization needs, and flatness is particularly desired for large-sized display devices.

このようにフラットが望まれる中で最も現在注目を集
めているのが液晶素子である。
The liquid crystal element is currently most attracting attention when flatness is desired.

液晶素子は古くは時計、電卓から、最近では大型化が
進み10インチ程度の大きさのOA端末にまでシェアをのば
している。精細度模640X400ドット程度の高精細のディ
スプレイ登場してきている。
Liquid crystal elements are gaining market share from watches and calculators in the old days to OA terminals with a size of about 10 inches due to the recent increase in size. High-definition displays with a resolution of 640 x 400 dots have been introduced.

このような高精細な液晶ディスプレイの殆どはX−Y
マトリクスと呼ばれる電極構成を有する基板からなって
いる。
Most of such high-definition liquid crystal displays are XY
It is composed of a substrate having an electrode structure called a matrix.

X−Yマトリクス構成とは第3図に示すように2枚の
基板21,22に帯状電極23,24がそれぞれ付設されており、
一般にこの帯状電極の一方を走査電極あるいはX電極2
3、もう一方を信号電極あるいはY電極24呼んでいる。
With the XY matrix configuration, as shown in FIG. 3, two substrates 21, 22 are provided with strip electrodes 23, 24, respectively,
Generally, one of the strip electrodes is the scanning electrode or the X electrode 2
3, the other is called the signal electrode or Y electrode 24.

この走査電極には線順次に電圧が印加され、信号電極
にはデータに応じた電圧が印加されることにより表示が
行なわれるのである。
A voltage is applied to the scanning electrodes line-sequentially, and a voltage corresponding to the data is applied to the signal electrodes, so that display is performed.

この走査法ではフリッカーが生じないようにフィール
ド周波数が通常50Hz以上は必要とされており、走査線が
400本の場合には印加される電圧波形の周波数は20kHzと
なりかなりの高周波数の電圧波形となる。
In this scanning method, the field frequency is usually required to be 50 Hz or higher so that flicker does not occur, and the scanning line is
In the case of 400 lines, the frequency of the applied voltage waveform is 20 kHz, which is a fairly high frequency voltage waveform.

発明が解決しようとする課題 しかしながら大面積表示、高精細な表示パネルともな
ると上記のように駆動周波数が高周波となるため従来の
ように電極の抵抗が均一な基板を用いると電圧供給端か
ら遠ざかるに従い電圧波形が鈍ってしまい表示に不均一
が生じるという課題があった。
However, when a large-area display and a high-definition display panel are used, the driving frequency becomes high frequency as described above. Therefore, when a substrate with uniform electrode resistance is used as in the conventional case, the distance from the voltage supply end increases. There is a problem that the voltage waveform becomes dull and the display becomes uneven.

課題を解決するための手段 上記、課題を解決するために電圧供給端より遠ざかる
にしたがい電極の抵抗を下げることにより表示の不均一
性を防ぐ。
Means for Solving the Problems As described above, in order to solve the problems, the nonuniformity of the display is prevented by lowering the resistance of the electrodes as the distance from the voltage supply end increases.

作用 電極抵抗を不均一にすることにより、電圧波形の鈍り
が均一化され、結果として均一な表示を得ることができ
る。
By making the working electrode resistance non-uniform, the dullness of the voltage waveform is made uniform, and as a result, uniform display can be obtained.

実施例 以下本発明の一実施例の光学素子用基板について図面
を参照しながら説明する。
Example A substrate for an optical element according to an example of the present invention will be described below with reference to the drawings.

(実施例1) 通常X−Yマトリクス構成の電極減衰は第4図のよう
な等価回路を考えることによって次式のように与えられ
る。ここで31は液晶層の単位長さ辺りの容量(C1)、32
は液晶層の単位長さ辺りのコンダクタンス(G1)、33は
走査電極の単位長さ辺りの抵抗(R)、34は信号電極の
単位長さ辺りのコンダクタンス(G2)、35は電極長
(L)、36は送信端での電圧(VS)、37は受信端での
電圧(VR)を表している。
(Example 1) The electrode attenuation of a normal XY matrix configuration is given by the following equation by considering an equivalent circuit as shown in FIG. Where 31 is the capacitance per unit length of the liquid crystal layer (C1), 32
Is the conductance per unit length of the liquid crystal layer (G1), 33 is the resistance per unit length of the scanning electrode (R), 34 is the conductance per unit length of the signal electrode (G2), and 35 is the electrode length (L). ), 36 represents the voltage (VS) at the transmitting end, and 37 represents the voltage (VR) at the receiving end.

第4図の等価回路は、一般のはしご型分布RCG回路に
変換でき、C1,G1,G2の等価回路は(1)および(2)式
の様に与えられる。
The equivalent circuit of FIG. 4 can be converted into a general ladder-type distributed RCG circuit, and the equivalent circuits of C 1 , G 1 and G 2 are given by equations (1) and (2).

C=C1G2 2/{(G1+G2+(wC1} (1) G={G1G2(G1+G2)+G2(wC1}/{(G1 +G2} (2) またこのような等価回路に対してv(x,t)=V
(x)exp(iwt)の正弦波電圧が印加された場合、次の
電信方程式が成立する。
C = C 1 G 2 2 / {(G 1 + G 2 ) 2 + (wC 1 ) 2 } (1) G = {G 1 G 2 (G 1 + G 2 ) + G 2 (wC 1 ) 2 } / {( G 1 + G 2 ) 2 } (2) For such an equivalent circuit, v (x, t) = V
When a (x) exp (iwt) sinusoidal voltage is applied, the following telegraph equation holds.

dV2/dx2=(G+iwC)RV (3) (3)式がV(0)=VRでx=0が開放端であるとい
う境界条件下では これより、送信端と受信端での電圧の実効値比すなわち
印加電圧の減衰比VR/VSは となる。また、Gを無視してよい場合、すなわち信号電
極の抵抗値が低く、液晶層の抵抗値が十分高い場合には
C=C1,G1=0となり、(5)式は となる。
dV 2 / dx 2 = (G + iwC) RV (3) Under the boundary condition that the equation (3) is V (0) = VR and x = 0 is the open end. From this, the effective value ratio of the voltage at the transmitting end and the receiving end, that is, the attenuation ratio VR / VS of the applied voltage is Becomes Further, when G can be ignored, that is, when the resistance value of the signal electrode is low and the resistance value of the liquid crystal layer is sufficiently high, C = C 1 and G 1 = 0, and the equation (5) becomes Becomes

(6)式からわかるようにZが一定になるようにL,
C、R,fを変化させても同じ電圧減衰率を与えることにな
る。
As can be seen from formula (6), L, so that Z is constant,
Even if C, R, and f are changed, the same voltage decay rate will be given.

また、幅Wの帯状電極を考えると、 但し、e:液晶の比誘電率、 r:電極の表面抵抗 であり、(7)、(8)式からZは と示され、電圧減衰率は電極幅Wには依存しないことが
わかる。
Further, considering a strip electrode having a width W, Where e: relative permittivity of liquid crystal, r is the surface resistance of the electrode, and Z is calculated from Eqs. (7) and (8). It can be seen that the voltage decay rate does not depend on the electrode width W.

通常マトリクス駆動時には、正弦波形ではなく、矩形
波形を用いており、電圧減衰率の計算はフーリエ変換に
より、正弦波に展開して行なう必要があるが大要は同じ
である。
Normally, when driving a matrix, a rectangular waveform is used instead of a sine waveform, and the voltage attenuation rate needs to be expanded into a sine wave by Fourier transform, but the same is true.

(9)式より、ZはLの関数であり、Zが一定であれ
ば(6)式より、減衰率は一定となる。
From the equation (9), Z is a function of L, and if Z is constant, the attenuation rate is constant from the equation (6).

ZがLに対して一定になるように電極の表面抵抗rを
変化させるためには r=L-2の関数で電極の表面抵抗を小さくする必要があ
る。
In order to change the surface resistance r of the electrode so that Z becomes constant with respect to L, it is necessary to reduce the surface resistance of the electrode by a function of r = L −2 .

実際にはこのように大きな差を電極の送信端と受信端
の間で設けることは、難しいので、実験として送信端で
表面抵抗が10オーム/ロ、受信端で40オーム/ロの電極
を用いた。尚、パネル構成としては液晶を光学素子とし
て選び、90度ツイスト構造を有する、いわゆるTN(ツイ
ステッド・ネマチック)パネルを用いた。パネルのパラ
メーターとしてはL=300mm、e=9,液晶の比抵抗を10
11オーム・cm、セル厚d=5μmとした。この時パネル
の送信端から10kHzの矩形波を印加したところ表面抵抗
が10オーム/ロの均一な抵抗の電極よりも電圧の減衰は
目立たなかった。
In practice, it is difficult to provide such a large difference between the transmitting end and the receiving end of the electrode, so as an experiment, we used an electrode with a surface resistance of 10 ohm / lo at the transmitting end and 40 ohm / lo at the receiving end. I was there. As the panel structure, a so-called TN (twisted nematic) panel having a 90-degree twist structure with liquid crystal selected as an optical element was used. As the parameters of the panel, L = 300mm, e = 9, liquid crystal resistivity 10
The thickness was 11 ohm · cm and the cell thickness d was 5 μm. At this time, when a rectangular wave of 10 kHz was applied from the transmitting end of the panel, the voltage attenuation was less conspicuous than that of a uniform resistance electrode having a surface resistance of 10 ohms / square.

また、このような電極減衰はあまり、小さなパネルで
は目立たず(Lに大きく依存するから)本実験ではLが
150mm以下のパネル(基板の大きさとしては対角8イン
チ以下)にはあまり効果がなかった。
Further, such electrode attenuation is not so noticeable in a small panel (since it largely depends on L), in this experiment, L
It was not very effective for panels of 150 mm or less (diagonal size of 8 inches or less as the size of the substrate).

(実施例2) 前述の表面抵抗が不均一な電極の製法として第1図に
示すように真空中の蒸着源の上を基板が通過して電極を
基板状に形成する工法において基板の通過速度を変化さ
せた。
(Example 2) As a method of manufacturing an electrode having a non-uniform surface resistance as described above, a substrate passing speed over a vapor deposition source in vacuum to form an electrode in a substrate shape as shown in FIG. Was changed.

第1図においてまず、ガラス基板11が蒸着源12(ここ
ではインジウム・スズ酸化物を用いた)を通過するとき
にガラス基板先端から最終端に至るまでに移動速度が1c
m/分から4cm/分になるように連続的に変化させた。ガラ
ス基板の大きさはLが300mm、対角15インチのものを用
いた。蒸着法は電子ビーム法を用い、蒸着時の真空度は
6X10-6Torrであった。その板の移動速度を変化させるこ
とによりITO(インジウム・スズ酸化物)の基板上での
膜厚が変化し、表面抵抗値が変化した。膜厚は1000オン
グストロームから4000オングストローム変化した。
In FIG. 1, when the glass substrate 11 passes through the vapor deposition source 12 (here, indium tin oxide is used), the moving speed is 1c from the front end to the final end of the glass substrate.
It was continuously changed from m / min to 4 cm / min. The glass substrate used had a size L of 300 mm and a diagonal of 15 inches. The evaporation method uses an electron beam method, and the degree of vacuum during evaporation is
It was 6X10 -6 Torr. By changing the moving speed of the plate, the film thickness of ITO (indium tin oxide) on the substrate was changed, and the surface resistance value was changed. The film thickness changed from 1000 angstroms to 4000 angstroms.

この結果、基板の抵抗は先端から、最終端まで10オー
ム/ロから40オーム/ロまで変化した。基板の表面抵抗
値は三端子法により測定した。
As a result, the resistance of the substrate changed from 10 ohms / lo to 40 ohms / lo from the tip to the end. The surface resistance value of the substrate was measured by the three-terminal method.

(実施例3) 表面抵抗が不均一な電極の製造法としてつぎに第2図
に示すような真空中に蒸着源21があり、その上で基板22
が蒸着源に対しある角度θ23で位置しているとき、実施
例2と同様な蒸着源を用いて電子ビーム法により基板上
にITO薄膜を設けた。このときθを30度とした。このと
き蒸着源から基板の最も近い部分の距離d1が300mm、最
も遠い部分の距離d2は600mmになるように基板を傾け
た。蒸着膜厚は距離の2乗で決まるため蒸着源から最も
近いところの表面抵抗が10オーム/ロであったのに対し
て最も遠い位置では40オーム/ロの表面抵抗であった。
(Example 3) As a method for producing an electrode having a non-uniform surface resistance, a vapor deposition source 21 is placed in a vacuum as shown in FIG.
Is positioned at an angle θ23 with respect to the vapor deposition source, an ITO thin film was provided on the substrate by the electron beam method using the vapor deposition source similar to that in Example 2. At this time, θ was set to 30 degrees. At this time, the substrate was tilted so that the distance d1 from the vapor deposition source to the closest portion of the substrate was 300 mm and the distance d2 to the farthest portion was 600 mm. Since the vapor deposition film thickness is determined by the square of the distance, the surface resistance at the position closest to the vapor deposition source was 10 ohms / lot, while at the furthest position it was 40 ohms / lot.

また、用いた基板の大きさはLが600mmのものを用い
た。
The size of the substrate used was L 600 mm.

発明の効果 本発明は電圧の供給端から遠ざかるに従い、電極抵抗
を下げることにより、電圧減衰をやわらげ、表面の不均
一性を防ぐという効果を有する。
EFFECTS OF THE INVENTION The present invention has the effect of reducing the electrode resistance as the distance from the voltage supply end increases, thereby softening the voltage attenuation and preventing the unevenness of the surface.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例2における電極抵抗を不均一化
するための装置の概略図、第2図は本発明の実施例3に
おける電極抵抗を不均一化するための装置の概略図、第
3図は従来のX−Yマトリクスの電極構成図、第4図は
本発明の電極減衰モデルをたてるためのモデル図であ
る。 11……基板、12……蒸着源。
FIG. 1 is a schematic view of an apparatus for making the electrode resistance non-uniform in Embodiment 2 of the present invention, and FIG. 2 is a schematic view of the apparatus for making the electrode resistance non-uniform in Embodiment 3 of the present invention. FIG. 3 is a conventional XY matrix electrode configuration diagram, and FIG. 4 is a model diagram for establishing an electrode attenuation model of the present invention. 11 ... Substrate, 12 ... Deposition source.

Claims (16)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電圧印加手段として帯状電極を有し、前記
帯状電極の抵抗が電圧供給端から遠ざかるに従い小さく
なることを特徴とする光学素子用基板。
1. A substrate for an optical element, which has a strip-shaped electrode as a voltage applying means, and the resistance of the strip-shaped electrode becomes smaller as the distance from the voltage supply end increases.
【請求項2】基板の対角方向の長さが8インチ以上であ
ることを特徴とする請求項(1)記載の光学素子用基
板。
2. The optical element substrate according to claim 1, wherein the length of the substrate in the diagonal direction is 8 inches or more.
【請求項3】光学素子がマトリクス構造の電極構成を有
することを特徴とする請求項(1)または(2)記載の
光学素子用基板。
3. The optical element substrate according to claim 1, wherein the optical element has a matrix-structured electrode structure.
【請求項4】光学素子が液晶素子であることを特徴とす
る請求項(1),(2)または(3)記載の光学素子用
基板。
4. The optical element substrate according to claim 1, wherein the optical element is a liquid crystal element.
【請求項5】基板上に物質を堆積させて前記基板上に帯
状電極を有する電圧印加手段を設ける製造方法におい
て、基板に物質を堆積する際の基板の移動速度を変化さ
せることによって前記帯状電極の抵抗が電圧供給端から
遠ざかるに従い小さくなるようにすることを特徴とする
光学素子用基板の製造方法。
5. A manufacturing method for depositing a substance on a substrate to provide voltage applying means having a strip electrode on the substrate, wherein the strip electrode is formed by changing a moving speed of the substrate when depositing the substance on the substrate. The method for manufacturing an optical element substrate is characterized in that the resistance is reduced as the distance from the voltage supply end increases.
【請求項6】基板の対角方向の長さが8インチ以上であ
ることを特徴とする請求項(5)記載の光学素子用基板
の製造方法。
6. The method for manufacturing an optical element substrate according to claim 5, wherein the length of the substrate in the diagonal direction is 8 inches or more.
【請求項7】光学素子がマトリクス構造の電極構成を有
することを特徴とする請求項(5)または(6)記載の
光学素子用基板の製造方法。
7. The method of manufacturing an optical element substrate according to claim 5, wherein the optical element has an electrode structure having a matrix structure.
【請求項8】光学素子が液晶素子であることを特徴とす
る請求項(5),(6)または(7)記載の光学素子用
基板の製造方法。
8. The method for manufacturing an optical element substrate according to claim 5, wherein the optical element is a liquid crystal element.
【請求項9】基板上に物質を堆積させて前記基板上に帯
状電極を有する電圧印加手段を設ける製造方法におい
て、物質の堆積される方向に対して基板を斜めに配置す
ることによって前記帯状電極の抵抗が電圧供給端から遠
ざかるに従い小さくなるようにすることを特徴とする光
学素子用基板の製造方法。
9. A manufacturing method for depositing a substance on a substrate to provide voltage applying means having a strip electrode on the substrate, wherein the substrate is arranged obliquely with respect to a deposition direction of the substance. The method for manufacturing an optical element substrate is characterized in that the resistance is reduced as the distance from the voltage supply end increases.
【請求項10】基板の対角方向の長さが8インチ以上で
あることを特徴とする請求項(9)記載の光学素子用基
板の製造方法。
10. The method for manufacturing an optical element substrate according to claim 9, wherein the length of the substrate in the diagonal direction is 8 inches or more.
【請求項11】光学素子がマトリクス構造の電極構成を
有することを特徴とする請求項(9)または(10)記載
の光学素子用基板の製造方法。
11. The method of manufacturing an optical element substrate according to claim 9, wherein the optical element has a matrix-structured electrode structure.
【請求項12】光学素子が液晶素子であることを特徴と
する請求項(9),(10)または(11)記載の光学素子
用基板の製造方法。
12. The method for manufacturing an optical element substrate according to claim 9, wherein the optical element is a liquid crystal element.
【請求項13】電圧印加手段として帯状電極を有し、前
記帯状電極の抵抗が電圧供給端から遠ざかるに従い小さ
くなる光学素子用基板を用いたことを特徴とする表示装
置。
13. A display device comprising an optical element substrate having a strip electrode as a voltage applying means, and the resistance of the strip electrode becoming smaller as the distance from the voltage supply end increases.
【請求項14】基板の対角方向の長さが8インチ以上で
ある光学素子用基板を用いたことを特徴とする請求項
(13)記載の表示装置。
14. The display device according to claim 13, wherein an optical element substrate having a diagonal length of 8 inches or more is used.
【請求項15】光学素子にマトリクス構造の電極構成を
有する光学素子用基板を用いたことを特徴とする請求項
(13)または(14)記載の表示装置。
15. The display device according to claim 13, wherein an optical element substrate having a matrix-structured electrode structure is used as the optical element.
【請求項16】光学素子が液晶素子であることを特徴と
する請求項(13),(14)または(15)記載の表示装
置。
16. The display device according to claim 13, wherein the optical element is a liquid crystal element.
JP16300889A 1989-06-26 1989-06-26 Substrate for optical element, manufacturing method thereof and display device Expired - Lifetime JP2507062B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16300889A JP2507062B2 (en) 1989-06-26 1989-06-26 Substrate for optical element, manufacturing method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16300889A JP2507062B2 (en) 1989-06-26 1989-06-26 Substrate for optical element, manufacturing method thereof and display device

Publications (2)

Publication Number Publication Date
JPH0327020A JPH0327020A (en) 1991-02-05
JP2507062B2 true JP2507062B2 (en) 1996-06-12

Family

ID=15765444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16300889A Expired - Lifetime JP2507062B2 (en) 1989-06-26 1989-06-26 Substrate for optical element, manufacturing method thereof and display device

Country Status (1)

Country Link
JP (1) JP2507062B2 (en)

Also Published As

Publication number Publication date
JPH0327020A (en) 1991-02-05

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