JP2504924B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a carrier tape, and more particularly to a means for preventing electrostatic breakdown during the manufacturing process. .

[0002]

2. Description of the Related Art Tape Automated B is one of the wireless bonding methods for mounting semiconductor chips.
There is an oncoming (hereinafter referred to as "T.A.B.") method. The T. A. B. In the method, a finger-shaped lead conductor obtained by etching a metal foil is used for connection, and this finger-shaped lead conductor is formed on a carrier tape made of an insulating resin film.

FIG. 3 is a top view of a conventional example. A.
B. It is for explaining the law. The long carrier tape 1 has a plurality of holes 2 and a plurality of lead conductor patterns 4, and the lead conductor patterns 4 form lead terminals.
It is formed by etching a metal film such as a copper foil. A bump (not shown) on the semiconductor chip 3 is opposed to the tip of the lead conductor pattern 4 on the hole 2 side for bonding.
Thus, T. A. B. When the semiconductor chip 3 is mounted by the method to create a device, electrostatic charges are accumulated on the device surface due to contact and friction with the reel on which the carrier tape 1 is wound and other devices, and the potential of the device rises. When the lead conductor pattern 4 on the device comes into contact with another object having a potential different from the surface of the device, the potential difference destroys the insulating film in the semiconductor chip 3 and loses the function as a film carrier device.

In order to prevent electrostatic breakdown of such a film carrier device, as shown in FIG. 4, charged particles are sprayed onto each device on the carrier tape 1 or the device and the conductive material are brought into contact with each other. The charge was being removed.

[0005]

As shown in FIG. 4, there is a method of discharging electricity by spraying charged particles on each device of the carrier tape 1 or by contacting the device with a conductive material. Although it is effective to carry out each device surely, if it is continuously formed on a long carrier tape 1 like a film carrier device and flows through the process at a high speed, surely remove all charges from the devices. Is difficult Therefore, only one of the adjacent devices is discharged, and the other remains charged, resulting in a potential difference between the devices, causing electrostatic breakdown during the manufacturing process, resulting in a defect.

[0006] In addition, as for the above-mentioned problems,
No. 17737, an electrostatic breakdown preventing conductor pattern 1 for electrically integrating a plurality of mounted semiconductor chips 3 is disclosed.
A method is described in which 0 is formed on the carrier tape 1 and the plurality of semiconductor chips 3 are neutralized at once.

However, in Japanese Utility Model Laid-Open No. 61-17737, as shown in FIG. 5, since all the electrodes of the semiconductor chip 3 are connected to the electrostatic breakdown preventing conductor pattern 10,
In order to perform the device test, there is a problem that the electrostatic breakdown preventing conductor pattern 10 must be separated from the semiconductor chip 3. FIG. 5 is a top view showing another conventional example, in which 2 is a hole and 4 is a lead conductor pattern.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of semiconductor chips are provided with a plurality of lead conductor patterns connected to electrodes of the semiconductor chips in a longitudinal direction. In a method for manufacturing a semiconductor device mounted on a formed carrier tape, the carrier is electrically connected to and integrated with a lead conductor pattern of the lead conductor patterns that is connected to a ground electrode of the semiconductor chip. A step of forming a conductor pattern for preventing electrostatic breakdown at the edge in the long axis direction of the tape, a step of mounting the semiconductor chip on the carrier tape, and connecting the electrode of the semiconductor chip and the lead conductor pattern, Before separating the electrostatic breakdown preventing conductor pattern from the semiconductor chip, a test of the semiconductor chip and the electrostatic breakdown preventing conductor pattern It is characterized in that a step of performing a neutralization by contacting the conductive material jig.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of semiconductor chips are provided with a plurality of lead conductor patterns connected to electrodes of the semiconductor chips in a longitudinal direction. In a method of manufacturing a semiconductor device mounted on a tape, between the lead conductor patterns on the carrier tape so as to be electrically connected to a lead conductor pattern connected to a ground electrode of the semiconductor chip among the lead conductor patterns. A step of forming an integrated electrostatic breakdown preventing conductor pattern on the lead conductor pattern separation region and the longitudinal edge of the carrier tape;
The step of mounting the semiconductor chip on the carrier tape, connecting the electrode of the semiconductor chip and the electrostatic breakdown preventing lead conductor pattern, and separating the conductor pattern connected to the ground electrode of the semiconductor chip from the semiconductor chip The method is characterized by further comprising a step of performing a test of the semiconductor chip and a static electricity removal by bringing a conductive material jig into contact with the electrostatic breakdown preventing conductor pattern.

[0010]

When the conductive pattern for preventing electrostatic breakdown is discharged by forming the lead conductive pattern and the conductive pattern for preventing electrostatic breakdown on the carrier tape as described above, all the devices can be discharged almost uniformly. Moreover, the potential of the ground electrode of the semiconductor chip can be lowered.

[0011]

EXAMPLES The present invention will be described in detail below with reference to examples, but the present invention is not limited thereto.

FIG. 1 is a top view showing an embodiment of the present invention.

The manufacturing process of a semiconductor device according to an embodiment of the present invention will be described below.

First, a plurality of holes 6 are formed in the long axis direction of a long carrier tape 5, and a lead conductor pattern 7 serving as a lead terminal is formed around each hole 6 in the carrier tape 5.
It is formed by etching a metal film such as a copper foil adhered to. In addition, the carrier tape and the lead conductor pattern separation area between the lead conductor patterns 7 on the carrier tape 5 and the carrier tape are electrically connected to the lead conductor 7a of the lead conductor pattern 7 which is connected to the ground electrode of the semiconductor chip 8. The integrated conductor patterns 9a and 9b for preventing electrostatic breakdown are formed on the edge portion of the electrode 5.

Next, one semiconductor chip 8 is set for each hole 6, and a bump (not shown) on the semiconductor chip 8 and a tip of the lead conductor pattern 7 on the hole 6 side are opposed to each other for bonding. Then, a device is created, and the device is tested before the conductor pattern 9 is separated from the semiconductor chip 8. Then, the conductor pattern 9 is brought into contact with a jig or the like made of a high-resistance conductive material, and electrostatic charges accumulated on the device surface due to contact with the reel and other devices and friction during the mounting process are discharged from the device. It is possible to remove charges from all devices substantially uniformly, and at the same time reduce the potential of the ground electrode of the semiconductor chip 8.

When this example was applied to carrier tapes having widths of 35 mm and 70 mm, electrostatic breakdown of the device during the manufacturing process was significantly reduced. In the present embodiment, the discharge conductor pattern 9 is formed so as to surround the lead conductor pattern 7 in three directions. However, the present invention is not limited to this, and the lead conductor pattern 7 is formed as shown in FIG.
You may form so that it may surround four sides.

[0017]

As described above in detail, by using the present invention, it is possible to lower the potential of the ground electrode of the semiconductor chip and alleviate the potential imbalance on the plane in the semiconductor chip. It is possible to prevent electrostatic breakdown during the device manufacturing process.

Further, the manufactured individual devices can be tested without disconnecting the conductor pattern for preventing electrostatic breakdown, and static eliminator after the test can be removed without adding a special step. . Therefore, the present invention contributes to high efficiency of the highly reliable semiconductor device manufacturing process.

[Brief description of drawings]

FIG. 1 is a top view of an embodiment of the present invention.

FIG. 2 is a top view of another embodiment of the present invention.

FIG. 3 is a top view of a conventional example.

FIG. A. B. It is a figure which shows the device static elimination method by the method.

FIG. 5 is a top view of another conventional example.

[Explanation of symbols]

 5 carrier tape 6 holes 7, 7a lead conductor pattern 8 semiconductor chip 9, 9a, 9b conductor pattern

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-5652 (JP, A) JP-A-61-90453 (JP, A) Actually-opened JP-A-61-17737 (JP, U)

Claims (2)

(57) [Claims] 1. A semiconductor device in which a plurality of semiconductor chips are mounted on a carrier tape having a plurality of lead conductor patterns connected to electrodes of the semiconductor chips and formed in a longitudinal direction, wherein Inside electrically connected to the lead conductor pattern connected to the ground electrode of the semiconductor chip,
A step of forming a conductor pattern for preventing electrostatic breakdown on the longitudinal edge of the carrier tape so as to be integrated; mounting the semiconductor chip on the carrier tape; and electrodes of the semiconductor chip and the lead conductor pattern And the step of connecting with, and before removing the electrostatic breakdown preventing conductor pattern from the semiconductor chip, the semiconductor chip is tested and static electricity removing is performed by bringing a conductive material jig into contact with the electrostatic breakdown preventing conductor pattern. A method of manufacturing a semiconductor device, comprising the steps of: 2. A method for manufacturing a semiconductor device, comprising: mounting a plurality of semiconductor chips on a carrier tape formed with a plurality of lead conductor patterns connected to electrodes of the semiconductor chips in a longitudinal direction. The lead conductor pattern separation region between the lead conductor patterns on the carrier tape and the long axis direction of the carrier tape are electrically connected to the lead conductor pattern connected to the ground electrode of the semiconductor chip in the conductor pattern. A step of forming an integrated electrostatic breakdown preventing conductor pattern on the edge portion, a step of mounting the semiconductor chip on the carrier tape, and connecting an electrode of the semiconductor chip and the lead conductor pattern, Before the conductor pattern for preventing electrostatic damage is separated from the semiconductor chip, the semiconductor chip is tested and the electrostatic damage is prevented. 2. A method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing static electricity by bringing a conductive material jig into contact with the breakage preventing conductor pattern.