JP2000012776A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JP2000012776A JP2000012776A JP10174301A JP17430198A JP2000012776A JP 2000012776 A JP2000012776 A JP 2000012776A JP 10174301 A JP10174301 A JP 10174301A JP 17430198 A JP17430198 A JP 17430198A JP 2000012776 A JP2000012776 A JP 2000012776A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- capacitor
- semiconductor device
- conductive film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、容量を含む半導体
装置を製造する方法に関するものである。The present invention relates to a method for manufacturing a semiconductor device including a capacitor.
【0002】[0002]
【従来の技術】半導体装置の製造においては、半導体基
板上にトランジスタ素子や抵抗といった種々の回路要素
と共にしばしばコンデンサ(ここでは容量ともいう)が
形成される。図4は半導体装置における容量形成箇所の
典型例を示す要部断面図である。図4に示したように、
半導体装置102では、例えばシリコンから成る半導体
基板104上にまずフィールド酸化膜106が形成さ
れ、その上に、容量108が形成される。容量108
は、下部電極110、誘電膜112、ならびに上部電極
114から成り、上記フィールド酸化膜106の上に、
アルミニウムなどの導電材料から成る下部電極110が
形成され、その上に誘電材料から成る誘電膜112が形
成され、さらにその上にアルミニウムなどの導電材料か
ら成る上部電極114が形成される。2. Description of the Related Art In manufacturing a semiconductor device, a capacitor (also referred to as a capacitance here) is often formed on a semiconductor substrate together with various circuit elements such as a transistor element and a resistor. FIG. 4 is a cross-sectional view of a main part showing a typical example of a capacitance forming portion in a semiconductor device. As shown in FIG.
In the semiconductor device 102, a field oxide film 106 is first formed on a semiconductor substrate 104 made of, for example, silicon, and a capacitor 108 is formed thereon. Capacity 108
Is composed of a lower electrode 110, a dielectric film 112, and an upper electrode 114. On the field oxide film 106,
A lower electrode 110 made of a conductive material such as aluminum is formed, a dielectric film 112 made of a dielectric material is formed thereon, and an upper electrode 114 made of a conductive material such as aluminum is formed thereon.
【0003】[0003]
【発明が解決しようとする課題】しかし、従来、このよ
うな半導体装置102を製造する際に、容量リークによ
り、必要な静電容量を備えた容量108を形成できない
場合があり、製造歩留りの低下を招いていた。特に、図
5の回路図に示したように、容量108の一端(上部電
極114)が、半導体基板104上に形成されたポリシ
リコンによる高抵抗116の一端に接続されているよう
な場合に、この問題がしばしば発生していた。However, conventionally, when manufacturing such a semiconductor device 102, there is a case where a capacitor 108 having a required capacitance cannot be formed due to a capacity leak, and the manufacturing yield is reduced. Was invited. In particular, as shown in the circuit diagram of FIG. 5, when one end (upper electrode 114) of the capacitor 108 is connected to one end of a high resistance 116 made of polysilicon formed on the semiconductor substrate 104, This problem often occurred.
【0004】そこで本発明の発明者はその原因を特定す
べく不良となった容量形成箇所を詳細に調べたところ、
誘電膜112に放電跡が観察され、不良発生の原因は、
製造途中に容量108に電荷が異常に蓄積し、蓄積した
電荷が誘電膜112を通じて一時に放電することにある
と判明した。また、電荷の蓄積は、半導体基板104上
でのアルミニウムのエッチング工程や、パッシベーショ
ン膜の成長工程で発生するものと考えられる。[0004] The inventor of the present invention examined the defective capacitor formation portion in detail to identify the cause, and found that
Discharge traces are observed on the dielectric film 112.
It has been found that the charge is abnormally accumulated in the capacitor 108 during the manufacturing, and the accumulated charge is temporarily discharged through the dielectric film 112. It is considered that charge accumulation occurs in the step of etching aluminum on the semiconductor substrate 104 and the step of growing a passivation film.
【0005】本発明の目的は、このような放電による不
良容量の発生を防止した半導体装置の製造方法を提供す
ることにある。An object of the present invention is to provide a method of manufacturing a semiconductor device in which the occurrence of defective capacity due to such discharge is prevented.
【0006】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため、半導体基板上に、導電材料から成る第1の導
電膜を形成し、前記第1の導電膜の上に誘電材料から成
る誘電膜を形成し、前記誘電膜の上に導電材料から成る
第2の導電膜を形成して前記半導体基板上に容量を構成
する半導体装置の製造方法であって、前記第2の導電膜
を前記第1の導電膜に電気的に接続する、導電材料から
成る配線を前記半導体基板上に形成する工程と、前記半
導体基板についての1つまたは複数の工程を行った後、
前記配線を切断する工程とを含むことを特徴とする。According to the present invention, in order to achieve the above object, a first conductive film made of a conductive material is formed on a semiconductor substrate, and a first conductive film made of a dielectric material is formed on the first conductive film. A method of manufacturing a semiconductor device in which a dielectric film is formed, a second conductive film made of a conductive material is formed on the dielectric film, and a capacitor is formed on the semiconductor substrate. A step of forming a wiring made of a conductive material over the semiconductor substrate to be electrically connected to the first conductive film, and performing one or more steps of the semiconductor substrate;
Cutting the wiring.
【0007】すなわち、本発明では、第2の導電膜を第
1の導電膜に接続する、導電材料から成る配線を半導体
基板上に形成し、その後、例えば製造工程の最終段階
で、この配線を切断する。したがって、製造途中では、
上記第1および第2の導電膜および誘電膜から成る容量
に電荷が蓄積しても、その電荷は上記配線を通じて直ち
に放電される。その結果、誘電膜を通じた放電による不
良容量の発生を回避でき、製造歩留りの低下を防止でき
る。That is, in the present invention, a wiring made of a conductive material for connecting the second conductive film to the first conductive film is formed on a semiconductor substrate, and then, for example, at the final stage of the manufacturing process, this wiring is formed. Disconnect. Therefore, during production,
Even if electric charges are accumulated in the capacitance formed by the first and second conductive films and the dielectric film, the electric charges are immediately discharged through the wiring. As a result, it is possible to avoid the occurrence of defective capacitance due to discharge through the dielectric film, and to prevent a reduction in manufacturing yield.
【0008】[0008]
【発明の実施の形態】次に本発明の実施の形態例につい
て図面を参照して説明する。図1は本発明による半導体
装置の製造方法の一例を説明するための平面図、図2お
よび図3は実施の形態例の半導体装置の製造方法により
製造した半導体装置の要部を示す回路図である。なお、
図中、図4、図5と同一の要素には同一の符号が付され
ている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view for explaining an example of a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing main parts of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the embodiment. is there. In addition,
In the drawing, the same elements as those in FIGS. 4 and 5 are denoted by the same reference numerals.
【0009】図1に示した半導体装置2の容量108は
従来と同様に製造される。すなわち、図4に示したよう
に、例えばシリコンから成る半導体基板104上にまず
フィールド酸化膜106が形成され、その上に、下部電
極110、誘電膜112、ならびに上部電極114がこ
の順番で順次形成される。なお、下部電極110は不図
示の箇所で半導体基板104(グランド)に電気的に接
続されている。The capacitance 108 of the semiconductor device 2 shown in FIG. 1 is manufactured in a conventional manner. That is, as shown in FIG. 4, a field oxide film 106 is first formed on a semiconductor substrate 104 made of, for example, silicon, and a lower electrode 110, a dielectric film 112, and an upper electrode 114 are sequentially formed thereon in this order. Is done. The lower electrode 110 is electrically connected to the semiconductor substrate 104 (ground) at a location (not shown).
【0010】その後、本実施の形態例では、図1に示し
たように、上部電極114(本発明に係わる第2の導電
膜)を半導体基板104、したがって下部電極110に
電気的に接続する配線14が形成される。この配線14
の材料としては例えばアルミニウムを用いることができ
る。また、本実施の形態例では、この配線14を形成す
る際に、配線14の異なる箇所に接続する第1および第
2のパッド16,18が同時に形成される。Thereafter, in this embodiment, as shown in FIG. 1, a wiring for electrically connecting the upper electrode 114 (the second conductive film according to the present invention) to the semiconductor substrate 104, and thus to the lower electrode 110. 14 are formed. This wiring 14
For example, aluminum can be used as the material. Further, in the present embodiment, when the wiring 14 is formed, the first and second pads 16 and 18 connected to different portions of the wiring 14 are formed simultaneously.
【0011】つづいて、本実施の形態例では、図2に示
したように、一端が上記上部電極114に接続されたポ
リシリコンから成る高抵抗116(図1には示さず)が
形成され、さらに、半導体基板104上で、アルミニウ
ムのエッチングやパッシベーション膜の成長などを行っ
て種々の素子などが形成される。その後、製造工程の最
終段階としてウェハーテストが行われ、その際、ウェハ
ープローブ針を上記第1および第2のパッド16,18
に当てて電圧を印加し、第1および第2のパッド16,
18間に通電して、配線14が溶断される。図3はこの
工程で配線14が溶断された後の状態を示し、この状態
で容量108は本来の機能を発揮するようになる。Then, in this embodiment, as shown in FIG. 2, a high resistance 116 (not shown in FIG. 1) made of polysilicon having one end connected to the upper electrode 114 is formed. Further, various elements are formed on the semiconductor substrate 104 by etching aluminum, growing a passivation film, and the like. Thereafter, a wafer test is performed as the final stage of the manufacturing process. At this time, a wafer probe needle is connected to the first and second pads 16 and 18.
To the first and second pads 16,
The wiring 14 is blown by applying a current between the wires 18. FIG. 3 shows a state after the wiring 14 has been blown in this step. In this state, the capacitor 108 exhibits its original function.
【0012】したがって、本実施の形態例の半導体装置
の製造方法では、製造途中で、容量108に電荷が蓄積
しても、その電荷は上記配線14を通じて直ちに放電さ
れる。その結果、誘電膜112(図4)を通じた放電に
よる不良容量の発生を回避でき、製造歩留りの低下を防
止できる。Therefore, in the method of manufacturing a semiconductor device according to the present embodiment, even if a charge is accumulated in the capacitor 108 during the manufacture, the charge is immediately discharged through the wiring 14. As a result, it is possible to avoid the occurrence of defective capacitance due to the discharge through the dielectric film 112 (FIG. 4), and it is possible to prevent a reduction in manufacturing yield.
【0013】以上、本発明について実施の形態例をもと
に説明したが、これはあくまでも一例であり、本発明は
この例に限定されることなく種々の形態で実施すること
ができる。例えば、上記本実施の形態例では、配線14
を通電により溶断するとしたが、選択的エッチングによ
り配線14を切断することも無論可能である。その場合
には、第1および第2のパッド16,18は形成する必
要がなくなる。As described above, the present invention has been described based on the embodiment. However, this is merely an example, and the present invention can be implemented in various forms without being limited to this example. For example, in the present embodiment, the wiring 14
Is cut by energization, but it is of course possible to cut the wiring 14 by selective etching. In that case, the first and second pads 16 and 18 do not need to be formed.
【0014】[0014]
【発明の効果】以上説明したように本発明は、半導体基
板上に、導電材料から成る第1の導電膜を形成し、前記
第1の導電膜の上に誘電材料から成る誘電膜を形成し、
前記誘電膜の上に導電材料から成る第2の導電膜を形成
して前記半導体基板上に容量を構成する半導体装置の製
造方法であって、前記第2の導電膜を前記第1の導電膜
に電気的に接続する、導電材料から成る配線を前記半導
体基板上に形成する工程と、前記半導体基板についての
1つまたは複数の工程を行った後、前記配線を切断する
工程とを含むことを特徴とする。As described above, according to the present invention, a first conductive film made of a conductive material is formed on a semiconductor substrate, and a dielectric film made of a dielectric material is formed on the first conductive film. ,
A method of manufacturing a semiconductor device in which a second conductive film made of a conductive material is formed on the dielectric film to form a capacitor on the semiconductor substrate, wherein the second conductive film is formed of the first conductive film Forming a wiring made of a conductive material on the semiconductor substrate, and performing one or more steps on the semiconductor substrate, and then cutting the wiring. Features.
【0015】したがって、本発明の半導体装置の製造方
法では、第2の導電膜を第1の導電膜に接続する、導電
材料から成る配線を半導体基板上に形成し、その後、例
えば製造工程の最終段階で、この配線を切断する。した
がって、製造途中では、上記第1および第2の導電膜お
よび誘電膜から成る容量に電荷が蓄積しても、その電荷
は上記配線を通じて直ちに放電される。その結果、誘電
膜を通じた放電による不良容量の発生を回避でき、製造
歩留りの低下を防止できる。Therefore, in the method of manufacturing a semiconductor device according to the present invention, a wiring made of a conductive material for connecting the second conductive film to the first conductive film is formed on the semiconductor substrate. At this stage, this wiring is cut. Therefore, during manufacture, even if electric charge is accumulated in the capacitance formed by the first and second conductive films and the dielectric film, the electric charge is immediately discharged through the wiring. As a result, it is possible to avoid the occurrence of defective capacitance due to discharge through the dielectric film, and to prevent a reduction in manufacturing yield.
【図1】本発明による半導体装置の製造方法の一例を説
明するための平面図である。FIG. 1 is a plan view for explaining an example of a method for manufacturing a semiconductor device according to the present invention.
【図2】実施の形態例の半導体装置の製造方法により製
造した半導体装置の要部を示す回路図である。FIG. 2 is a circuit diagram showing a main part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment;
【図3】実施の形態例の半導体装置の製造方法により製
造した半導体装置の要部を示し、配線切断後の状態を示
す回路図である。FIG. 3 is a circuit diagram showing a main part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment, and showing a state after wiring is cut;
【図4】従来の半導体装置における容量形成箇所の典型
例を示す要部断面図である。FIG. 4 is a cross-sectional view of a main part showing a typical example of a capacitance forming portion in a conventional semiconductor device.
【図5】図4の半導体装置に形成された容量の周辺を示
す回路図である。FIG. 5 is a circuit diagram illustrating a periphery of a capacitor formed in the semiconductor device of FIG. 4;
2,102……半導体装置、104……半導体基板、1
06……フィールド酸化膜、110……下部電極、11
2……誘電膜、114……上部電極、14……配線、1
6……第1のパッド、18……第2のパッド、116…
…高抵抗、108……容量。2, 102: semiconductor device; 104: semiconductor substrate, 1
06 ... field oxide film, 110 ... lower electrode, 11
2 ... dielectric film, 114 ... upper electrode, 14 ... wiring, 1
6 first pad, 18 second pad, 116
... high resistance, 108 ... capacity.
Claims (11)
の導電膜を形成し、前記第1の導電膜の上に誘電材料か
ら成る誘電膜を形成し、前記誘電膜の上に導電材料から
成る第2の導電膜を形成して前記半導体基板上に容量を
構成する半導体装置の製造方法であって、 前記第2の導電膜を前記第1の導電膜に電気的に接続す
る、導電材料から成る配線を前記半導体基板上に形成す
る工程と、 前記半導体基板についての1つまたは複数の工程を行っ
た後、前記配線を切断する工程と、 を含むことを特徴とする半導体装置の製造方法。1. A semiconductor device comprising: a first substrate made of a conductive material;
Forming a conductive film of a dielectric material on the first conductive film, forming a second conductive film of a conductive material on the dielectric film, and forming a conductive film on the semiconductor substrate. A method of manufacturing a semiconductor device forming a capacitor, wherein a step of electrically connecting the second conductive film to the first conductive film and forming a wiring made of a conductive material on the semiconductor substrate; A step of cutting the wiring after performing one or more steps on the semiconductor substrate.
に電流を流して前記配線を溶断することを特徴とする請
求項1記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of cutting the wiring, a current is applied to the wiring to blow the wiring.
で行うことを特徴とする請求項2記載の半導体装置の製
造方法。3. The method according to claim 2, wherein the cutting of the wiring is performed in a wafer test process.
よび第2のパッドを前記半導体基板上に形成する工程を
含み、前記配線を切断する工程では、前記第1および第
2のパッド間に電圧を印加して前記配線に電流を流すこ
とを特徴とする請求項2記載の半導体装置の製造方法。4. A step of forming first and second pads connected to different portions of the wiring on the semiconductor substrate, wherein the step of cutting the wiring includes a step between the first and second pads. 3. The method according to claim 2, wherein a current is applied to the wiring by applying a voltage.
印加にはウェハープローブ針を用いることを特徴とする
請求項4記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein a voltage is applied to the first and second pads using a wafer probe needle.
ッチングにより前記配線を切断することを特徴とする請
求項1記載の半導体装置の製造方法。6. The method according to claim 1, wherein in the step of cutting the wiring, the wiring is cut by selective etching.
ウムのエッチング工程およびパッシベーション膜の成長
工程のいずれ一方または両方を含むことを特徴とする請
求項1記載の半導体装置の製造方法。7. The method according to claim 1, wherein the one or more steps include one or both of an aluminum etching step and a passivation film growing step.
特徴とする請求項1記載の半導体装置の製造方法。8. The method according to claim 1, wherein the wiring is made of aluminum.
形成された高抵抗の一端に接続されていることを特徴と
する請求項1記載の半導体装置の製造方法。9. The method according to claim 1, wherein the second conductive film is connected to one end of a high resistance formed on the semiconductor substrate.
されていることを特徴とする請求項9記載の半導体装置
の製造方法。10. The method according to claim 9, wherein said high resistance is formed of polysilicon.
の間には、フィールド酸化膜が形成されていることを特
徴とする請求項1記載の半導体装置の製造方法。11. The method according to claim 1, wherein a field oxide film is formed between the semiconductor substrate and the first conductive film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10174301A JP2000012776A (en) | 1998-06-22 | 1998-06-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10174301A JP2000012776A (en) | 1998-06-22 | 1998-06-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000012776A true JP2000012776A (en) | 2000-01-14 |
Family
ID=15976279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10174301A Pending JP2000012776A (en) | 1998-06-22 | 1998-06-22 | Manufacture of semiconductor device |
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Country | Link |
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JP (1) | JP2000012776A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100737188B1 (en) | 2004-11-30 | 2007-07-10 | 후지쓰 메디아 데바이스 가부시키가이샤 | Electronic device and method of manufacturing the same |
JP2019515316A (en) * | 2017-03-29 | 2019-06-06 | 安徽▲雲▼塔▲電▼子科技有限公司 | Integrated circuit and method of testing integrated circuit |
-
1998
- 1998-06-22 JP JP10174301A patent/JP2000012776A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100737188B1 (en) | 2004-11-30 | 2007-07-10 | 후지쓰 메디아 데바이스 가부시키가이샤 | Electronic device and method of manufacturing the same |
JP2019515316A (en) * | 2017-03-29 | 2019-06-06 | 安徽▲雲▼塔▲電▼子科技有限公司 | Integrated circuit and method of testing integrated circuit |
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