JPH08330250A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a highly reliable semiconductor device by preventing the electrification of change by plasma dry etching. CONSTITUTION: A gate insulator film 4 and LOCOS oxide films 2 to serve as an element insulator film and a dummy insulator film are made on a substrate 1, and then a contact hole 13 is made in the dummy insulator film of the LOCOS oxide film 2. Then, a polysilicon film is accumulated, and a resist pattern is made by lithography technique, and by plasma etching, a dummy wiring 14a to which one end of each gate wiring 5 is connected, and a dummy region 14b connected to this dummy wiring 14a are made together with a gate wiring 5. At this time, the dummy wiring 14b is connected with the substrate 1 through a contact hole 13. Then, the dummy wiring 14a is etched off, and the the substrate 1 and each gate wiring 5 are isolated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method capable of reducing charge-up damage due to plasma dry etching.

[0002]

2. Description of the Related Art It has been conventionally pointed out that in a semiconductor device manufacturing process by plasma dry etching, a semiconductor element is damaged by electrical stress due to accumulation of electric charges, resulting in breakdown voltage failure and reliability deterioration.
That is, when an electric field is applied to the insulator film when the conductor film is over-etched in the process of etching the conductor film formed on the insulator film by the plasma dry etching method, this insulator film is This is because it is damaged by electrostatic stress.

The step of etching the conductor film on the insulator film by the plasma dry etching method is found in many steps in the manufacturing process of semiconductor devices. Here, the manufacturing steps of the gate wiring and the capacitor electrode will be described.

FIG. 4 is a sectional view and a top view showing a process of etching a gate wiring in a conventional semiconductor device.
In this figure, 1 is a substrate made of a semiconductor such as silicon, 2 is a LOCOS oxide film which is an element isolation insulator film made of an insulator film such as silicon dioxide formed on the substrate 1 to isolate elements, 3 is this LOCO of substrate 1
The island-shaped activation regions 4 used as actual elements other than the region where the S oxide film 2 is formed are formed in the activation region 3 and are formed of, for example, an insulating film such as silicon dioxide having a film thickness of about 5 to 15 nm. Is formed on the gate insulator film 4, and the gate wiring 6 is formed on the gate wiring 5 by a conductive film such as polysilicon having a film thickness of about 50 to 200 nm. This is a resist pattern used when etching the gate wiring 5.

A method of forming the gate wiring 5 will be briefly described below. First, after the LOCOS oxide film 2 is formed on the substrate 1 by the LOCOS oxidation method (local oxidation method),
A gate insulator film 4 is formed on the activation region 3 by a thermal oxidation method. Next, after depositing a polysilicon film on the entire surface of the substrate 1 by the CVD method, the resist pattern 6 is formed by the lithography technique so that the portion to be the gate wiring 5 remains.
By using the resist pattern 6 as a mask, the polysilicon film is etched by a reactive ion etching method (hereinafter referred to as RIE) which is plasma dry etching, and then the resist pattern 6 is removed. 5 is formed.

Next, the process of forming the gate wiring 5 by RIE will be described in detail. In the RIE apparatus, charged particles in plasma move randomly, but an electric field is not generated in the vertical direction of the substrate 1 in the vicinity of the substrate 1. Therefore, when positive ions enter this electric field region, Under the influence of this, the substrate 1 is accelerated in the vertical direction to have a large velocity component, and anisotropic etching is performed.

On the other hand, the electrons are reduced in the vertical direction of the substrate 1 by the electric field, the velocity component is reduced, the electrons cannot enter the narrow pattern bottom, most of the electrons are trapped in the resist, and only the positive ions are trapped. Will enter the bottom of the pattern.

Further, due to variations in the thickness of the polysilicon film, the polysilicon film remains between the gate wirings 5,
In order to prevent short circuit between the gate wirings 5, RIE
Is over-etched, but during this over-etching, that is, when the gate insulating film 4 is exposed between the gate wirings 5, each gate wiring 5 is isolated, so that positive charges are applied to the gate wiring 5. As a result, the potential difference is generated between the gate wiring 5 and the substrate 1, and a high electric field is applied to the gate insulator film 4. Therefore, electrostatic stress is applied to the gate insulator film 4,
The gate insulator film 4 is damaged, the breakdown voltage is deteriorated, and the semiconductor element is defective.

Next, a method of manufacturing a stack type capacitor electrode of a conventional semiconductor device will be described. FIG. 5 is a sectional view showing an etching process of a stack type capacitor electrode of a conventional semiconductor device. In this figure, 7 is an interlayer insulator film made of an insulator film such as silicon dioxide having a film thickness of about 600 to 1000 nm formed on the substrate 1, and 8 is an opening formed in the interlayer insulator film 7. It is a contact hole.

Reference numeral 9 denotes a capacitor which is formed on the interlayer insulating film 7 and is electrically connected to the substrate 1 through the contact hole 8 and is made of a conductive film such as a polysilicon film having a thickness of about 500 to 700 nm. The lower electrode 10 is a capacitor insulator film formed on the lower electrode 9 and made of an insulator film such as silicon nitride having a film thickness of about 6 to 10 nm, 11
Is an upper electrode of a capacitor formed of a conductor film such as a polysilicon film having a film thickness of about 150 to 300 nm on the lower electrode 9 with a capacitor insulator film 10 interposed therebetween. As a result, one upper electrode 11 is formed. 12 is formed on the upper electrode 11, and the upper electrode 1
1 is a resist pattern used at the time of etching 1.

The method of forming the capacitor electrode will be described below. First, a silicon dioxide film is deposited on the substrate 1 by the CVD method to form an interlayer insulating film 7, and then a region where the contact hole 8 is to be an opening is formed on the interlayer insulating film 7 by a lithography technique. After forming the pattern, the contact hole 8 is formed by RIE. Next, after depositing a polysilicon film by the CVD method, a resist mask in the shape of the lower electrode 9 that covers the contact hole 8 is formed by using the lithography technique, and then R
A lower electrode 8 made of a polysilicon film is formed on the contact hole 8 by IE.

Next, a silicon nitride film is deposited by the CVD method to form a capacitor insulator film 10, a polysilicon film is deposited by the CVD method, and a resist pattern 12 in the shape of the upper electrode 11 is formed by the lithography technique. Then, the polysilicon film is formed on the upper electrode 11 by RIE.
After etching into the shape of
Is removed, and the capacitor electrode is completed.

Also in the above-described etching process of the upper electrode 11 by RIE, as in the case of the gate wiring 5, positive charges are accumulated in the upper electrode 11 during overetching, and a potential difference from the lower electrode 8 is generated. As a result, a high electric field is applied to the capacitor insulator film 10, electrostatic stress is applied to the capacitor insulator film 10, the capacitor insulator film 10 is damaged, and as a semiconductor element such as breakdown voltage deterioration. Defects will occur.

[0014]

As described above, in the process of etching the conductor film formed on the semiconductor or conductor via the thin insulator film by plasma dry etching, the insulator film is removed. Therefore, a potential difference is inevitably generated between the semiconductor or conductor and the conductor film formed through this, electrical stress is applied to the insulator film, and the reliability of the insulator film such as deterioration of withstand voltage is reduced. Will be reduced. Therefore, there is a problem that the reliability of the semiconductor device is lowered.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the charging of electric charges by plasma dry etching and improving the reliability of the semiconductor device. And

[0016]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, an insulating film having a thin film region which is liable to be destroyed by an electric field due to a charge during the process is used. In a method of manufacturing a semiconductor device, in which a conductor film formed on a semiconductor or conductor is etched into a predetermined pattern by plasma dry etching, the insulator film is formed, and the conductor film is etched by plasma dry etching. After simultaneously forming the predetermined pattern and a dummy pattern electrically connected to the predetermined pattern and electrically connected to the semiconductor or conductor through a contact hole, the predetermined pattern and the dummy pattern are electrically connected. The feature is that they are separated physically.

In a method of manufacturing a semiconductor device according to a second aspect of the present invention, a step of forming an element isolation insulator film, a gate insulator film and a dummy insulator film on a semiconductor substrate, and a semiconductor on the dummy insulator film. After forming a contact hole reaching the substrate, a step of depositing a conductor film on the gate insulator film, the element isolation insulator film and the dummy insulator film, and etching this conductor film by plasma dry etching. A step of simultaneously forming a gate wiring and a dummy pattern electrically connected to the semiconductor substrate through a contact hole of the dummy insulator film and electrically connected to the gate wiring; And a step of electrically disconnecting the dummy pattern from the dummy pattern.

In a method of manufacturing a semiconductor device according to a third aspect of the present invention, a step of forming a lower electrode of a capacitor and a dummy lower electrode made of a conductor film on a semiconductor or a conductor, and a lower electrode of the capacitor. And a step of forming a capacitor insulator film so as to cover the dummy lower electrode, a step of forming a contact hole in the capacitor insulator film on the dummy lower electrode, and a step of forming a conductive film on the capacitor insulator film having the contact hole. After the body film is deposited, the conductor film is etched by plasma dry etching to electrically connect the upper electrode of the capacitor and the upper electrode of the capacitor, and to connect the semiconductor or conductive layer through the contact hole. A step of forming a dummy upper electrode electrically connected to the body, and the dummy upper electrode and the capacitor. Between the upper electrode of Sita, it is characterized in that a step of electrically disconnecting.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, a mask having an opening having a size sufficient to allow positive ions and electrons to pass through is formed at the time of plasma dry etching, and then plasma dry etching is performed. By etching the conductor film for the opening, the predetermined pattern and the dummy pattern, the gate wiring and the dummy pattern, or the upper electrode of the capacitor and the dummy upper electrode are electrically separated.

In a method of manufacturing a semiconductor device according to a fifth aspect of the present invention, a step of forming a gate insulating film on a semiconductor substrate, a step of forming an opening in this gate insulating film, and this opening After depositing a conductor film on the gate insulator film having the above, the conductor film is etched by plasma dry etching on the gate insulator film and on the semiconductor substrate at the opening of the gate insulator film to form a gate wiring. And a step of forming.

[0021]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, after forming a contact hole in an insulator film on a semiconductor or a conductor, a conductor film is formed on the insulator film, and a plasma is formed. The conductor film is etched by dry etching to simultaneously form a predetermined pattern and a dummy pattern electrically connected to the predetermined pattern and electrically connected to the semiconductor or conductor through a contact hole. Therefore, the electric charge charged in a predetermined pattern by the plasma dry etching escapes to the semiconductor or the conductor under the insulator film through the dummy pattern, so that the predetermined charge formed through the semiconductor film and the conductor and the insulator film. Since there is no potential difference between the patterns and no electric field is applied to the insulator film, damage to the insulator film can be prevented.

Further, by separating the predetermined pattern and the dummy pattern thereafter, the function of the predetermined pattern itself is not impaired.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, in the step of etching the conductor film formed on the semiconductor substrate via the gate insulator film by plasma dry etching, the gate wiring and the electrical conductor are formed. A dummy pattern that is electrically connected to the semiconductor substrate and is electrically connected to the semiconductor substrate through a contact hole formed in the dummy insulator film together with the gate wiring. Therefore, the charge charged on the gate wiring during the plasma dry etching escapes to the semiconductor substrate through the dummy pattern, so that there is no potential difference between the semiconductor substrate and the gate wiring formed through the gate insulator film, and the gate wiring is formed. Since no electric field is applied to the insulator film, damage to the gate insulator film can be prevented.

Further, by separating the gate wiring and the dummy pattern thereafter, the function of the gate wiring itself is not impaired.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, in the step of etching the conductor film by plasma dry etching to form the upper electrode of the capacitor, the upper electrode of the capacitor and the upper electrode of the capacitor are formed. By forming a dummy upper electrode that is electrically connected to the electrode and electrically connected to the dummy lower electrode via the insulator film of the capacitor, the charge charged on the upper electrode of the capacitor by plasma dry etching is Since it escapes to the semiconductor substrate through the dummy upper electrode and the dummy lower electrode, there is no potential difference between the capacitor upper electrode and the capacitor lower electrode, and no electric field is applied to the gate insulator film. It is possible to prevent damage to the body membrane.

Further, thereafter, by electrically disconnecting the upper electrode of the capacitor and the dummy upper electrode, the function of the capacitor electrode is not impaired.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, a mask having an opening having a size that allows electrons to pass through together with positive ions is used, and the conductive film in the opening is formed by plasma etching. By etching, a predetermined pattern and a dummy pattern, or a gate wiring and a dummy pattern, without charging electric charge,
Alternatively, the upper electrode of the capacitor and the dummy upper electrode are separated.

In the method of manufacturing a semiconductor device according to claim 5 of the present invention, an opening is formed in the gate insulator film on the semiconductor substrate, the conductor film is etched by plasma dry etching, and the gate insulator film is formed. In the step of forming the gate wiring in the step of forming the gate wiring on the exposed surface of the semiconductor substrate in the opening of the gate insulator film,
Even if the gate wiring on the gate insulating film is positively charged by plasma dry etching, the semiconductor substrate in the opening of the gate insulating film is also positively charged. Since there is no potential difference between them and no electric field is applied to the gate insulator film, damage to the gate insulator film can be prevented.

[0029]

【Example】

Example 1. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view and a top view showing an etching process of a gate wiring in a semiconductor device according to an embodiment of the present invention. In this figure, the same reference numerals as those in the conventional example indicate the same parts. Further, 13 is a contact hole formed in the dummy insulator film formed in a part of the LOCOS oxide film 2 in this embodiment, and reaching the substrate 1.
A dummy pattern 14 is formed during the process of forming the gate wiring 5 and electrically connects the plurality of gate wirings 5 and the substrate 1 to each other through the contact holes 13 and connects one end of the plurality of gate wirings 5. The dummy wiring 14a and the dummy region 14b for electrically connecting the dummy wiring 14a and the substrate 1 through the contact hole 13 are formed. Reference numeral 15 is an etching region serving as an opening of a resist pattern for separating the dummy pattern 14 and the gate wiring 5.

Next, a method of forming the gate wiring 5 will be described. Since the steps up to the formation of the gate insulator film 4 are exactly the same as the steps described in the conventional technique, they are omitted here and the subsequent steps will be described in detail. A resist pattern having a contact hole 13 as an opening is formed by a lithography technique on the LOCOS oxide film 2 serving as the gate insulator film 4, the element isolation insulator film, and the dummy insulator film, and then the dummy insulator is formed by RIE. The contact hole 13 is formed in the dummy insulator film by etching the film and removing the resist pattern.

Next, the gate insulator film 4 and the LOCOS.
A polysilicon film to be the gate wiring 5 is formed on the oxide film 2 by CV.
After depositing by the D method, a resist pattern 6 is formed by a lithographic technique so that the gate wiring 5 and the dummy pattern 14 remain, and the polysilicon film is formed by RIE which is plasma dry etching using the resist pattern 6 as a mask. After etching, the resist pattern 6 is removed and the gate wiring 5 and the dummy pattern 14 are formed.

The dummy pattern 14 is used for the gate wiring 5
One end is connected by the dummy wiring 14a, and the dummy region 14b connected to the dummy wiring 14a electrically connects the gate wiring 5 and the substrate 1 through the contact hole 13. Therefore, RI
Since the gate wiring 5 is electrically connected to the substrate 1 through the dummy pattern 14 by etching the dummy pattern 14 together with the gate wiring 5 during the etching by E, electrons are incident to the narrow pattern bottom. However, most of the electrons are trapped in the resist pattern and only positive ions enter the bottom of the pattern. Even if positive charges are charged on the gate wiring 5, the positive charges on the gate wiring 5 are dummy. Since it escapes to the substrate 1 through the pattern 14, no potential difference is generated between the gate wiring 5 and the substrate 1, and no electric field is applied to the gate insulator film 4. Therefore, the gate insulator film 4 is not damaged.

Next, as shown in FIG.
After forming a resist pattern in which the etching region 15 in (b) is an opening, the polysilicon film in the etching region 15 is etched by RIE to separate the gate wiring 5 and the dummy pattern 14 and connect the gate wirings 5 to each other. Then, the connection with the substrate 1 is cut off, and the gate wiring 5 is completed.

Here, RIE is used in the step of cutting the dummy pattern 14 and the gate wiring 5 described above. However, since the etching region 15 is very large, for example, 10 μm × 200 μm, electrons are sufficiently introduced together with positive ions, so that overetching is performed. There is no charge-up inside.

As described above, the gate wiring 5 and the dummy pattern 14 are simultaneously etched by RIE, so that the positive charges of the gate wiring 5 are transferred to the dummy pattern 1.
By allowing it to escape to the substrate 1 via 4, the static electricity stress is not applied to the gate insulator film 4, the occurrence of breakdown voltage deterioration and the occurrence of damage are prevented, and the occurrence of defects as semiconductor elements is avoided. You can

Furthermore, the gate wiring 5 and the dummy pattern 1
The function as the gate wiring 5 is not impaired by separating the wiring 4 from the wiring 4.

In the above embodiment, one end of the gate wiring 5 is connected by the dummy wiring 14a and the dummy area 14b connected to the dummy wiring 14a is connected to the substrate 1. Board 1 for each
It goes without saying that the dummy pattern 14 connected to the above may be formed.

Example 2. 2A to 2D are sectional views of a manufacturing process showing a method of manufacturing a capacitor electrode in a semiconductor device according to a second embodiment of the present invention. In the figure, 16 is a dummy lower electrode which is a dummy pattern formed at the same time as the lower electrode 9 of the capacitor in a region other than the region where the element is formed. The dummy lower electrode 16 is electrically connected to the lower electrode 9 via the substrate 1. Connected to each other. Reference numeral 17 denotes a contact hole formed in the capacitor insulator film 10 on the dummy lower electrode 16 and 1
8 is a resist pattern for forming this contact hole 17, 19 is formed at the same time as the upper electrode 11, is electrically connected to the upper electrode 11, and is electrically connected to the dummy lower electrode 16 through the contact hole 17. The dummy upper electrode 20 is a resist pattern for etching the upper electrode 11 with the dummy upper electrode 19 connected, and 21 is the upper electrode 11 and the dummy upper electrode 19
It is a resist pattern having an opening for separating and.

Next, a method of forming the capacitor electrode will be described. After depositing a silicon dioxide film on the substrate 1 by the CVD method to form an interlayer insulating film 7, a contact hole 8 is formed on the interlayer insulating film 7 by using a lithography technique.
After forming a resist pattern in which the region to be an opening becomes an opening, a contact hole is formed by RIE. At this time, the contact hole 8 for forming the dummy lower electrode 16 is also formed adjacent to the lower electrode 9.

Next, after depositing a polysilicon film by the CVD method, a mask covering a desired region is formed by using a lithography technique, and then the polysilicon film is formed into a shape of the lower electrode 9 together with the dummy lower electrode 16 by RIE. Etching process.

Next, as shown in FIG. 2A, CV
After depositing a silicon nitride film by the D method and forming the capacitor insulator film 10, a resist mask having an opening above the dummy lower electrode 16 is formed by using a lithography technique, and the capacitor insulator film 10 is etched by RIE. Then, a contact hole 17 is formed in the capacitor insulator film 10. Then, a polysilicon film is deposited by the CVD method, and a resist pattern is formed by the lithography technique such that the dummy upper electrode 19 remains on the contact hole 16 of the capacitor insulator film 10 together with the upper electrode 11.

Next, as shown in FIG. 2B, RI
The polysilicon film is etched by E so that the upper electrode 11 and the dummy upper electrode 19 are connected to each other. In this etching process, the dummy upper electrode 19 connected to the upper electrode 11 is etched together with the upper electrode 11, so that the charge of the upper electrode 11 is changed.
9 and the contact hole 17 and escapes to the substrate 1 through the dummy lower electrode 16, so that there is no potential difference between the upper electrode 11 and the lower electrode 9 of the capacitor.
No electric field is applied to the capacitor insulator film 10 and the capacitor insulator film 10 is not damaged.

Finally, as shown in FIG. 2C, a resist pattern 21 having an opening of 2 μm or more in width is formed between the upper electrode 11 and the dummy upper electrode 19 by a lithography technique, and etching is performed by RIE. The upper electrode 11 and the dummy upper electrode 19 are separated by
Only the upper electrode 11 is used as a device.

As described above, by setting the separation width between the upper electrode 11 and the dummy upper electrode 19 to be about 2 μm or more, the positive ions and the electrons can reach the bottom of the pattern sufficiently to charge the upper electrode 11 by RIE. Can be prevented from being charged.

In the above-mentioned embodiment, the example of preventing the damage of the gate insulator film 4 and the capacitor insulator film 10 is described, but the present invention is not limited to this, and there is a possibility that the electric field due to the charged electric charges may cause destruction during the process. The same method can be used in the step of forming a pattern with a narrow pitch by plasma etching the conductor film formed via the insulator film.

Example 3. 3A to 3D are sectional views of a manufacturing process for explaining a method of forming a gate wiring in a semiconductor device which is Embodiment 3 of the present invention. In this figure, 22 is an opening formed in the gate insulating film 4, for example, a size of about 1 chip and having a size of about 1.5 × 1.5 cm, and 23 is a gate insulating material for forming the opening 22. It is a resist pattern formed on the film 4. Reference numeral 24 is a polysilicon film which is a conductor film for forming the gate wiring 5.

The difference between the method of forming the gate wiring of the third embodiment and the conventional technique is that after forming the gate insulator film 4, a resist pattern 23 which will be an opening for about one chip is formed by the lithography technique. , RIE is used to etch the gate insulating film 4 to form an opening 22 having a size of one chip in the gate insulating film 4. After the opening 22 of the gate insulating film 4 is formed, In the process, the gate wiring 5 is formed by the same method as that described in the related art. At this time, the opening 2 of the gate insulator film 4
2, that is, the gate wiring 5 is formed also on the exposed substrate 1.

Thus, the opening 2 of the gate insulator film 4 is formed.
In the step of etching the polysilicon film 24 to the gate wiring 5 by RIE by forming the gate wiring 5 on the exposed substrate 1 of 2, the gate wiring 5 is formed on the gate wiring 5 during overetching as described in the related art. Even when the positive charge is charged, the opening 2 of the gate insulator film 4 is similarly formed.
The substrate 1 is also charged with positive charges through 2, and the positive charges charged on the gate wiring 5 formed on the substrate 1 in the opening 22 of the gate insulator film 4 also flow to the substrate 1. Therefore, there is no potential difference between the gate wiring 5 and the substrate 1, no electric field is applied to the gate insulator film 4, and the gate insulator film 4
Will not be damaged.

Therefore, in the gate wiring forming method of this embodiment, it is possible to prevent the breakdown voltage of the gate insulator film 4 and the occurrence of damage, so that it is possible to prevent the occurrence of defects in the semiconductor device and improve the yield. The reliability of the semiconductor device can be improved.

[0050]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the conductor film formed on the semiconductor or conductor via the insulator film is etched by plasma dry etching to form a predetermined pattern. In the process of forming
By forming a dummy pattern that is electrically connected to the predetermined pattern together with the predetermined pattern and is electrically connected to the semiconductor or the conductor, a potential difference does not occur between the predetermined pattern and the semiconductor or the conductor,
Since the electric field is not applied to the insulating film between the predetermined pattern and the semiconductor or the conductor, the insulating film can be prevented from being damaged. Further, by electrically separating the predetermined pattern and the dummy pattern thereafter, the function of the predetermined pattern is not impaired, and the reliability of the semiconductor device is improved.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the step of etching the conductor film formed on the semiconductor substrate via the gate insulator film by plasma dry etching to form a gate wiring is performed. By forming a dummy pattern that is electrically connected to the gate wiring together with the gate wiring and electrically connected to the semiconductor substrate by etching, a potential difference does not occur between the gate wiring and the semiconductor substrate, Since no electric field is applied to the gate insulator film, damage to the gate insulator film can be prevented. Furthermore, by electrically separating the gate wiring from the dummy pattern thereafter, there is an effect that the reliability of the semiconductor device is improved without impairing the function of the gate wiring.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, the lower electrode of the capacitor formed on the semiconductor or the conductor and the dummy lower electrode are formed via the capacitor insulator film. In the process of etching the conductor film by plasma dry etching to form the upper electrode of the capacitor, together with the upper electrode of the capacitor,
By forming a dummy upper electrode, which is electrically connected to the upper electrode of the capacitor and electrically connected to the semiconductor or the conductor through the dummy lower electrode, by etching, the upper electrode and the lower electrode of the capacitor are formed. Since there is no potential difference between the capacitor insulator film and the capacitor insulator film and no electric field is applied to the capacitor insulator film, damage to the capacitor insulator film can be prevented. Further, thereafter, by electrically disconnecting the upper electrode of the capacitor and the dummy upper electrode, there is an effect that the reliability of the semiconductor device is improved without impairing the function of the capacitor electrode.

In the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, the conductive film for the opening is etched by plasma etching using a mask having an opening through which electrons as well as positive ions can sufficiently pass. There is an effect that the predetermined pattern and the dummy pattern, the gate wiring and the dummy pattern, or the capacitor upper electrode and the dummy pattern can be separated without charging the electric charge.

In the method for manufacturing a semiconductor device according to the fifth aspect of the present invention, an opening is formed in the gate insulator film, and the conductor film on the gate insulator film is etched by plasma dry etching to form a gate. By simultaneously forming the gate wiring on the exposed surface of the semiconductor substrate in the opening of the gate insulating film in the step of forming the wiring, charges are charged on the semiconductor substrate together with the gate wiring, so that the gate wiring and the semiconductor substrate Since there is no potential difference between them and no charge is applied to the gate insulator film, damage to the gate insulator film can be prevented, and the reliability of the semiconductor device is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view and a top view for explaining a method for manufacturing a semiconductor device that is Embodiment 1 of the present invention.

FIG. 2 is a manufacturing step sectional view showing a method of manufacturing a semiconductor device, which is Embodiment 2 of the present invention.

FIG. 3 is a manufacturing step sectional view showing a method of manufacturing a semiconductor device, which is Embodiment 3 of the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view for explaining another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 substrate, 2 LOCOS oxide film, 4 gate insulator film, 5 gate wiring, 9 lower electrode, 10 capacitor insulator film, 11 upper electrode, 13 contact hole,
14a dummy wiring, 14b dummy region, 15 etching region, 16 dummy lower electrode, 17 contact hole, 19 dummy upper electrode, 22 opening.

Claims (5)

[Claims] 1. A conductor film formed on a semiconductor or a conductor through an insulator film having a thin film region that is likely to be destroyed by an electric field due to a charged electric charge during a process is subjected to plasma dry etching in a predetermined pattern. In the method of manufacturing a semiconductor device, wherein the insulator film is formed, the conductor film is etched by plasma dry etching, and the predetermined pattern and the predetermined pattern are electrically connected to each other, and the semiconductor or conductor is formed. And a dummy pattern that is electrically connected through a contact hole are formed at the same time, and then the predetermined pattern and the dummy pattern are electrically separated from each other. 2. A step of forming an element isolation insulator film, a gate insulator film and a dummy insulator film on a semiconductor substrate, and a step of forming a contact hole reaching the semiconductor substrate in the dummy insulator film, and then forming the gate. A step of depositing a conductor film on the insulator film, the element isolation insulator film and the dummy insulator film, and etching this conductor film by plasma dry etching to remove the gate wiring and the contact hole of the dummy insulator film. A step of simultaneously forming a dummy pattern electrically connected to the semiconductor substrate via the gate wiring and the gate wiring, and a step of electrically disconnecting the gate wiring and the dummy pattern. A method of manufacturing a semiconductor device, comprising: 3. A step of forming a lower electrode of a capacitor and a dummy lower electrode made of a conductor film on a semiconductor or a conductor, and a capacitor insulator film covering the lower electrode of the capacitor and the dummy lower electrode. Forming step, forming a contact hole in the capacitor insulator film on the dummy lower electrode, depositing a conductor film on the capacitor insulator film having the contact hole, and then performing plasma dry etching The body film is etched to form an upper electrode of the capacitor and a dummy upper electrode electrically connected to the upper electrode of the capacitor and electrically connected to the semiconductor or the conductor through the contact hole. And a step of electrically disconnecting the dummy upper electrode and the upper electrode of the capacitor. A method for manufacturing a semiconductor device, comprising: 4. A predetermined mask is formed by forming a mask having an opening having a size that allows electrons together with positive ions to pass through sufficiently during plasma dry etching, and etching the conductor film corresponding to the opening by plasma dry etching. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern and the dummy pattern, the gate wiring and the dummy pattern, or the upper electrode of the capacitor and the dummy upper electrode are electrically separated. 5. A step of forming a gate insulator film on a semiconductor substrate, a step of forming an opening in the gate insulator film, and a conductor film deposited on the gate insulator film having the opening. And a step of forming a gate wiring on the gate insulator film and on the semiconductor substrate in the opening of the gate insulator film by plasma dry etching. Device manufacturing method.