JP2504522Y2 - Address pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application field" The present invention relates to an address pattern generator for generating address data in a device for testing a memory to which address data is serially input.

“Prior Art” Address data of a normal memory is parallel input, but there is a memory in which address data is serial input in order to reduce the number of external terminals. This kind of memory is second
As shown in the figure, the address data is serially input to the address register 11 in 1-bit units. The address register 11 accumulates the input serial data by the address bit width and converts it into parallel data by the address decoder.
Tell 12. The address decoder 12 decodes the parallel address data to access the memory cell 13.

Although the address generating circuit of the conventional memory test apparatus has a structure for generating a parallel address, the address data is multiplied by 2 by using the multiplying function of the address generating circuit. Address data was serially output by using left shift by 1 bit.

On the other hand, most semiconductor memories differ from the external address (logical address) and the actual chip address (physical address) due to compatibility with the same product type of other companies and miniaturization of chip size. In order to test the effect of interference between memory cells, it is necessary to test the memory with the actual chip address (physical address). Therefore, in the memory testing device, as shown in FIG. 3, the parallel address data (logical address data) generated from the address generation circuit 14 is input to the address scramble memory 15 to be converted into parallel physical address data, and the physical address data Are supplied to the memory under test 16.

When testing a memory in which the address is input serially and the physical address is different from the logical address, if address data is generated serially from the address generation circuit and the serial address data is passed through the address scramble memory, meaningless data Will be. For this reason, in the past, a memory whose address is serially input can be tested with high accuracy only when the physical address matches the logical address. , I can only test by estimating the address and writing the data and reading the data of the cell at that address,
It was not possible to perform a highly accurate test for testing the interference between adjacent cells due to the influence on the adjacent cells due to the writing of data.

The present invention provides an address pattern generator capable of testing a memory in which an address is serially input and a physical address is different from a logical address.

According to the present invention, parallel logical address data from the address generator is converted into physical address data by the address scramble memory, and the parallel physical address data is serially addressed by the serial out circuit. Converted to data, and by the address generator,
Whether to output from the upper bit or the lower bit is controlled.

"Embodiment" FIG. 1 shows an embodiment of the present invention. Address generation circuit
The parallel logical address data generated from 14 is converted into parallel physical address data by the address scramble memory 15. The parallel physical address data is converted into serial address data by the serial out circuit 17 and supplied to the memory under test 16.

The serial-out circuit 17 is composed of, for example, a multiplexer and a control circuit including a counter for controlling the multiplexer, and is controlled by a control signal from the address generation circuit 14 to perform a serial-out operation. This serial out is the upper bit,
Output from any of the lower bits is possible, and the operation is also performed by the control signal from the address generation circuit 14. The serial out circuit 17 is for converting parallel data into serial data, and may be a parallel-serial conversion circuit using a shift register. When the address of the memory under test 16 is 2-bit or 4-bit serial input, the serial-out circuit 17 is set to 2-bit or 4-bit serial-out according to this.

[Advantage of Invention] As described above, according to this invention, the parallel logical address data is first converted into physical address data and then converted into serial data. It is possible to generate a test address pattern for a semiconductor memory having a different physical address, and it is possible to perform a highly accurate test including an inter-cell interference test.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an address pattern generator according to the present invention, FIG. 2 is a block diagram showing a memory of serial input addresses, and FIG. 3 is a block diagram showing an address pattern generator of conventional parallel address data. Is.

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Claims (1)

(57) [Scope of utility model registration request] 1. An address generator, an address scramble memory for converting logical address data generated by the address generator into physical address data, and physical address data from the address scramble memory for converting serial address data, and An address pattern generator, comprising: a serial-out circuit in which which of upper bits or lower bits is output by the address generator is controlled.