JPS6164000A - Test device for semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the test accuracy for semiconductor memories by securing the coincidence between a proper address matrix number of a test device and the physical position of a memory cell. CONSTITUTION:A primary control part 1 transmits a start signal to a memory exerciser 2, and the exerciser 2 start execution of a microprogram. Both the address information and the write information are written on a semiconductor memory 7 to be tested through a driver 5. The read data information given from the memory 7 is read to the exerciser 2 through a comparator 6, and a clock is applied to the memory 7 from a timing signal generator 3 via a driver 4. In this case, an address conversion circuit 8 consists of a ROM and obtains the coincidence between a proper address matrix number of a test device which is decided by the output signal of an address counter within the exerciser 2 and an address matrix number of the memory 7 and the physical position of a memory cell within a semiconductor chip respectively.

Description

[Detailed description of the invention] The present invention relates to a testing device for semiconductor manufacturing.

When testing a semiconductor memory, assuming that the number of memory cells of this semiconductor memory is 1, the semiconductor memory has 21'11! It is possible to memorize L combination patterns, and it takes a huge amount of time to test all of these combination patterns, making it extremely difficult to test semiconductor memories. The reason for this is that it also depends on the history of the addresses that read and write the above pattern. The main reason for this is the memory bits and memory pins of the semiconductor memory mentioned above.
This can be said to be because the selection circuits and the like are fabricated at a very high density on the same substrate, so their physical positional relationship cannot be ignored. However, at present, it is not economically viable to perform all of the combinations of data patterns and address pattern history, so a memory exerciser using a microprogram is used to generate and compare data and address patterns. It is common to perform tests using a selection of rigorous test conditions. It is composed of circuits, etc., and the data pattern is the addition and subtraction of binary data.
2'll: etc., store the results in multiple registers, create an ef for the information stored in these registers, i.e., the combination of pattern and address selection, and for the address pattern, increment the address counter. , decrement, store the results in multiple registers, replace the information in these registers with the address counter information from time to time, and output the address counter information.
Multiple output information i! of the above address counter. , each address has a certain weight and is assigned an address matrix number unique to the test device. Therefore, the address output information of the test device is determined completely independently of the address matrix number of the semiconductor memory under test (hereinafter referred to as MUT).

As mentioned above, the address operation history is important in semiconductor memory testing, and it also includes the physical positional relationship. If there is a one-to-one correspondence between the row and column numbers, or if the rows and rows are in a one-to-one correspondence, or if they are located just as far apart as a certain number of address rows and rows, the physical connection between the address information output terminal of the test device and the address information input terminal of the MUT is The error in physical positional relationship matching can be solved by wiring connections, but if any part of the selection circuit output of the memory cell of the MUT is moved to an arbitrary position, the error between the terminals Delivery! This problem cannot be solved by connection, and it cannot be applied to the test method intended by the tester. Therefore, it has the disadvantage that it is not possible to conduct a highly accurate test using the above-mentioned test device. The present invention has been made to solve the above problems, and its purpose is to provide a test device that partially achieves the same test accuracy for semiconductor memories.

A test device according to the present invention for achieving the above object includes a memory exerciser that generates a common phase address signal to a semiconductor memory under test, and a memory exerciser coupled to the memory exerciser that receives the unique address signal and predicts the address signal. a read-only memory that converts and outputs the converted address signal according to previously stored conversion data; and means for supplying the converted address signal to the semiconductor memory under test; The data is such that the physical location of the address number specified by the address decoder in the semiconductor memory under test using the converted address signal matches the address number indicated by the unique address signal generated by the memory exerciser. ◎ Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an example of a general configuration diagram of a conventional semiconductor memory testing device, and FIG. 2 is a configuration diagram of an embodiment according to the present invention. is a memory enhancer p1
3 is a timing signal generator, 4 is a clock driver, 5 is a data and address driver, 6 is a comparator, and 7 is an MUT. The main control unit 1 manages the control of the entire system and storage and execution of the test program, and the test program is decoded and executed one instruction at a time in response to an external start signal. The address information and data information are sent to the memory exerciser 2 as a microprogram and stored therein, and the timing signal information is sent to the timing signal generator s3 and stored therein. In this state, the main controller 1 sends a start signal to the memory exerciser 2, and the memory exerciser 2 starts executing the microprogram, and the execution speed is determined by the synchronization signal with the timing signal generator 3. By executing the microprogram, the seat address information and write data information are applied to the MtJT7 through the driver 5, and the read data information from the MtJT7 is applied to the memory exerciser 2 through the comparator 6.
The clock signal is applied from the timing signal generator 3 to the MUT 7 through the clock driver 48. In this case, a unique address matrix number is assigned to the address signal output of the memory extensor 2, and is led to the entrance of MυT7 through the driver 5, and the connection with the address matrix number of MUT7 is made by physical wiring. .

The cases in which the conventional test apparatus shown in FIG. 1 can match the physical arrangement of the memory cells of the MUT 7 and the cases in which it cannot be explained will be explained with reference to FIGS. 3, 4, and 5.

FIG. 3 shows an example of a portion of the MUT 7 in which the physical arrangement of memory cells is regular, FIG. 5 shows details of an example of the memo cell portion, and FIG.
An example of a portion of the MUT 7 in which the physical arrangement of cells is irregular is shown.

In FIGS. 3 and 4, 21 to 28 are inverter circuits, and 29 to 36 are two-person AND circuits that serve as address signals for the MUT 7. Form a decoding circuit for the signal input of ~person, and use X, %X for the A6 + AI signal input.
, and outputs Y0 to Y for At and A, indicating that one of memory cells 00 to n□ is selected.◎In Figure 3, the output of the decoding circuit is regular. Since they are lined up in a row, memory cells that physically correspond can be created by simply wiring the address matrix number Ao -'-A of the MUT 7 that corresponds to the address matrix number unique to the test equipment in the driver 5 shown in Figure 1. can be selected. According to FIG. 5, 40 to 47 indicate MO8) transistors, and output signals XM (M=θ) of the address decoding circuit are shown.
3), Ym (m = 0 to 3) indicates that data information is read and written to the memory cells (formed by 40 to 43). Naakatsu Memory Se, Not〆n6
″−’I+”4 ~nl t 'a ′nlD
'11 to n0 indicate that they are formed on the same data input line, which means that they are susceptible to noise on the address decoding circuit output line, for example, the above address decoding circuit output line. When valleys iLC+ to C1 are formed, noise tends to flow into nearby lines, especially into adjacent 2-in lines, during signal transients. For example, in FIG. 3, the memory cell n0 is most affected when the memory cell n1, n4, or n is selected by the capacitor JtCt or C6.

The important thing in this test is to read or write data information in memory cell n6, and then read or write data information 8 to memory cell n, or n4, or n, which is closest to the physical location. ◎However, in the example of FIG. 4, among the address decoding circuit output signals, X, X! This shows that nt4 or n has been replaced compared to the example in FIG. 3, and is affected by the capacitances 04 to C1 as in FIG. Selecting n is based on physical location.

Alternatively, it means that a highly accurate test cannot be performed because n6 is closer.

The present invention eliminates such drawbacks, and the physical wiring connections between the address matrix numbers A0 to A of MU'I'7 and the unique address matrix numbers of the test equipment do not change at all, and the memory 1-. This makes it possible to select cell n or n6 after selecting cell n0.

That is, as a specific example of the non-invention, there is an atsis change between the memory exerciser 2 and the driver 5 and 0 for the conventional test V & position shown in FIG. FIG. 2 shows an embodiment in which the address conversion circuit 8 is provided with a read-only memory. Conversion is performed between the column number and the address column number of the MUT 7 in order to match the physical location with the memory cell in the semiconductor chip.

If this invention is applied to the MUT7V which has a regular array of memory cells as shown in Fig. 85g3, it is necessary to input a unique address from the memory exerciser.

For A, each logic @Q II is at address 0.
, @Q II is at address 1, @1m is at address 1, @0” is at address 2,
10” on the street address.

111'' or 3:lIi is ``l'', ``'1'',
Unique address input A! e For Am, address 0 has logic fi@0' and 'O', respectively, and address 1 has @l.
+l, @Q 11 ka, @O" 11 at address 2
．． lj, @1'' and @11'' are stored in the read-only memory 8 at the 3n position, respectively. In this case the unique address signals AO*Al and A, , A, K
On the other hand, the data output A0' of the memory 8.

This means that the same information as the address input can be obtained for A1' and A2't A,/. Therefore, the configuration in this case is completely equivalent to that shown in FIG.

When the present invention is applied to the MUT 7 in which memory cells are arranged irregularly as shown in FIG. 4, the read-only memory 8
has a unique address A0. For A and Ic, the logic ``101.''''O' is at address 0, and @0 is at address 1.
"S Pi is 1 bit at the 2nd address, IIQ" is 11 at the 3rd address.
”, 'Bi is also a unique address person,.

For A, the same information as in the above case is stored. Therefore, the unique address AOt
When the address information of Al is "o" @Qll (address 0), @O", @0; is output to the data output of the memory 8, and no is selected in the memory cell of FIG. 4. The above address information @O′.

If it is @l' (address 1), @ill and @1011 are output to the read-only memory 8, and n is selected in the memory cell.□The above address information is @1'' IIQ
``(address 2), @O'' and @l'' are output to the output of the read-only memory 8, and the memory cell outputs n,
is selected.

Therefore, when the present invention is implemented, the unique address matrix number of the test device matches the physical location of the memory cell, making it possible to test semiconductor memory with high precision.
The effect is huge.

Furthermore, it is easy to see that if the MUT 7 has a large capacity, the capacity of the memory 8 should be increased. Further, although the memory cell of the present invention shown in FIG. 5 is of a static type, it is clear that a dynamic type memory cell can also have similar effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional test device, FIG. 2 is a configuration diagram of an embodiment of a test device according to the present invention, and FIG. 3 is a configuration diagram of a test device according to the present invention.
A circuit diagram showing an example of a memory under test in which cells are arranged regularly, FIG. 4 is a circuit diagram showing an example of a memory under test in which memory cells are arranged irregularly, and FIG. 5 is a circuit diagram showing an example of a memory under test in which memory cells are arranged irregularly. This is a circuit diagram of...Main control section, 2...Memory exerciser, 3...
- Timing signal generation section, 4... Clock driver, 5... Data and address driver, 6...
Comparator, 7...Semiconductor memory under test, Address conversion circuit (ROM), 21-28...Inverter circuit, 29-36...2 manual AND circuit, [I0-
fill...Memory cell, =40-47...M
OS) Ranjistor. Agent: Susumu Uchihara, Patent Attorney: Figure 2, 3rd, 4th page

Claims (1)

[Claims] a memory exerciser that generates a unique address signal to be supplied to the semiconductor memory under test; and a memory exerciser coupled to the memory exerciser that receives the unique address signal and converts it according to conversion data stored in advance. and means for supplying the converted address signal to the semiconductor memory under test,
The conversion data stored in the read-only memory is such that the physical location of the address number specified by the address decoder in the semiconductor memory under test by the converted address signal is determined by the address number generated by the memory exerciser. 1. A test device for a semiconductor memory, characterized in that the device is set to match an address number indicated by an address signal.