JP2503217B2 - Method of forming electrode wiring - Google Patents
Method of forming electrode wiringInfo
- Publication number
- JP2503217B2 JP2503217B2 JP30457186A JP30457186A JP2503217B2 JP 2503217 B2 JP2503217 B2 JP 2503217B2 JP 30457186 A JP30457186 A JP 30457186A JP 30457186 A JP30457186 A JP 30457186A JP 2503217 B2 JP2503217 B2 JP 2503217B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- barrier metal
- electrode wiring
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明の電極配線の方法は、異方性エッチング技術を
利用すること等により、Cu配線の周囲に該Cuのバリア膜
を形成することを特徴とする。これによりその後の熱処
理等に曝された場合にもCu膜のCuがSiやSiO2膜中に拡散
したり、あるいは酸化されることがないので、Cu配線の
低抵抗値を維持することが可能となる。DETAILED DESCRIPTION OF THE INVENTION [Outline] The electrode wiring method of the present invention is characterized in that a Cu barrier film is formed around a Cu wiring by utilizing an anisotropic etching technique or the like. As a result, even when exposed to subsequent heat treatment, etc., Cu in the Cu film will not diffuse into the Si or SiO 2 film or be oxidized, so that the low resistance value of the Cu wiring can be maintained. Becomes
本発明は電極配線の形成方法に関するものであり、更
に詳しく言えばCuを基体とする電極配線の形成方法に関
するものである。The present invention relates to a method for forming electrode wiring, and more particularly to a method for forming electrode wiring based on Cu.
従来より配線材料としてAl又はAl合金が多用されてい
るが、近年の半導体装置の集積化により、配線の一層の
微細化が要求されている。Conventionally, Al or Al alloy has been frequently used as a wiring material, but further integration of semiconductor devices in recent years has required further miniaturization of wiring.
しかし、Al又はAl合金からなる配線においては、エレ
クトロマイグレーションやストレスによるボイド発生等
により断線が生じ、半導体装置の信頼性の低下を招く。However, in a wiring made of Al or an Al alloy, disconnection occurs due to generation of voids due to electromigration or stress, which leads to deterioration in reliability of the semiconductor device.
そこでエレクトロマイグレーションやストレスに強
く、またAlよりも低抵抗のCuを半導体装置の配線材料と
して用いることが注目されている。Therefore, attention has been paid to using Cu, which is resistant to electromigration and stress and has a lower resistance than Al, as a wiring material for semiconductor devices.
しかし、CuはSiやSiO2膜に対する拡散係数が大きく、
このためプロセス中の熱処理により該SiやSiO2膜中に容
易に拡散してｐ−ｎ接合のリーク電流の原因となる等の
問題がある。また熱処理によりCuが酸化して配線抵抗が
急激に上昇するという問題がある。However, Cu has a large diffusion coefficient for Si and SiO 2 films,
Therefore, there is a problem that the heat treatment during the process easily diffuses into the Si or SiO 2 film and causes a leak current of the pn junction. Further, there is a problem that Cu is oxidized by heat treatment and wiring resistance is rapidly increased.
本発明はかかる従来の問題点に鑑みて創作されたもの
であり、Cuの保護膜によってCu配線を囲むことにより、
低抵抗で、かつ高信頼性の電極配線の形成方法の提供を
目的とする。The present invention was created in view of such conventional problems, by surrounding the Cu wiring by a protective film of Cu,
An object of the present invention is to provide a method of forming electrode wiring having low resistance and high reliability.
本発明の電極配線の方法は、Cuの第１のバリア金属
膜,Cu膜,Cuの第２のバリア金属膜を順次、半導体基板上
に重ねて形成する工程と、前記各膜をパターニングして
配線パターンを形成する工程と、全面にCuの第３のバリ
ア金属膜を形成する工程と、異方性エッチングにより前
記配線の側面に前記第３のバリア金属膜を残す工程とを
有することを特徴とする。The electrode wiring method of the present invention comprises a step of sequentially stacking a Cu first barrier metal film, a Cu film, and a Cu second barrier metal film on a semiconductor substrate, and patterning each film. The method has a step of forming a wiring pattern, a step of forming a Cu third barrier metal film on the entire surface, and a step of leaving the third barrier metal film on the side surface of the wiring by anisotropic etching. And
異方性エッチングにより、配線の側面以外の平坦な場
所に形成された第３のバリア金属膜は除去される。しか
し、配線の表面には第３のバリア金属膜の下に第２のバ
リア金属膜が形成されているので、第３のバリア金属膜
がエッチング除去された時点でエッチングを停止すれ
ば、配線の側面に第３のバリア金属膜を、また配線の表
面に第２のバリア金属膜を残すことができる。By anisotropic etching, the third barrier metal film formed on a flat portion other than the side surface of the wiring is removed. However, since the second barrier metal film is formed under the third barrier metal film on the surface of the wiring, if the etching is stopped when the third barrier metal film is removed by etching, the wiring The third barrier metal film can be left on the side surface and the second barrier metal film can be left on the surface of the wiring.
このように、本発明によればCuの周囲をバリア金属膜
によって完全に囲むことができる。As described above, according to the present invention, the periphery of Cu can be completely surrounded by the barrier metal film.
次に図を参照しながら本発明の実施例について説明す
る。第１図は本発明の実施例に係る電極配線の形成方法
を説明する図である。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a method of forming electrode wiring according to an embodiment of the present invention.
（１） まずSi基板１上のSiO2膜２の上に、膜厚500Å
のTi膜3,膜厚1000ÅのTiN膜4,膜厚7000ÅのCu膜5,膜厚2
000ÅのTiN膜６を形成する。次いでTiN6,Cu膜5,TiN膜4,
Ti膜３のパターニングを順次行ない電極配線を形成す
る。このときCuのエッチングはTiN膜６をマスクにした
イオンミリング法により行ない、またTiNとTiのエッチ
ングはSF6＋O2,10％の反応性イオンエッチング法（RIE
法）により行なう（同図（ａ））。(1) First, a film thickness of 500 Å on the SiO 2 film 2 on the Si substrate 1.
Ti film 3, 1000 Å TiN film 4, 7000 Å Cu film 5, film thickness 2
A 000Å TiN film 6 is formed. Next, TiN6, Cu film 5, TiN film 4,
The Ti film 3 is sequentially patterned to form electrode wiring. At this time, Cu is etched by an ion milling method using the TiN film 6 as a mask, and TiN and Ti are etched by SF 6 + O 2 , 10% reactive ion etching method (RIE
Method) ((a) in the same figure).
（２） 次いで膜厚3000ÅのTiN膜７をバイアススパッ
タリング法により形成する。これによりSiO2膜２および
TiN膜６の表面だけでなく、Cu膜５の側面にもTiN膜７が
一様に形成される（同図（ｂ））。(2) Next, a TiN film 7 having a film thickness of 3000 Å is formed by the bias sputtering method. As a result, the SiO 2 film 2 and
The TiN film 7 is uniformly formed not only on the surface of the TiN film 6 but also on the side surface of the Cu film 5 (FIG. 7B).
（３） 次にRIE法によりTiN膜の異方性ドライエッチン
グを行なう。これによりSiO2膜２の上およびTiN膜６の
上のTiN膜７がエッチングされるが、Cu膜５の側面に形
成されたTiN7は残る。またSiO2膜２の上のTiN膜７がエ
ッチング除去された時点でエッチングを停止すれば、Cu
膜５の上のTiN膜６を残すことができる（同図
（ｃ））。(3) Next, anisotropic dry etching of the TiN film is performed by the RIE method. As a result, the TiN film 7 on the SiO 2 film 2 and the TiN film 6 is etched, but the TiN 7 formed on the side surface of the Cu film 5 remains. If etching is stopped when the TiN film 7 on the SiO 2 film 2 is removed by etching, Cu
The TiN film 6 can be left on the film 5 (FIG. 7C).
このように本発明の実施例によれば、低抵抗で、かつ
信頼性の高い電極配線を形成することができる。As described above, according to the embodiment of the present invention, it is possible to form electrode wiring having low resistance and high reliability.
なお実施例ではバリア金属膜としてTiN膜を用いたが
それ以外にＷ膜,Mo膜,Ta膜又はCr膜を用いてもよい。Although the TiN film is used as the barrier metal film in the embodiment, a W film, a Mo film, a Ta film or a Cr film may be used instead.
また実施例ではSi基板１上に形成された場合のオーミ
ックコンタクト用金属膜としてTi膜３を用いたが、その
他のオーミックコンタクト用金属膜を用いてもよい。Although the Ti film 3 is used as the ohmic contact metal film when formed on the Si substrate 1 in the embodiment, other ohmic contact metal films may be used.
以上説明したように、本発明によれば配線基体として
のCu膜の周囲をバリア金属膜によって完全に被覆してい
るので、その後のプロセスにおいて熱処理を施された場
合にも、該Cu膜からCuがSiO2膜やSi基板中に拡散するこ
とを防止することができるとともに、該Cu膜が酸化する
のを防止することができる。このため低抵抗で、信頼性
の高い電極配線を得ることが可能である。As described above, according to the present invention, since the periphery of the Cu film as the wiring substrate is completely covered with the barrier metal film, even if a heat treatment is applied in the subsequent process, the Cu film is not removed from the Cu film. Can be prevented from diffusing into the SiO 2 film or the Si substrate, and the Cu film can be prevented from being oxidized. Therefore, it is possible to obtain a highly reliable electrode wiring having a low resistance.
従って本発明によって形成される電極配線を、微細化
する半導体集積回路に用いれば、特に有効である。Therefore, it is particularly effective if the electrode wiring formed by the present invention is used in a semiconductor integrated circuit which is miniaturized.
第１図は本発明の実施例に係る電極配線の形成方法を説
明する図である。 （符号の説明） １……Si基板、２……SiO2膜、３……Ti膜（オーミック
コンタクト用金属膜）、4,6,7……TiN膜（バリア金属
膜）、５……Cu膜。FIG. 1 is a diagram illustrating a method of forming electrode wiring according to an embodiment of the present invention. (Description of symbols) 1 ... Si substrate, 2 ... SiO 2 film, 3 ... Ti film (metal film for ohmic contact), 4,6,7 ... TiN film (barrier metal film), 5 ... Cu film.
Claims (2)
バリア金属膜を順次、半導体基板上に重ねて形成する工
程と、 前記各膜をパターニングして配線パターンを形成する工
程と、 全面にCuの第３のバリア金属膜を形成する工程と、 異方性エッチングにより前記配線の側面に前記第３のバ
リア金属膜を残す工程とを有することを特徴とする電極
配線の形成方法。1. A step of sequentially forming a first barrier metal film of Cu, a Cu film, and a second barrier metal film of Cu on a semiconductor substrate, and patterning the respective films to form a wiring pattern. And a step of forming a third barrier metal film of Cu on the entire surface, and a step of leaving the third barrier metal film on the side surface of the wiring by anisotropic etching. Forming method.
又はCr膜のいずれかであることを特徴とする特許請求の
範囲第１項に記載の電極配線の形成方法。2. The method for forming electrode wiring according to claim 1, wherein the barrier metal film is any one of a TiN film, a W film, a Mo film, a Ta film and a Cr film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30457186A JP2503217B2 (en) | 1986-12-19 | 1986-12-19 | Method of forming electrode wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30457186A JP2503217B2 (en) | 1986-12-19 | 1986-12-19 | Method of forming electrode wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63156341A JPS63156341A (en) | 1988-06-29 |
| JP2503217B2 true JP2503217B2 (en) | 1996-06-05 |
Family
ID=17934594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30457186A Expired - Lifetime JP2503217B2 (en) | 1986-12-19 | 1986-12-19 | Method of forming electrode wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2503217B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2659714B2 (en) * | 1987-07-21 | 1997-09-30 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| US5506449A (en) * | 1993-03-24 | 1996-04-09 | Kawasaki Steel Corporation | Interconnection structure for semiconductor integrated circuit and manufacture of the same |
| JP2701730B2 (en) * | 1994-02-24 | 1998-01-21 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US6391771B1 (en) * | 1998-07-23 | 2002-05-21 | Applied Materials, Inc. | Integrated circuit interconnect lines having sidewall layers |
| CA2328907A1 (en) * | 1999-02-18 | 2000-08-24 | Naoki Tsukiji | Electrode for semiconductor device and its manufacturing method |
| JP3473485B2 (en) | 1999-04-08 | 2003-12-02 | 日本電気株式会社 | Thin film resistor and manufacturing method thereof |
| US6339258B1 (en) | 1999-07-02 | 2002-01-15 | International Business Machines Corporation | Low resistivity tantalum |
| US6699777B2 (en) * | 2001-10-04 | 2004-03-02 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
| KR20030053673A (en) * | 2001-12-22 | 2003-07-02 | 동부전자 주식회사 | Semiconductor Devices and Method For Fabricating The Same |
| US7508075B2 (en) | 2003-08-01 | 2009-03-24 | Micron Technology, Inc. | Self-aligned poly-metal structures |
| JP4423379B2 (en) | 2008-03-25 | 2010-03-03 | 合同会社先端配線材料研究所 | Copper wiring, semiconductor device, and method of forming copper wiring |
| JP4441658B1 (en) | 2008-12-19 | 2010-03-31 | 国立大学法人東北大学 | Copper wiring forming method, copper wiring, and semiconductor device |
| JP2017503432A (en) * | 2014-01-15 | 2017-01-26 | エプコス アクチエンゲゼルシャフトＥｐｃｏｓ Ａｇ | An electronic acoustic filter and a method for manufacturing an electronic acoustic filter. |
-
1986
- 1986-12-19 JP JP30457186A patent/JP2503217B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63156341A (en) | 1988-06-29 |
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