JP2502528B2 - Teletext receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a teletext receiver.

2. Description of the Related Art In recent years, character broadcasting in which character signals are multiplexed in a vertical retrace period of television waves has begun and has become widespread in earnest. Teletext is not transmitted in a multiplexed manner over the entire transmission time of television radio waves. Some stations do not provide teletext service.

Therefore, the teletext receiver is currently performing teletext, and the display element or the like allows the user to recognize whether or not the teletext can be received.

An example of a teletext display showing that teletext is being performed by a conventional teletext receiver will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of the character multiplex receiver showing the above conventional example.

In FIG. 4, reference numeral 1 denotes a sync separation circuit, which extracts a horizontal sync signal and a vertical sync signal from the video signal A. In the horizontal sync separation, phase synchronization control is performed on the self-oscillation by the horizontal sync signal of the broadcast wave extracted from the video, and when there is no signal, a pulse is output by the self-oscillation. 2 is waveform equalization, character signal separation circuit, 4 is display clock generation circuit, 5 is display control, bus control circuit, 6 is color memory, 7 is pattern memory, 8 is color matrix circuit, 9 is additional sound interface circuit, Reference numeral 10 is an additional sound decoder circuit, 11 is a character signal decoding microprocessor (CPU), 12 is a program ROM for character signal decoding processing, 13 is work RAM, 14 is buffer RAM, and 15 is pattern information based on code information. Character generator for converting to, 16 is a keyboard for instructing program selection, etc., 17 is a keyboard interface circuit for converting data input from the keyboard to 11 microprocessors for connection, and 18 is a TV signal A switching circuit for switching between the character signal and the character signal, and the reference numeral 19 turns on the display element by the microprocessor of 11 judging whether or not the character broadcasting is being performed. Than become I / O port registers for, 20 is its driver and the display element.

A circuit for displaying that the teletext broadcast of the teletext broadcasting receiver configured as described above can be received will be described. From the video signal input A, in the waveform equalization and character signal separation circuit of 2, the superimposition section of the character signal in the vertical blanking section is gated by the output of the 1 synchronization separation circuit to extract the character signal and make it a binary signal. . This signal is sent to the error correction circuit 3 to correct an error generated on the transmission line. From the received data after this error correction, data processing is performed by a decoding processing unit including 11 CPUs, 12 program ROMs, 13 work RAMs, 14 buffer RAMs, 15 character generators, and 6 color memories. A character broadcast screen is decoded and displayed by writing figures and character information to be displayed in the pattern memory 7 through the display control circuit 5. The transmitted data relating to the additional sound is transferred to the sound decoder circuit 10 through the additional sound interface 9 to decode the additional sound,
Generate a sound. Conventionally, it is determined that the character multiplex broadcasting service is provided and indicates that the character multiplex broadcasting can be received. Conventionally, when decoding the error-corrected received data, the data packet service is used. The identification (SI) is determined by 11 microprocessors to determine whether it is a pattern transmission method, an encoding method, or an operation signal, and the display element is turned on in the register of the I / O port in FIG. 4 and 19. Or, it was done by writing data to turn off the light.

Problems to be Solved by the Invention However, the above-described configuration has the following problems. At present, due to the program structure of the character multiplex broadcasting, an operation signal may be inserted to fill a gap between the programs as the operation signal is sent to a packet to be multiplexed.

Therefore, the received data superimposed on the vertical blanking period
When 11 microprocessors are loaded, the service identification (SI) is determined for each vertical period, and the I / O port is controlled, there is a period during which light is turned off even though the teletext service is being performed for several vertical periods. is there. In other words, the display element may blink. FIG. 5 illustrates this state. D represents a vertical synchronizing signal, and E represents a data packet superimposed in the vertical blanking period. n is a packet having SI indicating the coded transmission method, n + 1 to n + 3 are operational signal packets, and n + 4 is a coded transmission method packet. The microprocessor shown in FIG. 4 controls the 19 display I / O ports by determining the service identification (SI) in each vertical period by the interrupt process, and therefore n + 1 data packets after n data packets arrive. The display element lights up to the packet,
The data packets of n + 1 to n + 3 are turned off, and are turned on again at n + 4, and the display blinks. When the antenna cable is disconnected or the video signal input is disconnected in the adapter type character multiplex receiver, the character multiplex screen cannot be decoded depending on the timing, but the display element remains lit. It happened to happen. The state is shown in FIG. If the video signal input is disconnected at the time point X after the data packet of n + 1 has been fetched and SI has been determined and the lighting process has been performed, the microprocessor cannot perform the interrupt determination process. Therefore, it remains lit. F is
The display element control signal from the I / O port is shown.

In view of the above-mentioned problems, the present invention has a character multiplex reception display means that the display element does not blink when the character multiplex broadcasting service is provided, and that is surely turned off when the character multiplex broadcasting cannot be received. A character multiplex broadcasting receiver is provided.

Means for Solving the Problems In order to solve the above problems, the present invention provides a circuit for counting a horizontal synchronizing signal reproduced by applying phase synchronization to self-oscillation and its counting circuit for register output of an I / O port. It is provided with a character multiplex reception display control circuit composed of a circuit to be initialized by, an I / O port, a display element and its driver circuit.

With the above-described configuration, the present invention allows the microprocessor to perform I / O
The display element is turned on by initializing the counting circuit of the horizontal synchronizing signal through the O port, and when the text broadcast is not received for the time specified by the counting circuit, it is turned off by the output from the counting circuit. Therefore, it is possible to perform the character multiplex broadcast reception display that is surely turned off when the character broadcast cannot be received without the display element blinking in a short time due to an operation signal or the like.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a teletext receiver of the present invention. 7 to 20 are the same as the conventional example. Reference numeral 30 is a character multiplex broadcast reception display control circuit, B is a reproduced horizontal synchronizing signal, and C is a display clock. FIG. 2 is an example of a specific circuit that details the character multiplex broadcast reception display. 19 is an I / O port, which is composed of 191 flip-flops. K is a data line and L is a write pulse to the register. Reference numeral 30 is a character multiplex broadcast reception display control circuit, 304 is a counting circuit for counting the reproduced horizontal synchronizing signal B, 301 and 302 are flip-flops for delaying a write pulse, and 303 is a NOR circuit, which is delayed from the output of the register. The gate of the write pulse is taken and connected to the reset signal G and to the reset terminal of the counting circuit 304. The NOR circuit of 306 and 307 and the flip-flop of 308 form a set-reset circuit.
The reset signal G is input to one end of the OR circuit, which serves as a set signal for the set reset circuit. The output of the AND circuit of 305 is connected to one end of 307 and serves as a reset signal of the set reset circuit. The output H of the counting circuit and the horizontal synchronizing signal B are input to the AND circuit 305. The output J of 308 is connected to the base of the transistor of 202 through the resistor of 201. The emitter of the transistor 202 is grounded, and the collector is connected to the display element 204 via the resistor 203.

The operation of the character multiplex reception / display circuit configured as described above will be described with reference to FIG. D and E are the same signals as described in the conventional example. The 11 microprocessor determines the service identification (SI) of the fetched data and writes "H" to the register 191 of the 19 I / O port at the time of the n data packet, and the inverted output of 191 is NOR of 303. The circuit is gated with a signal obtained by delaying the write pulse L to form a positive pulse such as G in FIG. 3 to initialize the counting circuit 304. Along with that, the set / reset circuit is set and the control signal J of the display element is set.
Is set to "H" to turn on the display element 204. n + 1 to n +
Since it is an operation signal in the packet of 3, the register 191 '
After writing L ', the reset pulse G is not output. 30
Although the counting circuit of 4 counts up, the counting circuit overflows and its output H is set to "H" level for about 1 second, so J remains "H".
Since the +4 packet is a packet of the encoding transmission system, the counting circuit is reset. When a character signal is not input after n + 1, the signal G for resetting the counting circuit remains "L", so the output H of the counting circuit is output after 1 second.
Becomes "H" level, a pulse is output to the reset output I of the set / reset circuit, the control signal J of the display element becomes "L" level, and the display element is turned off. Therefore, unlike the conventional example, the display element does not blink in a short time due to the operation signal, and when the teletext cannot be received, it can be surely turned off.

EFFECTS OF THE INVENTION As described above, the present invention provides a counting circuit that counts a horizontal synchronizing signal reproduced by performing phase synchronization with a horizontal synchronizing signal obtained by synchronously separating an input video signal from a signal oscillated by self-excited oscillation, and a counting circuit. The microprocessor for decoding the teletext data by the counting circuit determines the presence or absence of teletext,
The I / O port that outputs the result is equipped with a character multiplex broadcast reception and display circuit that resets when a character broadcast is being performed. It is possible to obtain a character multiplex broadcasting receiver having a character multiplex receiving and displaying means for surely extinguishing when the character broadcasting cannot be decoded without the display element of the character multiplex receiving display blinking for a short time even if is inserted. It is useful.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a character multiplex receiver according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a character multiplex reception display control circuit section, and FIG. FIG. 4 is a block diagram of a character multiplex receiver having a conventional character multiplex reception display circuit, and FIG. 5 is a waveform diagram for explaining its operation. 19 ...... I / O port, 20 ... Display element drive circuit, 30 ... Character multiplex broadcast reception display control circuit, 191 ... Register, 304 ...
… Counter circuit, 308 …… D flip-flop.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toyoaki Unemura 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Inventor Yuji Kondo 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Inventor Eimi Hidemi 1006, Kadoma, Kadoma-shi, Matsuda Denki Sangyo Co., Ltd. (56) Reference JP-A-59-224989 (JP, A) Actual development S51-28034 (JP, U) Actual development S58-28476 (JP, U) Actually open 59-50166 (JP, U)

Claims (1)

(57) [Claims] 1. A horizontal sync signal having the same phase as the horizontal sync signal of the input video signal by phase-locking a signal oscillating by self-excited oscillation with a horizontal sync signal obtained by synchronously separating the input video signal. A counting circuit for counting the reproduced horizontal sync signal from the sync separation circuit for generating
A circuit for the microprocessor for decoding teletext data to determine the presence or absence of teletext based on the service identification code of the packet data and initialize the counting circuit with the output from the output port for outputting the result, A set / reset circuit that is output when the count value reaches a predetermined count value, that is reset by the output of the count circuit and that is set by the output from the output port, and that output drives a display element via a display drive circuit. Then, the character multiplex broadcasting receiver is provided with a character multiplex broadcasting receiving and displaying circuit section for receiving and displaying the character multiplex broadcasting.