JPH029750B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sampling pulse correction method that is effective for use in systems that receive and reproduce television signals containing character information. In a communication system, when sampling incoming data using sampling pulses,
It is required that the data bits and sampling pulses match in phase with high accuracy. However, the transmitted data is not always kept at a constant phase and amplitude due to disturbances or internal factors. Therefore, a means for accurately extracting data by automatically adjusting the phase of the sampling pulse is desired. This invention was made in view of the above circumstances, and it not only automatically adjusts the phase of the clock pulse for sampling, but also automatically adjusts the slice level of the data being sent. It is an object of the present invention to provide a sampling pulse correction method that can obtain a sampling pulse that can accurately extract the data, and in particular has a fast correction operation. Embodiments of the present invention will be described below with reference to the drawings. First, a teletext receiving system for a color television receiver to which the present invention is applied will be explained. The format of the television signal used in teletext broadcasting is set as shown in FIG. 1a and 1b show the vertical blanking period portions of the first field and the next field of a composite video signal, where V is a vertical synchronizing signal. Teletext packets 1 and 2 are set at the rear of this vertical retrace period, for example, at the 20th H (H; one horizontal period) after the end of the previous field. The format of this teletext packet is set as shown in FIG. 1c. H is a horizontal synchronization signal, and 5 is a color burst. The teletext packet 2 is formed by a header section 6 and an information section 7. This teletext packet 2 is shown in more detail in FIG. 1d. That is, the header section 6 has a clock line in (clock line in).
It is composed of a runin signal (CRI), a framing code (FC), an identification eye code (IDC), program codes PC1, PC2, etc. The clock run-in signal (CRI) is a signal for adjusting the phase of the clock pulses necessary for sampling the data in this teletext packet. Fleming code (FC) is a code that indicates the beginning of data. The identification code (IDC) is a code for identifying the display format, transmission signal format, etc., and the program codes PC1 and PC2 are codes indicating the type of text information program. The teletext packets described above are processed, for example, by a system as shown in FIG. 1
Reference numeral 1 denotes an input terminal to which an intermediate frequency of a teletext television signal is input. The signal applied to this input terminal is subjected to image detection by the image detection circuit 12. The video-detected composite video signal is input to a waveform shaping circuit 13 that extracts teletext packets and performs waveform shaping. Further, the composite video signal is input to a synchronization separation circuit 21 that separates a vertical synchronization signal V and a horizontal synchronization signal H. The vertical synchronization signal V and horizontal synchronization signal H separated from the synchronization separation circuit 21 are sent to the vertical position counter 2.
2 is input. This vertical position counter 22 is
It is reset by the vertical synchronizing signal V, and the horizontal synchronizing signal H
By counting the numbers, it is possible to obtain a sampling pulse corresponding to the position where the teletext packet is superimposed. The sampling pulse obtained by the vertical position counter 22 is input to the waveform shaping circuit 13. As a result, the waveform shaping circuit 13 extracts the teletext packet described in FIG. 1 and shapes its waveform. The output obtained from this waveform shaping circuit 13 is input to a sampling circuit 14 and also to a clock run-in signal detection circuit 16. The clock run-in signal detection circuit 16 extracts the clock run-in signal (CRI) shown in FIG. This clock pulse generating circuit 17 has a function of generating continuous clock pulses in synchronization with the clock run-in signal. The continuous clock pulses output from this clock pulse generation circuit 17 are as follows:
The signal is input to the sampling circuit 14 and used as a data sampling pulse. In the sampling circuit 14, various types of data as shown in FIG. The output of the sampling circuit 14 is also input to a framing code detection circuit 18.
This framing code detection circuit 18 performs detection by comparing a predetermined framing code and an input code, detects a point where the codes completely match, and detects the beginning of data in the buffer memory. This is what you set. Framing code detection circuit 18 is driven by clock pulses from horizontal position counter 23, for example. The horizontal position counter 23 is reset by the horizontal synchronization signal H from the synchronization separation circuit 21, and counts the clock pulses from the clock pulse generation circuit 17. This horizontal position counter 2
The count information of 3 is also added to the address circuit 24. Further, this address circuit 24 includes:
The previous vertical synchronization signal is also input. This address circuit 24 can generate address data regarding the horizontal and vertical directions of the image obtained by the currently input composite video signal. As described above, the buffer memory 15 stores the contents of a teletext packet when it arrives. The data stored in this buffer memory 15 is processed by a microcomputer. Central processing unit (hereinafter referred to as CPU) 30
decodes the data contents of the buffer memory 15. For example, what is the data format?
This is because of what the program is. For example, a case will be explained in which it is desired to display a weather forecast as a teletext broadcast. If it is desired to display the weather forecast, a command signal for processing the weather forecast data can be input by operating the keyboard 40. The weather forecast program is specified by the program code shown in FIG. For example, program code
Assuming that the data of PC1 is sending the weather forecast, this program code PC1 is
The calculation is processed by . As a result, if the data in the program code PC1 matches the data designated from the keyboard 40, it is determined that the data in the buffer memory 15 is data for a weather forecast. A command signal for reproducing a weather forecast specified from the keyboard 40 is stored in a random access memory 32 (hereinafter referred to as RAM). The weather forecast pattern data read from the buffer memory 15 is finally stored in the pattern memory 33 as character data and symbol data. The color data is stored in color memory 34. The data read from the buffer memory 15 is stored in the pattern memory 33 as character data or signal data, but if the transmission method is a code transmission method, the data read from the buffer memory 15 is decoded and read. Predetermined character data, that is, characters, signals, and graphic data may be read out from the only memory 31 (hereinafter referred to as ROM) and stored in the pattern memory 33 or the like. Therefore, a character ROM 39 is also provided. As mentioned above, character and signal graphic data are stored in the pattern memory 33 based on the data derived from the buffer memory 15. However, by extracting the teletext packet only once in the vertical period, the character display can be performed. Not enough data is available. Therefore, each time there is a vertical synchronization period and each time a desired program is detected, the data is sequentially stored in the pattern memory 33. When data is stored in the pattern memory 33 and color memory 34, address designation data specifying the storage address may be input together with the data to determine in which address the data is stored. When data stored in the pattern memory 33 and color memory 34 is read out and displayed, the data in the pattern memory 33 is sent to the pattern decoder 35, and the data in the color memory 34 is sent to the color decoder 36 to be converted to DC. is converted to
The output interface 37 synthesizes the signals. Then, it is combined with the composite video signal in a combining circuit 38. The timing of reading data from the pattern memory 33 and color memory 34 is based on a command signal from the CPU 30. The CPU 30 constantly decodes address data (corresponding to the current screen beam irradiation position) input from the address circuit 24. When this address data matches the desired display designation data set in the RAM 32, read signals corresponding to these address data are applied to the pattern memory 33 and color memory 34.
The display designation data is included in the program stored in the RAM 32, and various display formats can be set according to changes in the display designation data and program switching. In a system operating as described above, it is important to sample teletext packet data without error in evaluating its performance. Next, the clock pulse generating means according to the present invention will be explained with reference to FIG. In FIG. 3, 52 is an input terminal to which a signal from the video detection stage is applied, and this is connected to one input terminal of the slice circuit 10G.
The output of this slice circuit 10G is the output terminal 53
The signal is input to the sampling circuit 14 via. Therefore, this slice circuit 10G corresponds to the waveform shaping circuit 13 described above. On the other hand, the original clock pulse is applied to input terminal 50. This original clock pulse is generated by an oscillation circuit that oscillates and outputs a clock pulse based on the clock run-in signal detected by the clock run-in signal detection circuit 16. The frequency of this original clock pulse is, for example, twice the frequency of the data sampling pulse. This original clock pulse is phase-corrected by the delay means 10A, and is led out to the output terminal 51 through the frequency divider 54 and used as a data sampling pulse. The system shown in FIG. 3 has a function of correcting the data sampling pulse to an appropriate phase and a function of setting the data slice level to an appropriate level. First, this system includes the delay means 10A,
It includes a delay amount control means 10B, a slice level control means 10C, a digital-to-analog converter 10F, and the like. Furthermore, digital phase detection means 10D for the clock run-in signal of the corrected clock pulse and input data;
It has a converter 10E etc. that converts the information output from D into phase correction information and slice level correction information. Next, to explain the operation of each part, first, for the digital phase detection means 10D, the slice circuit 1
The data from 0G and the correction clock pulse _CP1 taken out from the delay means 10A are input. The correction clock pulse CP ₁ is used as a driving pulse for the latch circuit 55 and is also used as a driving pulse for the inverter 5.
8 to the clock pulse input terminals of shift registers 56 and 57. The data output from the slice circuit 10G is sent to the latch circuit 5.
It is applied to the input terminal of shift register 57 as well as to the input terminal of shift register 57. Latch circuit 5
The output of 5 is also applied to the input terminal of shift register 56. Output terminal A ₁ of shift register 56,
A ₃ , A ₅ , A ₇ and output terminal of shift register 57
A ₀ , A ₂ , A ₄ , A ₆ , A ₈ are the corresponding latch circuits 5
9, and each output terminal of this latch circuit 59 is connected to the input terminal of each corresponding converter 10E. As described above, the output terminals A ₁ , A ₃ , A ₅ , and A ₇ of the shift register 56 sequentially output data obtained by sampling input data using sampling pulses in the latch circuit 55.
Output terminals of shift register 57 A ₀ , A ₂ , A ₄ ,
Data obtained by sampling the input data using an inverted sampling pulse passed through the inverter 58 is sequentially output from A ₆ and A ₈ . Therefore, the data obtained from the output terminals A ₀ -A ₈ of the shift registers 56 - 57 becomes data substantially equivalent to input data sampled at a frequency four times that of the sampling pulse. This is the clock pulse
This is because CP ₁ is twice the sampling pulse, and this pulse is used as a clock for latch circuit 55 and, via inverter 58, as a clock for shift registers 56 and 57. The output data obtained from the output terminals _A0 to _A8 includes not only the duty ratio of the input data but also phase information with respect to the sampling pulse, as shown in FIGS. 4e to 4m. The output of the AND circuit 61 is used as the latch pulse of the latch circuit 59. The correction clock pulse is applied to one input terminal of the AND circuit 61, and the output of the frequency divider 54 is applied to the other input terminal via the inverter 62.
That is, a correction sampling pulse is added. Therefore, a logical output corresponding to one bit of the output data of the slice circuit 10G is obtained from the AND circuit 61. According to the above digital phase detection means 10D,
Output information related to the phase and slice level of the data and sampling data output from the slice circuit 10G is transmitted to the shift registers 56 and 5.
7 output terminals _A0 to _A8 . If the information obtained from the digital phase detection means 10D is shown in a table, information _A0 to _A8 as shown in Tables 1 to 5, which will be described later, can be obtained from the shift registers 56 and 57. Table 1 shows examples of information representing the phase relationship between sampling pulses and data, and the correspondence between information D ₀ to D ₇ output from the converter 10E based on this information. A read-only memory ROM is used as the converter 10E, and what kind of output information is to be output in response to input information is stored in advance. In the converter 10E, as shown in FIG. 4, the sampling pulse P ₀ is 0 for the data.
If there is a delay of ~90°, the output information D ₀ to D ₇ is set to be “00001000”. Fourth
Figure a is the correction clock pulse CP1, Figure 4 b, c
are the sampling pulse P ₀ and the data D. Also, d in the same figure is the output of the latch circuit 55, and e to m in the same figure.
is the output information of the shift registers 56 and 57, n is the latch pulse applied to the latch circuit 59, o is the output information D ₄ , and p is the output information D ₀
~ _D3 , _D5 ~ _D7 . Next, as shown in Fig. 5, if the phase of data D is ahead of the sampling pulse P ₀ by 90° to 180°, that is, if the sampling pulse P ₀ is delayed by 90° to 180°, , output information _D0 to _D7 are set to be "00000100". Fifth
Figure a shows the correction clock pulse CP ₁ , and figures b and c show the sampling pulse P ₀ and data. d in the figure is the output of the latch circuit 55, e to m in the figure are output information of the shift registers 56 and 57, n in the figure is the latch pulse applied to the latch circuit 59, o is the output information _D5 , p is output information D ₀ ~ D ₄ , D ₆ ~ _{D 7}
It is. Next, as shown in Figure 6, the sampling pulse
If P ₀ is leading the data by 0° to 90°, then
The output information _D0 to _D7 is set to be "00000010". Figure 6a shows the correction clock pulse
CP ₁ , b and c in the figure are the sampling pulse P ₀ and data. Also, d in the same figure is the output of the latch circuit 55,
The figures e to m are the output information of the shift registers 56 and 57, the figure n is the latch pulse applied to the latch circuit 59, the figure o is the output information _D6 , and the figure p is the output information _D0 to _D5 , _D7. It is. Next, as shown in Figure 7, the sampling pulse
If P ₀ is leading the data by 90° to 180°, then
The output information _D0 to _D7 is set to be "00000001". Figure 7a shows the correction clock pulse
CP ₁ , b and c in the figure are the sampling pulse P ₀ and data. Also, d in the same figure is the output of the latch circuit 55,
Figures e to m are output information of the shift registers 56 and 57, n is a latch pulse applied to the latch circuit 59, o is output information _D7 , and p is output information _D0 to _D6 . As mentioned above, the conversion table shown in Table 1 is set in advance in the converter 10E. Information representing the phase relationship as described above is input to the delay amount control means 10B. The delay amount control means 10B is composed of up-down counters 63 and 64 and OR circuits 65 and 66. The previous information _D4 is applied to the down-count command signal input terminal of the up-down counter 63, and the information _D6 is applied to the up-count command signal input terminal. The carry output of the up-down counter 63 is applied to the second input terminal of the OR circuit 65. Information _D7 is applied to the first input terminal of this OR circuit 65, and the signal obtained at the output terminal is applied to the up-count command signal input terminal of the up-down counter 64. Further, the borrow output of the up-down counter 63 is applied to the first input terminal of the OR circuit 66. Information D ₅ is applied to the second input terminal of this OR circuit 66, and the signal obtained at the output terminal of this OR circuit 66 is applied to the down-count command signal input terminal of the up-down counter 64. Since the delay amount control means 10B is constructed as described above, its up-count or down-count output is varied depending on the input of the information _D4 to _D7 . The output information of the up-down counters 63 and 64 is applied to the control terminal of the selection circuit 68 of the delay means 10A. The delay means 10A is a delay circuit 69
and a selection circuit 68. Delay circuit 69 delays the original clock pulse at input terminal 50 to different phases at various points, and applies each delayed pulse to each corresponding input terminal of selection circuit 68. This selection circuit 68 derives the phase of any one of the delayed clock pulses based on the control information applied from the up-down counters 63 and 64, and uses this as a correction clock pulse. Therefore, when the original clock pulse is corrected by the delay means 10A and derived as a corrected clock pulse, the content of the output control information of the up-down counters 63 and 64 determines the correction amount. Become. According to the delay amount control means 10B, when the phase shift between the data and the sampling pulse is large, the correction amount is increased to quickly obtain an appropriate sampling pulse, and when the phase shift is small, the correction is performed. It is characterized by the ability to make fine phase adjustments (the phase of the sampling pulse) by reducing the amount. That is, the output information D ₄ and D ₆ which becomes logic "1" when the phase difference between the data and the sampling pulse is 90 degrees or less is the up count command signal input of the up down counter 63 which is in charge of the lower bits of the control information. terminal, applied to the down count command signal input terminal. Furthermore, the output information D ₅ and D ₇ which becomes logic "1" when the phase difference between the data and the sampling pulse is large and is between 90° and 180° is sent to the up-down counter 64 which is in charge of the upper bits of the control information.
It is directly input to the up count command signal input terminal and the down count command signal input terminal of , via OR circuits 65 and 66. Therefore, the output information D ₅
Alternatively, when _D7 becomes logic "1", the delay amount of the clock pulse is greatly corrected, and the time required to obtain an appropriate sampling pulse is shortened. Next, a control system regarding the data slice level will be explained. The basic information regarding the slice level is the output information D ₀ to _{D 3} from the converter 10E.
It is. Table 2 below shows information A ₀ to _{A 8} and converter 1 when the slice level of the slice circuit is a little too high.
The relationship between output information D ₀ to D ₇ of 0E is shown. If the slice level is a little too high, D ₀ to D ₇ will be "10000000". Information D ₀ is then applied to the down-count command signal input terminal of the up-down counter 71. Table 3 also shows information A ₀ to _{A 8} and converter 10 when the slice level of the slice circuit is too high.
The relationship between the output information D ₀ to _{D 7} of E is shown. If the slice level is too high, _D0 to _D7 will be "01000000". The output information D ₁ is then applied to the down-count command signal input terminal of the up-down counter 72 via the OR circuit 74 . Furthermore, Table 4 shows information A ₀ to _{A 8} and converter 10 when the slice level of the slice circuit is a little too low.
The relationship between the output information D ₀ to _{D 7} of E is shown. If the slice level is a little too low, _D0 to _D7 will be "00100000". The output information _D2 is then applied to the up-count command signal input terminal of the up-down counter 71. Table 5 also shows the information A ₀ to _{A 8} and the converter 10 when the slice level of the slice circuit is too low.
The relationship between the output information D ₀ to _{D 7} of E is shown. If the slice level is too low, _D0 to _D7 will be "00010000". The output information _D3 is then applied to the up-count command signal input terminal of the up-down counter 72 via the OR circuit 73. As mentioned above, in the output information _D0 to _D3 , if the slice level is a little too high, only information _D0 becomes logic "1", and if the slice level is too high, only information _D1 becomes logic "1". Become.
Also, if the slice level is a little too low, the information
Only D ₂ becomes logic "1", and if the slice level is too low, only information D ₃ becomes logic "1"
becomes. Up-down counters 71, 72, OR circuit 7
3,74 are the previous up-down counters 63,6
4. Operation similar to OR circuits 65 and 66 is obtained. That is, when an up-down count or down-count command signal is input to the up-down counter 72, the upper bits of the output information constituted by the up-down counters 71 and 72 are varied.
Therefore, when a command signal is directly input to the up-down counter 72, the analog output of the digital-to-analog converter 10F is roughly varied. Also up-down counter 71
If an up-count or down-count command signal is input to the digital-to-analog converter 1,
The analog output of 0F will be finely varied. Next, the necessity of setting the data slice level to an appropriate level in the slice circuit 10G will be described. In other words, the data input to the input terminal 52 has a waveform as shown in FIG. 8a,
If the appropriate slice level is _S1 as shown in the figure, the output will have a duty as shown in figure b.
It becomes a 50% square wave signal. For example, this data is converted into a clock pulse with twice the frequency (as shown in figure c).
By sampling the data, it is possible to obtain an accurate digital conversion code of the data. However, when the slice level changes to _S2 as shown in the figure, the output data of the slice circuit 10G becomes as shown in FIG. 8d. If this is sampled with a data sampling pulse (shown in e of the same figure), the ? An ambiguous part occurs in the code at the position indicated by , and accurate sampling cannot be obtained. Therefore, it is necessary to set the slice level to an appropriate level. As mentioned above, the present invention not only automatically adjusts the phase of the sampling clock pulse, but also automatically adjusts the slice level of the data being sent to accurately extract data. Therefore, it is possible to provide a sampling pulse correction method that can obtain a sampling pulse that can perform a high speed correction, and in particular can perform a fast correction operation.

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【table】 [Brief explanation of drawings]

1A to 1D are explanatory diagrams showing the format of television signals used in teletext broadcasting, FIG. 2 is an explanatory diagram of the configuration of a system for processing data of teletext broadcasting signals, and FIG. Circuit configuration diagrams showing one embodiment, Fig. 4 a-p, Fig. 5 a-
6, a to p, and 7, a to p, are signal waveform diagrams shown to explain an example of the operation of the circuit in FIG. 3, and FIG. 8, a to e, are data slice levels and sampling pulses. FIG. 3 is a signal waveform diagram shown to explain the relationship between 10A...Delay means, 10B...Delay amount control means, 10C...Slice level control means, 10D
...Digital phase detection means, 10E...Converter,
10F...Digital analog converter, 10G...
slice circuit.

Claims (1)

[Claims] 1. A slicing means for slicing data to be extracted according to a set slicing level, and a sampling clock having the same frequency as that for sampling the data sliced by the slicing means, a pulse train generating means for generating pulse trains each having a different phase; and a pulse train for selecting and outputting one of the pulse trains generated from the pulse train generating means as the sampling pulse according to set pulse selection data. selection means; sampling at least one cycle period of the clock synchronized portion of the sliced data at a frequency at least four times that of the sampling pulse output from the pulse train selection means, and determining the phase of the sampling pulse and the slice level; and a phase correction including a correction direction and correction amount for setting the phase of the sampling pulse and the slice level to an appropriate phase and level based on the detection result of the state detection means. correction data output means for outputting data and level correction data; and correcting the pulse selection data by the correction amount of the phase correction data in the correction direction of the phase correction data output from the correction data output means to select the pulse train. and a level correction means that corrects the slice level by the correction amount of the level correction data in the correction direction of the level correction data output from the correction data output means and sets it in the slice means. A sampling pulse correction method characterized by comprising the following.