JP2502131Y2 - Karakuri Alarm Control Circuit - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a wake-up alarm that pushes out and stores a decorative body at a predetermined time, and more particularly to storage control of the decorative body.

[0002]

2. Description of the Related Art In recent years, a mechanical clock that operates a decorative body and enjoys its movement has become popular for household use. In particular, the time signal clock is at the forefront, and the doll operates at the hour. As described above, the clock is required not only to know the time but also to have a function of softening the atmosphere of figurines, movements, music and the like. In order to ensure the operation of the ornament, the ornament is stored by the initial reset.
According to the publication No. 2291, it was forcibly stored by a reset signal when the decorative body was not stored.

[0003]

[Problems to be Solved by the Invention] In the above-mentioned conventional forced storage system, even if it should be operated, it is ignored, so it may be unnatural and may be considered to be a failure. I had to confirm. An object of the present invention is to provide a reset operation that does not give a feeling of strangeness to the user by paying attention to such a point and making the operation natural.

[0004]

In order to achieve the above object, the present invention outputs an alarm operation signal in response to an ON signal of a reference switch that detects a predetermined time when a silence switch is turned on. The alarm sound is generated and the decorative body such as a doll is moved by a motor that can rotate forward and backward, and the decorative body is housed in the initial position when the alarm operation signal is stopped. A reset operation control circuit for outputting the alarm operation signal for a predetermined time in response to a reset switch for returning to the state is provided.

[0005]

[Function] BG of code 0 due to generation of alarm operation signal
While playing M (back music), the normal rotation control circuit causes the motor to rotate in the forward direction to push the decorative body to a predetermined position.
When the doll is hit with a bell by the forward rotation control again, at the same time the sound of code 2 is played and the sound is stopped and the BGM of code 0 is played by auto stop or snooze operation, while the reverse rotation control circuit reverses the motor and stores the ornament. In the Karakuri alarm, when the power is turned on by replacing the battery when the Noh decoration is stopped in the middle due to a drop in the battery voltage, etc., a single pulse is output from the reset operation control circuit as an alarm operation signal. The alarm output state is set to the alarm time operation, and then the alarm is turned off by the falling edge of the single pulse, whereby the decoration body is stored.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a control circuit for an alarm clock according to an embodiment of the present invention. Snooze switch 2, anti-squeeze switch 4, reference switch 6, monitor switch 8, front switch 10 for detecting that the decorative body is pushed out to a predetermined position, rear switch 12 for detecting that the decorative body is housed, initial state Reset switch 14, an alarm signal control circuit 16 for inputting an alarm operation signal generated by turning on the stop ring 4 and the reference switch 6 and a snooze signal from the snooze switch 2 and outputting an alarm output signal,
A normal rotation control circuit 18 for pushing out the ornament in response to the output of the alarm output signal, a melody is selected in response to the alarm output signal and the front switch 10, and an output instruction signal for instructing the output of sound is output. Front switch 1
When 0 is turned on, the normal rotation control circuit 18 is operated again,
In response to the stop of the alarm output signal, the sound output control circuit 24 which operates the reverse rotation control circuit 20 to be described later to stop the output instruction signal in response to being housed and is selected by the output instruction signal. Voice IC2 that outputs the sound of the chord
8, a sounding circuit 50 that amplifies and outputs a signal from the voice IC 28 according to the output instruction signal, a reverse control circuit 20 that stores and operates the decorative body in response to the stop of the alarm output signal, and the normal / reverse rotation. A motor 26 for moving the decorative body based on signals from the control circuits 18 and 20, and a reset operation control circuit 22 for generating a single pulse alarm output signal by turning on the power source or a reset switch to store the decorative body. Has been done.

Next, the operation will be described with reference to FIGS. 2, 3 and 4 which are detailed circuit diagrams of each block. FIG. 2 shows an alarm signal control circuit 16 and a reset operation control circuit 22. The alarm signal control circuit 16 is composed of a switch signal output circuit 32 and a timer control circuit 78. The reference switch 6 is closed at a predetermined time when the alarm is set. The switch signal that has become L level due to the closing of the reference switch 6 is input to the OR gate 82, the output thereof is inverted to L level, and the FF 8 is supplied via the inverter 84.
6. The reset of the counter 88 is released, the output of the NOR gate 110 is inverted to the H level, and the FF 100, 1
The reset of 02 is also released. On the other hand, this switch signal goes to H level via the inverter 36 and the OR gate 36.
The level signal is input to the NAND gate 38. The inverted Q output of the flip-flop (hereinafter referred to as FF) 102 is input to the other input terminal of the NAND gate 38, but the output of the counter 88 is still at L level, so the inverted Q output is at H level and the NAND gate 38 has The output will be inverted to the L level. Therefore, Q of FF108
The NOR gate 40 which inputs the L level which is the output outputs the H level to release the reset of the FF 42, and the OR gate 4
An inverted ALIS signal which is an alarm output signal is output via 4. This signal is output as an H level ALIS signal through the inverter 46, and the FF 48 is set to invert the inverted Q output to the L level to invert ALBS.
The Y signal is output and the ALBSY signal is output via the inverter 50.

ALBSY output from the inverter 50
The signal closes the AND gate 92 through the inverter 83, opens the AND gate 94, and inputs Φ2 to the other terminal, and the Φ2 signal is output from the AND gate 94.
This signal is sent to the counter 88 via the NOR gates 96 and 98.
Is input to Further, a single pulse is generated as an ALSTA signal from the exclusive NOR gate 70 by the ALBSY signal, so that the FF 86 and the counter 8 are temporarily provided.
8 is reset. When the counter 88 counts a certain period of time, the NOR gate 98 is closed and the Q of the FF 102 is inverted.
The output is inverted to the L level and the output of the NAND gate 38 is changed to the H level.
The level is inverted to set the FF 42 in the reset state, and the ALIS signal output from the inverter 46 is also inverted to the L level. Therefore, only the inverted ALBSY signal holds the L level. Further, even if the deadening switch 4 is turned off before a certain period of time, the H-level signal is input to the OR gate 82, so that the FF 86 and the counter 88 are in the reset state and the output of the NAND gate 38 is in the H level and the FF 42 is also in the reset state. As ALIS
The signal is inverted to L level. After this, the counter 88
The inverted ALBSY signal holds the L level as in the case of counting up. This inverted ALBSY signal is an L-level single pulse output when the stage is housed by the reverse control circuit 20 from the sound output control circuit 24 which will be described later, and the inverted Q output of the FF 48 becomes the H level by the inverted ALEND signal. The ALBSY signal output through the inverter 50 becomes L level and the NOR gate 80
Is set to the H level, the counter 88 is reset to return to the initial state.

If the snooze switch 2 is operated before the counter 88 counts a fixed time, the Q and inverted Q outputs of the FF 42 are inverted to H and L levels, respectively, and the FFs 100 and 102 are turned on by the SNZ signal of the Q output. It will be in the reset state. Further, the RAD signal, which is a reverse rotation instruction signal from the sound output control circuit 24 described later, becomes the H level, the counter 88 is reset, and the reverse control circuit 20 stores the stage. ALE
The ND signal causes the inverted Q output of the FF 32 to be at the H level, and the ALBSY signal output via the inverter 50 is at the L level.
Open the AND gate 92, close the AND gate 94, and close the exclusive NOR gate 70.
The FF 86 and the counter 88 are once reset by outputting a single pulse from. Further, the NOR gate 104 is also an open pair. Therefore, after counting the signals of Φ2 divided by 2,
The above operation is repeated by inverting the output of the NOR gate 40 to the L level by the Q output of the FF 108 and resetting the FF 42.

Reference numeral 22 denotes a reset operation control circuit which outputs an L level inverted RES signal as a reset signal from the reset circuit 72 when the power is turned on or the reset switch 14 is operated to reset each FF and set the initial state. This signal becomes H level after a predetermined time. As a result, when the output of the AND gate 54 is at the H level, the FF 56 outputs the Q output to the OR gate 36 of the alarm signal control circuit 16 as the H level, which is similar to the state where the switches 4 and 6 are closed and becomes the L level. Inversion ALI
S, an inverted ALBSY signal is output. This inversion ALB
The output of the SY signal causes the FF66 via the inverter 50.
Is input to the exclusive NOR gate 70, and the inverted Q output of the FF 62 is set to L level to close the AND gate 54, and the Q output of the FF 56 is also set to L level to stop the output to the OR gate 36. Therefore, when the signal from the rear switch 12 is input to the other input terminal of the AND gate 54 and the storage state is not set, a pseudo alarm output signal is output to perform the storage operation.

FIG. 3 shows a forward rotation control circuit 18 and a reverse rotation control circuit 2.
0 is shown and the front switch 10 is in the stored state.
Is open and the rear switch 12 is closed. Normally, the output of the NAND gate 122 is at H level, the output of the NAND gate 154 is also at H level, the transistors 176, 178, 180, 182 are closed, and the motor 184 is stopped. When the L level inverted ALIS signal is generated from the alarm signal control circuit 16, the FFs 118 and 120 are released from the reset state, the Q output of the FF 120 becomes H level, and the output of the NAND gate 122 becomes L level.
As a result, the transistors 176 and 182 are turned on and the motor 184 rotates in the normal direction. After that, when the front switch is closed, the output of the NAND gate 114 becomes L level and the output of the NAND gate 122 becomes H level to turn off the transistors 176 and 182 to stop the motor 184. When the front switch 10 is closed, the output of the NOR gate 140 becomes H level and the FF13
Release the reset of 4. After that, when the output from the voice IC is completed, the BUSSY signal becomes L level and the counter 1
28 operates and counts up and NAND gate 11
4 outputs H level, the output of the NAND gate 122 becomes L level again, and the motor 184 rotates forward. At this time, the doll (not shown) performs a bell-striking operation by operating the hand part of the doll by the slip mechanism. In this operation, the ALIS signal (reverse ALIS signal) is L
At the level (H level), the counter 128 is reset and stopped.

The reverse rotation control circuit 20 is the forward rotation control circuit 18
With the operation of, the rear switch is turned off and becomes H level, and the signal is output as an inverted SR signal. In response to the L level inverted RAD signal from the FF 228 of the sound output control circuit 24, which will be described later, the reset of the FFs 158 and 160 and the counter 168 is released, the Q output of the FF 160 is set to the H level, and the output of the NAND gate 154 is inverted to the L level. The transistors 180 and 178 are turned on and the motor 184 is operated in the reverse direction to be housed. When stored, the rear switch 12 is closed, the NOR gate 152 becomes L level, the output of the NAND gate 154 is inverted to H level, the transistors 180, 178 are turned off, and the motor 184 is turned off.
Stops. Incidentally, the counter 168 is for storing the motor 184 forcibly when the motor 184 is operating without being stored even after a certain period of time.

FIG. 4 shows a sound output control circuit 24, which receives the inverted ALBSY signal, the inverted ALIS signal, the ALIS signal, and the inverted SNZ signal from the alarm signal control circuit 16, which will be described with reference to the alarm signal control circuit 16. When the noise stop switch 4 and the reference switch 6 are closed as described above, A
The LIS signal becomes H level and the inverted ALBSY signal becomes L level. The inversion ALBSY signal activates the sounding circuit 30, and the NOR gate 22 for inputting these both signals.
The output of 4 becomes L level, and FF198, 214, 21
6, 226 and 228 are in a reset state. At this time, the output of the inverter 234 is L level, and the output of the NOR gate 236 which inputs this signal and the ALIS signal is L level.
Level. Further, the inverted SFF signal is at the H level because the ornament is in the housed state and the front switch 10 is off.
The output of the NOR gate 240 which inputs this signal and the ALIS signal through the inverter 238 also becomes L level. The output sound of the voice IC is determined by the output states of the NOR gates 236 and 240, and the sound of code 0 is selected. In addition, the FF 190 which inputs the inverted ALIS signal
Inverts the inverted Q output to the H level and the Q output of the FF 192 to the L level, and NOR gate 1 for inputting both outputs
The output of 94 is L level and does not change. This signal is inverted via the NOR gate 210 to change the H level to the voice IC.
The reset signal is input to the inverted RES terminal of the above. Further, since the NAND gate 204 inputs the L level of the Q output signal of the FF 200 and the H level of the inverted Q output of the FF 202, its output is at the H level,
The output of the AND gate 206 for inputting this signal, the inverted SRO signal of H level from the reverse control circuit 20 and the inverted SFO signal of L level during the operation of the normal control circuit 18 becomes L level to operate the voice IC. The sound of code 0 is input to the inversion ST terminal and output through the sounding circuit. At this time, the voice IC outputs an inverted BUSSY signal indicating that it is in operation and outputs it as an H level BUSSY signal to the normal rotation control circuit through the inverter 250.

After that, when the ornament reaches a predetermined position and the front switch 10 is turned on, the inverted SFO signal becomes H level, the output of the AND gate 206 becomes H level, and when the output of the predetermined sound is finished, the BUSSY signal becomes L level. Flip to. At this time, the inverted SFF input to the NOR gate 240
Since the signal is at L level, 2 is selected as the sound code. After a predetermined time, the inverted SFO becomes L level again, and the bell 2 of the code 2 is output. Here, when the counter 88 of the alarm signal control circuit 16 times out or the deadening switch 4 is turned off, the ALIS signal is inverted to L level and FFs 198, 214, 216, 226, 2
Since the reset of 28 is released and the inverted ALIS signal is inverted to the H level and the Q and inverted Q outputs of the FFs 190 and 192 are also inverted to the H and L levels, respectively, a single pulse is output through the NOR gate 194 and the NOR gate 210 is output. Through L
A level single pulse is output and the voice IC 28 is once reset. At this time, the motor 184 is stopped and the inverted SFO signal is at H level, and the voice IC 28 is not operating, but the output of the FF 198 becomes H level in synchronization with the fall of the single pulse of the NOR gate 194, and the NAND gate 204 is operated. L level single pulse is generated from the sound I
Operate C28 and start FF22
The Q output of 6 is inverted to H level. At this time, the NOR gates 236 and 240 are at the H and L levels, respectively, to select the sound of chord 1. The voice of the code 1, for example, "Good morning" is output from the voice IC 28. When the voice output of this code 1 is completed, the inverted BUSSY signal becomes H level and the inverted Q output of FF 228 becomes L level and inverted RAD
The signal is output to the reverse rotation control circuit 20 to start the storing operation, and the output of the NOR gate 236 is set to L level to select the code 0 and the inverted SRO signal becomes L level, and the AND gate 206 becomes L level to operate the voice IC. Then, the selected sound is output.

When the ornament is stored, the inverted SRO signal becomes H.
The level becomes the level, the operation of the voice IC 28 is terminated, and the Q output of the FF 214 is set to the H level. When a predetermined sound is output, the inverted BUSSY signal becomes H level and FF216
To the H level. This makes the NAND gate 22
From 2, the L level single pulse is output as the inverted ALEND signal, the inverted ALBSY signal becomes the H level, and the operation of the tone generation circuit 30 is also stopped to return to the initial state.
When the snooze switch 2 is operated during operation, the inverted SNZ signal of L level is input, so that the output of the NAND gate 204 does not change, the AND gate 206 becomes H level, and the operation of the voice IC 28 is terminated, and F
The Q output of F228 is set to H level, and the storing operation is performed while playing the sound of code 0 in the same manner as the above operation.
A signal is output and the inverted ALBSY signal is set to H level.
After that, when the counter 88 of the alarm signal control circuit 16 times up and the FF 42 is reset, the ALIS signal becomes H level and the above operation is repeated.

[0016]

As described above, the control circuit of the karakuri alarm of the present invention uses the alarm operation signal when the silence switch 4 and the reference switch 6 are turned on.
M is configured to operate, and when the reset switch 14 or the battery is turned on in a state where the ornament is not stored, a simple circuit configuration in which a pseudo alarm operation signal is output for a single time is set to the initial state. Can be returned to. Moreover, when the switches 4 and 6 are turned on when the battery is turned on and the switch is in the operating state, the naturally set operation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control circuit for a mechanical alarm clock according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an alarm signal control circuit and a reset operation control circuit.

FIG. 3 is a circuit diagram of a forward rotation control circuit and a reverse rotation control circuit.

FIG. 4 is a circuit diagram of a sound output control circuit.

[Explanation of symbols]

2 Snooze switch 4 Silence stop switch 6 Reference switch 8 Monitor switch 10 Front switch 12 Rear switch 14 Reset switch 16 Alarm signal control circuit 18 Forward rotation control circuit 20 Reverse rotation control circuit 22 Reset operation control circuit 24 Sound output control circuit 26 Motor 28 Voice IC 30 sounding circuit

Claims (1)

(57) [Scope of utility model registration request] 1. A doll by a motor capable of rotating forward and backward while outputting an alarm operation signal in response to an ON signal of a reference switch that detects a predetermined time when a sound stop switch is ON In the control circuit of the wake-up alarm, which moves the ornament such as the ornament and stores the ornament at the initial position by stopping the alarm operation signal, a reset switch for turning on the battery or returning the initial state when the ornament is not in the initial position. In response to the above, a reset operation control circuit for outputting the alarm operation signal for a predetermined time is provided, and a control circuit for a wake-up alarm.