JPH0248914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tempo control device for an automatic performance machine (for example, an electronic organ with an automatic performance machine, an autorhythm device, an auto bass chord device, an auto arpeggio device, etc.), and particularly relates to a tempo control device for an automatic performance machine, such as an electronic organ with an automatic performance machine, an auto rhythm device, an auto bass chord device, an auto arpeggio device, etc. The present invention relates to a device that allows the performance tempo of an automatic musical instrument to be set to a desired value in conjunction with a person's normal time signature motion.

The present applicant has previously proposed various types of automatic performance machines (for example, an electronic organ with an automatic performance function, an autorhythm device, an auto bass chord device, an auto arpeggio device, etc.). The performance tempo of these automatic musical instruments is determined in synchronization with a clock signal called a tempo clock, and therefore, the performance tempo can be arbitrarily changed by changing the frequency of this tempo clock.

Conventionally, in order to change the performance tempo, a voltage controlled oscillator (hereinafter referred to as VCO), for example, was used as a tempo clock oscillator, and a control voltage for this was applied via a sliding or rotary variable resistor. The frequency of the tempo clock can be continuously changed by sliding or rotating the operator of the variable resistor.

However, as is well known, the actions that a person takes or gives instructions during a musical performance include, for example, swinging a conductor's baton, stepping, and tapping a desk, etc. This is far from the slide or rotation operations of a child, and it must be said that it is extremely difficult to quickly and accurately set the performance tempo of an automatic musical instrument to a desired tempo using such slide or rotation operations. I don't get it.

This invention was devised in view of the above-mentioned difficulties in setting the tempo of conventional automatic musical instruments, and its purpose is to enable a person to set the playing tempo on this type of automatic musical instrument in a way that would not normally be possible. The objective is to be able to set an arbitrary tempo depending on the action of taking the time signature.

Therefore, in the present invention, there is provided an external operator means having a pulse generating means that generates pulses in synchronization with the operation timing, and a pulse generator provided in the main body of the automatic musical instrument that outputs the pulses one after another from the pulse generating means. measuring means for measuring the time interval of and outputting tempo control data corresponding to the measured time interval; and a measuring means provided in the automatic performance machine main body for storing a plurality of the tempo control data sequentially output from the measuring means. and an averaging means provided in the automatic performance machine body for averaging the values of a plurality of tempo control data stored in the storage means;
Tempo clock generating means, which is provided in the main body of the automatic performance machine and generates a tempo clock for controlling the performance tempo of automatic performance, the frequency of the generated tempo clock being controlled in accordance with the output of the averaging means. The present invention is characterized in that the pulse generating means is configured to be connected to the automatic performance machine main body via a wireless transmission means.

The present invention will be described in detail below based on examples.

Fig. 1 is an overall block circuit diagram showing the case where the present invention is applied to an electronic organ with an automatic performance function as an example of an automatic performance machine, and Fig. 2 shows a tempo clock generation control circuit which is the main part of the present invention. 3 is a block circuit diagram showing the data format in the data memory, FIGS. 4, 5, and 6 are structural diagrams showing an example of the tempo setting pulse generating means, and FIGS. FIG. 13 is a timing chart showing the temporal relationship of each signal in the tempo clock generation control circuit.

In Figure 1, 1 is the key switch group of the upper keyboard (UK), 2 is the key switch group of the lower keyboard (LK),
3 shows key switch groups of a pedal keyboard (PK), and each key code generated from these key switch groups 1, 2, and 3 is transmitted through a melody sound generation circuit 4, an accompanist generation circuit 5, and a bass sound generation circuit 6. Each of the signals is converted into a musical tone signal and outputted as a musical tone via a sound system 7 consisting of a main amplifier, speakers, etc.

Reference numeral 8 denotes a pattern memory for storing rhythm patterns, and in this pattern memory 8 there are, for example, 128 addresses that are sequentially addressed by the output of an address counter 9 whose advance is controlled by a tempo clock TCL, which will be described later. , the memory content of each address corresponds to whether or not a rhythm sound is produced in each section where the time length of two measures is equally divided into 1/128. Therefore, when the address counter 9 increments in synchronization with the tempo clock TCL, a rhythm timing signal is output from the pattern memory 8 in chronological order, and this signal is converted into a rhythm sound signal via the rhythm sound source 10. Furthermore, it is output as rhythm sound via the sound system 7.

Next, reference numeral 11 is a memory in which various performance data are stored (hereinafter referred to as data memory). In this example, the data memory 11 uses RAM so that it can be rewritten according to the desired song number. As shown in the figure, a system is employed in which performance data magnetically recorded along the lower part of a musical score 12 is scanned and read by a reading device 13 and written into a data memory 11.

On the other hand, performance data, as the name suggests, refers to various data necessary for performance.In this embodiment, performance data includes a note code representing the note name of the key to be pressed in the UK, and an octave representing the octave to which the note belongs. chord, note length code that represents the length of the note, root note code that represents the root note of the chord to be played with LK, type of chord (for example,
Major, Minor, 7th, Minor 7th, etc.) Type code indicating the end of the song
It consists of a FINISH code and an identification code that identifies these various codes.

Each of the encoded performance data is stored at each address in the data memory 11 according to a predetermined format, as shown in FIG. In other words, each address in the data memory 11 has a storage capacity of 8 bits, and the contents of each address marked "UK", "LK", "note length", and "FINISH" in the figure are shown by the arrows in the figure. It is structured as follows.

(i) "UK"; the upper two bits b ₁ and b ₂ store an identification code "10" indicating that the data is related to the UK. UK for 3rd and 4th bits b ₃ and b ₄
An octave code indicating the octave to which the note to be pressed belongs is stored. In this octave code, for example, the first to fourth octaves correspond to 2-bit binary codes "00" to "11". The 5th to 8th bits _b5 to _b8 contain note codes indicating the note names (notes) to be played in UK.
It is stored in bit binary code. For example, the 12 tones of C, C#, D, D#...A#, B are made to correspond to the binary codes "0001" to "1100".

(ii) "LK"; the upper two bits b ₁ and b ₂ store an identification code "01" indicating that the data is related to LK. LK for 3rd and 4th bits b ₃ and b ₄
The type of chord you should type (for example, Major,
Minor, 7th, Minor 7th) is stored. In this example, Major "00",
There is a relationship between Minor "01", 7th "10", and Minor 7th "11". In the fifth to eighth bits _b5 to _b8 , a root note code indicating the root note of the above code is stored. In this example, the 12 root tones of C, C#, and -B are made to correspond to the 4-bit binary code "0000" to "1011."

(iii) “Note length”; the upper two bits b ₁ and b ₂ contain an identification code “00” indicating that the data is related to note length.
is memorized. The 3rd to 8th bits _b3 to _b8 contain a tempo clock corresponding to 1/64th of a whole note.
A note length code is recorded that indicates the note length using the TCL count value.

(iv) "FINISH"; The 1st to 8th bits store an end code "11111111" indicating the end of the song.

(v) Others; UK identification code “10” is stored in the first and second bits b ₁ and b ₂ , and the third to eighth bits b ₃
Setting all the values of ~ _b8 to 0 indicates a UK rest, and storing the note length code in the 3rd to 8th bits _b3 to _b8 of the following note length address indicates a rest. It shows the length of.

In the above configuration, when the power is turned on, the initial clear circuit (not shown) is driven and the initial clear pulse IC is sent to the RS via the OR gate 14.
Flip Flip (hereinafter simply referred to as RSFF)
15, and its output "1" resets the address counter 16 to the first address. Further, the initial clear pulse IC is also supplied to the reset input R of the RSFF 19 via the OR gate 18 to disable the AND gate 20.

Next, when the start switch 21 is closed, a start pulse SS is outputted from the differentiating circuit 22 in synchronization with the rise of its output. This start pulse SS is supplied to the set input S of RSFF19,
Due to the Q output "1", the inhibition of the AND gate 20 is released, and the
It is also supplied to the reset input R of the RSFF 24, and its Q output "0" disables the AND gate 25. Furthermore, the start pulse SS is RSFF1
The pulse SS is also supplied to the set input S of the RSFF 27 through the OR gate 26, and its output "0" enables the address counter 16 to increment. , the address counter 9 for the pattern memory 8 is reset by the Q output "1".

Next, a tempo setting pulse generator 28, which will be described later,
Tempo setting pulse ON that occurs with the operation of
is passed through AND gate 20 and OR gate 29
When fed to the set input of RSFF24, its Q
The AND gate 25 is disabled by the output "1", and the address counter 16 starts incrementing in response to the clock φ, and this tempo setting pulse
ON is also supplied to the reset input R of RSFF27,
The Q output "0" enables the address counter 9 to increment, and from then on, the tempo clock, which will be described later, is activated.
The TCL is started to be counted, and accordingly, the pattern memory 8 outputs a rhythm timing signal in time series as described above, and the rhythm timing signal is converted into a rhythm sound via the rhythm sound source 10 and the sound system 7. In addition, the tempo setting pulse ON is applied to a D-type flip-flop (hereinafter simply DFF) via an AND gate 20.
) 17, and after being delayed, it is supplied to the reset input R of the RSFF 19 via an OR gate 18. As a result, the Q output of RSFF19 becomes “0”, and the AND gate 20 receives the start pulse.
Banned until SS occurs again. This means that
This is because it is necessary to start the address counter 16 with the first pulse of the tempo setting pulse ON, and to prevent the address counter 16 from incrementing with subsequent pulses.

When the address counter 16 starts incrementing, the data contents of each address of the first data group marked as "UK", "LK", and "note length" in FIG. 3 are sequentially 8 bits on the common bus 30. If the UK, LK, and note length identification codes are present in the upper two bits of the data that is output in parallel and read out sequentially, the UK code detection circuit 31, LK code detection circuit 32, and note length code detection circuit 33 each The latch circuit 34 receives the lower 6 bits of the UK data, and the latch circuit 35 receives the lower 6 bits of the LK data.
Furthermore, the lower 6 bits of the code length data are latched in the latch circuit 36. When the note length data is latched in the latch circuit 36, the detection output "1" of the note length code detection circuit 33 is
It is supplied to the reset input of RSFF24 via OR gate 23, and its Q output "0"
The gate 25 is inhibited, the address counter 16 stops advancing, and the detection output "1" resets the note length counter 37.
The counter 37 will begin counting the tempo clock TCL. And this note length counter 3
When the count value of 7 and the note length code latched in the latch circuit 36 match, the comparison circuit 38 outputs a match output.
EQ changes from "0" to "1", and in synchronization with the rising edge, the differentiation circuit 39 outputs a coincidence pulse EP. This coincidence pulse EP is supplied to the set input S of the RSFF 24 via the OR gate 29, and its Q output "0" disables the AND gate 25, and the address counter 16 receives the clock φ and starts incrementing. resume. Then, when the address counter 16 resumes incrementing, the contents of the second data group shown in FIG. Each note length code is latched in the circuit 36. At this time, since there is no LK data in the second data group as shown in FIG. 3, the data content of the latch circuit 35 remains the same as the LK code content in the previous data group. Then, at the same time that the note length code is latched in the latch circuit 36, the address counter 16 stops advancing in the same manner as described above, and the note length counter 37 starts counting the tempo clock TCL.
When the counted value matches the note length code latched in the latch circuit 36, the third
The data group is read onto the common bus 30, and in the same manner, every time the counted value of the note length counter 37 and the note length code of the latch circuit 36 match, the fourth and fifth
...Each data group is sent out sequentially onto the common bus,
It will be latched in each latch circuit 34-36. At this time, the latching period of each of the UK and LK codes, which are latched one after another in the latch circuits 34 and 35, is determined by the note length code included in the data group to which each code belongs, and as described above, this code is latched one after another by the latch circuits 34 and 35. Since the long chord represents the length of a note based on the tempo clock TCL, the UK chord and LK chord are latched into the latch circuits 34 and 35 at the timing and length at which the key should be pressed, respectively.

Next, when the FINISH code "11111111" is read while repeating the reading of each data group, the detection output "1" of the FINISH code detection circuit 40 is supplied to the reset input R of the RSFF 15 via the OR gate 14. , the address counter 16 is reset to the predetermined starting address again by the ^Q output "1".

On the other hand, the UK chord (octave chord + note chord) latched by the latch circuit 34 is automatically
After being decoded by the decoder 42 enabled by the UK performance switch 41, it is supplied to the melody sound generation circuit 43, and the melody sound generation circuit 43 outputs a melody sound signal, and this melody sound signal is further used as a sound. It is output as a melody sound via the system 7.

Furthermore, the LK code (type code + root note code) latched by the latch circuit 35 is decoded by the decoder enabled by the automatic LK performance switch 44.
After being decoded into note codes constituting a chord via the ROM 45, they are supplied to an accompaniment sound generation circuit 46, which outputs an accompaniment tone signal, and this accompaniment tone signal is further converted into a sound. It is output as an accompanist via the system 7.

Thus, according to this electronic organ, score 12
After setting it in the reading device 13, turn on the power,
Operate the start switch 21, tempo setting pulse generator 28, and also operate the automatic UK performance switch 4.
1. When the automatic LK performance switch 44 and the automatic rhythm performance switch 10a are turned on, the sound system 7 automatically plays the song written on the musical score with melody, accompaniment, and rhythm sounds; The tempo of the song being played is determined based on the frequency of the tempo clock TCL; if the frequency of the tempo clock TCL is high, the tempo of the song is fast, and conversely, if the frequency of the tempo clock TCL is low, the tempo of the song is slow.

In particular, in this embodiment, the frequency of the tempo clock TCL can be quickly and reliably set to an arbitrary value by adjusting the operation timing of the tempo setting pulse generator 28, and the operation of the tempo setting pulse generator 28 can be controlled quickly and reliably. By stopping, the generation of the tempo setting pulse TCL can be stopped, and the progress of the automatically performed music piece can also be stopped at any time.

That is, first, some specific examples of the tempo setting pulse generator 28 will be explained with reference to FIGS. 4, 5, 6A, and 6B.

Figure 4 shows that in consideration of the fact that during music performances, people usually use actions such as stepping, clapping their hands, or tapping their desks to set the time signature of a piece of music or give instructions. It is configured so that a pulse synchronized with the timing can be generated by the operation accompanied by the timing.
In the illustrated example, contacts 48 are provided on a rigid substrate 47.
a, 48b are placed facing each other, and above them, an impact plate 49 made of a flexible plate is placed facing each other with an appropriate gap therebetween, and a conductive plate 50 for contact conduction is fixed to the lower surface of the shock plate 49. By hitting the impact plate 49 with your hand or a stick,
Alternatively, by stepping on the shock plate 49, conduction can be established between the contacts 48a and 48b, and the rise of the output from "0" to "1" due to the opening and closing of the contacts is controlled by a differentiating circuit 5.
1, the pulse is detected and converted into a pulse, and this pulse is set as the above-mentioned tempo setting pulse ON.

Fig. 5 is based on the fact that when a person normally performs music, in order to set the time signature of a piece of music or give instructions, a person performs a shaking motion such as shaking a baton.
It is configured so that a pulse can be generated in synchronization with the timing of such a rocking operation, and in the illustrated example, a hollow space 53 extending in the axial direction is formed in a rod-shaped member 52 such as a baton, and One contact piece 54 is attached to the inner end surface on the tip side of the space.
Also, facing this and normally biased backward via a spring 55, the rocking motion (arrow)
The other contact member 56 is built in so as to protrude toward the distal end side due to the centrifugal force accompanying the movement of the contact member 56, and a transmitting device 57 is also provided to transmit an electrical signal on a carrier wave as the contacts 54 and 56 open and close. Built-in,
On the other hand, on the main body side of the electronic organ, a receiving device 58 and a differentiation circuit 59 for detecting the rising edge of the received switching signal from "0" to "1" are provided to receive this signal. This device is configured so that the tempo of the automatic performance of the electronic organ can be arbitrarily set simply by a movement similar to shaking a conductor's baton.

Figures 6A and 6B show that pulses are generated in synchronization with the metronome's swing, considering that when a person normally takes the time signature of a piece of music during a musical performance, they often synchronize with the metronome's pendulum. In the illustrated example, the light emitter 62 and the light receiver 63 are placed opposite to each other across the swing trajectory of the pendulum 61 of the metronome 60, and the pendulum 6
Based on the interruption between the light emitter and receiver 62 and 63 due to the swing of 1, the rising edge of the pulse obtained from the light receiver 63 is detected via the differentiating circuit 64 and converted into a minute width pulse. It is configured so that the tempo setting pulse is turned on.

In this way, various configurations can be adopted as the tempo setting pulse generator 28, and in short, the tempo setting pulse generator 28 can be implemented by an action that a person normally performs when setting the beat of music, or an instrument that a person normally uses when setting the beat of music. A tempo pulse is generated in synchronization with the timing of the operation of a metronome (for example, a metronome). The tempo setting pulse ON outputted from the tempo setting pulse generator 28 is supplied as a control input to the tempo clock generation control circuit 65 as shown in FIG. Tempo clock with frequency according to ON cycle
TCL will be output. In other words, the longer the period of the tempo setting pulse ON, the higher the frequency of the tempo clock TCL, and conversely, the shorter the period of the tempo setting pulse ON, the higher the frequency of the tempo clock TCL.
The frequency of TCL also becomes low, and if the operation of the tempo setting pulse generator 28 is stopped, the tempo clock TCL will no longer be output.

FIG. 2 is a block circuit diagram showing a specific example of the above-mentioned tempo clock generation control circuit 65. The operation of this circuit will be explained below with reference to the timing charts of FIGS. 7 to 13.

First, to briefly explain the functions of the main blocks that make up this circuit, 66 is a tolerance range setter, and its function is to set the tolerance range when taking in the tempo setting pulse ON as a control input. . That is, the tolerance range setter 66
includes a standard tempo setting device 67 for setting the standard tempo based on a quarter note or eighth note, and a standard tempo setting device 67 for setting the standard tempo based on the standard tempo set by the standard tempo setting device 67. The tempo variable range setting device 68 is provided to set the vertical range in which the tempo is to be varied. In this example, there are three setting buttons consisting of "high", "medium", and "low", and the "medium" setting allows the tempo to be varied within equal widths above and below the reference tempo. To make it possible, the tempo setting is set to "high" so that the variable width is increased above the reference tempo (in the direction of becoming higher), and on the other hand, the variable width is reduced below (in the direction of becoming lower) than the reference tempo. In addition, in the "Low" setting, the variable width is increased below (lower direction) than the standard tempo, and the variable width is decreased above (higher direction) than the standard tempo. This makes it possible to change the tempo like this. That is, the tolerance range setter 6
From 6 onwards, parallel data (range setting data) indicating the contents of each of the above settings is output.

Reference numeral 69 is a data discriminator circuit that successively monitors the count value of a tempo counter 70, which will be described later, and at the same time that the count value falls within the range specified by the range setting data output from the tolerance range setter 66.
The EN output is configured to change from "0" to "1".

Reference numeral 71 is an averaging circuit configured to output an average value of data supplied to each input A, B.

72 is a selector configured to selectively output data supplied to each input A, B;
When select input SA is “1”, the data supplied to input A is “1”, and select input SB is “1”
In this case, the data supplied to input B will be selected.

Reference numeral 73 denotes a tempo clock oscillator, which is composed of a reference oscillator that generates a reference clock and a variable frequency dividing circuit that divides the output of this reference oscillator. is configured to be set by.

Reference numeral 74 denotes a tempo setter (manual) for manually setting the frequency of the tempo clock TCL to an arbitrary value without depending on the output of the averaging circuit 71, and the tempo setter 74 indicates each set tempo. Digital data is output in parallel.

75 is the tempo standard for automatic performance (for example, ♪ = 120,
This is a tempo standard setting device for setting the tempo standard (e.g. 〓 = 240), and in this example, it has two setting buttons 76 and 77 for setting the tempo standard as either a quarter note or an eighth note. is provided, and when each setting button 76, 77 is operated, digital data representing the number of tempo clock TCLs generated within a time corresponding to one beat of the standard tempo when performing automatic performance at the standard tempo is output. be done. For example, when performing automatic performance at a standard tempo (〓 = 120, etc.), the time corresponding to one beat at that tempo (for example, if one beat is based on a quarter note, 4 minutes) Assuming that 16 tempo clocks TCL are generated within a note length), the tempo standard setting device 75 is set as the standard setting button 76 to set the quarter note as the standard.
will output digital data corresponding to the numerical value "16", and if the setting button 77 for setting the eighth note as a reference is operated, digital data corresponding to the numerical value "8" will be output at the same time.

78 compares the numerical values represented by the digital data supplied to the two inputs A and B, and if the numerical value represented by the A input is larger than the numerical value represented by the B input (A>B), " 1”, and on the other hand, if the numerical value represented by the A input and the numerical value represented by the B input are equal (A=B)
This is a digital comparison circuit configured to output "1" as an output.

Reference numeral 79 denotes a variable frequency dividing circuit configured such that the frequency dividing ratio is switched between two levels according to the digital data outputted from the tempo standard setting device 75, and the tempo standard setting device If the frequency division ratio when the setting button 76 based on musical notes is operated is N, then the frequency division ratio when the setting button 77 based on eighth notes on the same tempo setter 75 is operated is It is configured to be 1/2N.

In the above configuration, when the initial clear circuit (not shown) is activated when the power is turned on and an initial clear pulse IC is generated, this pulse IC passes through the OR gate 14 to the RSFF15 as described above.
The pulse IC is supplied to the R input of the IC, and its output "1" resets the address counter 16 and prohibits it from advancing.The data memory 11 also becomes inactive, and the pulse IC is supplied to the OR gate 18.
is supplied to the R input of RSFF19 via
In addition to inhibiting the AND gate 20 by the output "0", the pulse IC also uses the clear inputs of the first latch circuit 80 and the second latch circuit 81 shown in FIG.
It is also supplied to the CLR to clear these memory contents. On the other hand, when the power is turned on and the manual selector switch 82 is closed, the tempo clock oscillator 73 shown in FIG. 2 outputs a tempo clock TCL having a frequency determined by the setting data from the tempo setter (manual) 74. This tempo clock TCL is input to the tempo detection counter 86 via an AND gate 83, an OR gate 84, and an AND gate 85.
Supplied to CK. Next, when the count value of the tempo detection counter 86 matches the numerical data output from the tempo standard setter 75, the (A=B) output of the digital comparison circuit 78 becomes "1", and this output "1" is OR It is supplied to the reset input R of RSFF88 through gate 87, and its output is “1”.
is set to On the other hand, since the tempo setting pulse ON has not yet arrived at this time, the output of the inverter 89 is always "1", and on the other hand, the output of the digital comparison circuit 7
Since the (A=B) output of 8 and the output of RSFF88 become "1" almost simultaneously, the input condition of AND gate 90 is satisfied at this point, and the output "1" is supplied to the set input S of RSFF91. After the Q output "1" is inverted by the inverter 92, the AND gate 85 is inhibited.

As a result, the tempo clock TCL that had been output from the tempo clock generation control circuit 65
is stopped, and the preparation for automatic performance is thus completed.

By the way, as described above, the automatic performance machine according to the present invention can set the automatic performance tempo to an arbitrary value by operating the tempo setting pulse generator 28, and can also stop the automatic performance by stopping the operation of the pulse generator 28. Although it is possible to stop the song in the middle of any song, especially in the case of this embodiment device, the above operation is performed in two modes: "fixed correction mode" and "continuous correction mode". be able to.

Therefore, the operation in the "fixed correction mode" will be explained first. With the selector manual changeover switch 82 closed, the start switch 2 shown in FIG.
1, a start pulse SS is generated from the differentiating circuit 22, and this pulse SS is supplied to the set input S of the RSFF 19, and its Q output "1" releases the inhibition of the AND gate 20. The same pulse SS is passed through OR gate 23 to RSFF
It is also supplied to the reset input R of 24, and its Q output "0" inhibits the AND gate 25, and the same pulse SS is also supplied to the RSFF15 through the OR gate 14.
is also supplied to the set input S of
enables address counter 16 and data memory. On the other hand, the same pulse SS is supplied to the set input S of the RSFF 27 via the OR gate 26, and the rhythm counter 9 is prohibited from incrementing by its Q output "1". It is also supplied to the reset input R of , and resets it.

Next, when a tempo setting pulse ON is generated in synchronization with the operation timing of the tempo setting pulse generator 28, this tempo setting pulse ON is supplied to the set input S of the RSFF 24 via the AND gate 20 and the OR gate 29, and its Q output AND with “1”
The gate 25 is disabled, and the address counter 16 starts incrementing in response to the clock φ. Also, the same pulse ON is the reset input R of RSFF27.
is also supplied to the rhythm counter 9, and its Q output “1” enables the rhythm counter 9.
ON is the Q output of DFF93 “1” as shown in Figure 2.
It is also supplied to the reset input R of the RSFF91 via the AND gate 94 and the OR gate 95, which are in the inhibited state, and is connected to the output path of the tempo clock TCL by its Q output "0".
At the same time as canceling the inhibition of the AND gate 85, the above Q output "0" is delayed by 1 clock φ and is output to the DFF93.
AND by its Q output “0”
Gate 94 is prohibited.

On the other hand, as shown in Figure 1, the Q output of RSFF19 is set to "1" by the start pulse SS.
When the AND gate 20 is disabled, a performance start pulse PLAY is output to the output side of the AND gate 20 in synchronization with the first tempo setting pulse ON, and this pulse PLAY is 2
As shown in the figure, it is connected to the reset input R of the tempo detection counter 86 via the OR gate 96, and to the reset input R of the RSFF 88 via the OR gate 87.
It is supplied to the reset input R of the RSFF 91 via the OR gate 95, to the reset input R of the tempo counter 70 via the OR gate 97, and to the reset input R of the RSFF 98, thereby resetting each of these circuits.

As a result of the AND gate 85 being disabled, the tempo clock TCL generated from the tempo clock oscillator 73 becomes the AND gate 8.
3. The clock is output from the tempo clock generation control circuit 65 via the OR gate 84 and the AND gate 85, and is input to the note length counter 37 as shown in FIG.
CK, and thereafter, each time the count value of the note length counter 37 matches the value indicated by the note length code latched in the latch circuit 36, the second, third, . . . As described above, the data groups are read out one after another. On the other hand, the tempo clock TCL is the clock input of the tempo detection counter 86 as shown in FIG.
CK is also supplied, and each time the count value of the counter 86 matches the setting data of the tempo standard setter 75, "1" appears at the (A=B) output of the digital comparison circuit 78, and this "1" ”The output is DFF
99 and is delayed by one clock φ.
Tempo detection counter 8 via OR gate 96
6 is supplied to the reset input R of 6. Therefore, the tempo setting counter 86 is controlled by the tempo standard setting device 75.
The number of tempo clocks indicated by the setting data of
It will be reset repeatedly every time the TCL is counted. Here, as mentioned above, the numerical data output from the tempo standard setter 75 is 1/1 of the standard tempo when automatic performance is performed at the standard tempo.
Tempo clock that occurs within a time corresponding to a beat
The tempo detection counter 86 indicates the number of TCLs, and the tempo detection counter 86 is the performance start pulse output in synchronization with the first tempo setting pulse ON.
Since counting is started by PLAY, assume that the frequency of the tempo clock TCL generated from the tempo clock oscillator 73 is 32 cycles/second corresponding to the standard tempo (for example, = 240), and that When the setting button 77 is operated on the setter 75 to count one beat based on the eighth note and numerical data "8" is output, the tempo setting pulse generator 28 sets the eighth note as the tempo reference. Assuming that the operation is performed at the standard tempo timing, the timing at which the tempo setting pulse ON arrives and the digital comparison circuit 78 (A=B) as shown in the timing chart of FIG.
This completely coincides with the timing at which a "1" pulse (hereinafter referred to as tempo detection pulse TP) is obtained at the output. Therefore, in this state
Both the logic conditions in the AND gate 100 and the AND gate 90 are not satisfied, and each Q output of RSFF88 and RSFF91 is held at "0", and the tempo clock TCL generated from the tempo clock oscillator 73 is The melody, accompaniment, and rhythm sounds are supplied from the electronic organ to the rhythm counter 9 and note length counter 37 shown in FIG.
240) is automatically played.

On the other hand, the tempo clock TCL generated from the tempo clock oscillator 73 in the same way as above.
is 32 cycles/second corresponding to the standard tempo (for example, = 240), and the setting button 77 is operated in the tempo standard setter 75 to count one beat based on the eighth note, and the numerical data is If "8" is being output and the tempo setting pulse generator 28 is operated at a timing faster than the standard tempo with the eighth note as the tempo standard, the tempo setting pulse generator 28 will generate a tempo setting pulse as shown in FIG.
The timing at which ON arrives is t ₁ more than the timing at which tempo detection pulse TP arrives at standard tempo.
This causes the tempo setting pulse to advance by a second.
At the same time as ON arrives, the logic condition in the AND gate 100 is established and the Q output of the RSFF 88 is set to "1", which is inverted by the inverter 101 and inhibits the AND gate 83.
Conversely, the AND gate 102 is released from the inhibition by the same Q output "1". For this reason, the tempo clock TCL generated from the tempo clock oscillator 73 is prohibited from being output by the AND gate 83, and instead, a very high-speed clock _φH output from a high-speed clock oscillator (not shown) is output.
are AND gate 102, OR gate 84 and AND
The signal is supplied to the note length counter 37 and the tempo detection counter 86 through the gate 85, and both counters are simultaneously fast-forwarded at high speed. Therefore, the (A=B) output of the digital comparator circuit 78 is delayed by a minute time Δt from the arrival point of the tempo setting pulse ON.
That is, the tempo detection pulse TP is output almost simultaneously, and this pulse TP is outputted via the OR gate 87.
It is supplied to the reset input R of the RSFF 88, and its Q output "0" inhibits the AND gate 102 again, and conversely, the AND gate 83 is disabled, and the output of the high-speed clock _φH is disabled. , and instead use the tempo clock TCL again.
will now be output.

As a result, the count value of the note length counter 37 is as follows until the tempo setting pulse ON arrives.
In response to the tempo clock TCL, it advances at a speed corresponding to the standard tempo, but the tempo setting pulse is ON.
As soon as the tempo detection counter 86 arrives, the tempo detection counter 86 is fast-forwarded by the remaining number to be counted. Therefore, even if the note length code latched in the latch circuit 36 at that time represents the length of an eighth note based on the standard frequency tempo clock TCL, the data memory 11
The time until the next data group is read out is shorter than the length of an eighth note based on the standard tempo clock TCL, and is almost the same as the period of the tempo setting pulse ON. The faster the operation timing, the faster the automatic performance tempo will be.
Moreover, the tempo is determined in synchronization with the operation timing of the tempo setting pulse generator 28 and according to the setting contents (ⓓ or ♪) of the tempo reference setting device 75. In other words, taking the tempo pulse generator shown in FIG. 4 as an example, after setting the tempo standard setter 75 to an eighth note, the shock plate 49 is set at a tempo of 260 times per minute, which is faster than the standard tempo = 240. If you hit it, 〓=
Automatic performance is performed at a tempo of 260.

On the other hand, in the same manner as above, the frequency of the tempo clock TCL generated from the tempo clock oscillator 73 is 32 cycles/second corresponding to the standard tempo (for example, = 240), and the frequency of the tempo clock TCL generated by the tempo clock oscillator 73 is 32 cycles/second, and the tempo reference setting device 75 also has a frequency of 8 cycles/second. When the setting button 77 is operated to count one beat based on a musical note and numerical data "8" is output, the tempo setting pulse generator 28 is operated at a timing slower than the standard tempo using an eighth note as a tempo reference. If so, the tempo setting pulse is turned on as shown in Figure 9.
The arrival timing of the tempo detection pulse TP is delayed by t ₂ seconds from the arrival timing of the tempo detection pulse TP, and as a result, the logic condition in the AND gate 90 is established at the same time as the tempo detection pulse TP arrives, and the Q output of the RSFF 91 becomes "1". ” is set to
This will be inverted by inverter 92 to inhibit AND gate 85. Therefore, no pulses to be counted are supplied to the note length counter 37 and the tempo detection counter 86, and the incrementing of these counters is stopped. Next, when the tempo setting pulse ON arrives after time t ₂ seconds has elapsed, this pulse ON is supplied to the reset input R of the RSFF 91 via the AND gate 94 and the OR gate 95.
The inhibition of the AND gate 85 is canceled by the Q output "0", and the above operation is performed by the tempo detection pulse.
This is repeated each time a TP arrives.

As a result, the count value of the note length counter 37 is as follows until the tempo detection pulse ON arrives.
It receives the tempo clock TCL and steps at a speed corresponding to the standard tempo, but the tempo detection pulse is ON.
As soon as , the progress is stopped. Therefore, the note length code latched in the latch circuit 36 at that time is transferred to the standard frequency tempo clock.
Even if the length of an eighth note is expressed based on the TCL, the time it takes to read the next data group from the data memory 11 is longer than the length of an eighth note based on the standard tempo clock TCL. It is extended to be the same as the period of the tempo setting pulse ON, that is, the tempo setting pulse generator 28
If the operation timing of the tempo standard setter 75 is delayed, the automatic performance tempo will also be lowered accordingly, and the tempo will be synchronized with the operation timing of the tempo setting pulse generator 28 and the setting contents of the tempo standard setter 75 ( ♪). In other words, taking the tempo pulse generator shown in FIG. 4 as an example again, after setting the tempo reference setter 75 to an eighth note, the shock plate 49 is set to a tempo of 200 times per minute, which is slower than the standard tempo = 240. If you hit it, it will automatically play at a tempo of =200.

Furthermore, as described above, if the timing at which the tempo detection pulse TP arrives is earlier than the timing at which the tempo setting pulse ON arrives, the AND gate 85 is inhibited at the same time as the arrival of the tempo detection pulse TP, and the tempo clock TCL is generated. Therefore, according to this embodiment, if the operation of the tempo setting pulse generator 28 is stopped and the tempo setting pulse ON is not generated, the tempo setting pulse generator 28 can be automatically turned on at any point in the song as shown in FIG. You can stop the performance, and the tempo setting pulse generator 2
If you restart the operation in step 8, you can restart the automatic performance from the stopped point in the song as shown in FIG. You can also return to the beginning and resume automatic performance.

Thus, when the manual selector switch 82 is closed to set the "fixed correction mode" and the tempo setting pulse generator 28 is operated at an arbitrary timing, the timing will be changed depending on whether the timing is later or earlier than the standard timing. Then, the tempo clock generation control circuit 65 generates the tempo clock TCL or the high-speed clock _φH , or no clock is generated at all, which causes the tempo setting pulse
By the end of one cycle of ON, the number of increments in the note length counter 37 is corrected so that it is always constant regardless of the frequency of the tempo clock TCL output from the oscillator 73, and on the other hand, each note in the data memory 11 is Since data compressed using the pitch data and note length data is stored as one group,
If the stepwise operation of the note length counter 37 is corrected in accordance with the operation of the tempo setting pulse generator 28, the tempo of the automatically played music output from the sound system 7 can be adjusted to the tempo setting pulse generator 28.
Moreover, the performance tempo immediately responds to the operation of the tempo setting pulse generator 28 without a delay of one tempo.

Next, the operation in the "continuous correction mode" in which the manual selector switch is opened will be explained.

To briefly explain the characteristics and merits of operation in the "continuous correction mode", as mentioned above, in the case of the "fixed correction mode", the clock output from the tempo clock generation control circuit 65 is the tempo clock.
Even if the number of clocks generated in each period of the tempo setting pulse ON is uniform for TCL or high-speed clock _φH , the frequency changes extremely irregularly when looking at an arbitrary minute period. It is something to do. However, as long as each performance data is compressed and stored in the data memory 11,
This is not much of a problem, but it becomes a slight problem in cases where the performance data is not compressed and each address corresponds to a certain length of time, such as in the rhythm pattern memory 8 mentioned above. In fact, it creates a very irregular rhythm. On the other hand, in the "continuous correction mode" operation, in addition to making the number of clocks generated within each period of the tempo setting pulse ON equal, the frequency can also be made uniform when looking at any minute period. The above-mentioned rhythm pattern memory 8
Even in an automatic performance machine in which performance data is stored without being compressed, it is possible to perform at a regular tempo, and this will be explained in detail below.

First, with the selector manual changeover switch 82 open, press the start switch 21 to complete automatic performance preparation, and then when the tempo setting pulse ON is generated in synchronization with the operation timing of the tempo setting pulse generator 28, this tempo setting Pulse ON is performed by AND gate 20 and OR gate as shown in Figure 1.
It is supplied to the set input of the RSFF 24 through the gate 29, and its Q output "1" disables the AND gate 25, and the address counter 16 starts incrementing. As already explained, each performance data group is read out sequentially.

On the other hand, the tempo counter 70 shown in FIG.
Upon receiving PLAY, the variable frequency divider circuit 79 starts counting the clock φ' as shown in the timing chart of FIG. AND gate 103 changes from “0” to “1”
ban will be lifted. Then, with the arrival of the next tempo setting pulse ON, the count value of the tempo counter 70 is latched in the first latch circuit 80, and in response to the same pulse ON, the tempo counter 70 is reset again, and the EN of the discrimination circuit 69 is reset. The output also changes from “1” to “0” and the AND gate 10
3 becomes prohibited again. Next, when the count value of the tempo counter 70 falls within the tolerance range set by the tolerance range setter 66, the discrimination circuit 6
9's EN output changes from "0" to "1" again,
The inhibition of the AND gate 103 is released again, and when the third setting pulse ON arrives in this state, it is transferred to the first latch circuit 81, and
The new count value of the tempo counter 70 is latched in the first latch circuit 80, and at the same time, the new count value of the tempo counter 70 is latched.
When the EN output becomes "0", the AND gate 103 is inhibited again. In this way, three setting pulses are turned on from the tempo setting pulse generator 28.
has arrived and both of these inter-pulse periods T ₁ and T ₂ are within the tolerance range specified by the tolerance range setter 66, the first and second latch circuits 80 and 81 respectively Each pulse-to-pulse period T ₁ ,
Period data representing T ₂ with reference to the period of clock φ' will be latched, and the setting pulse ON will be passed through AND gates 103 and 104 so that it will overflow when the count value exceeds "2". Since it is also supplied to the clock input CK of the configured initial tempo setting counter 105, its overflow output C ₀ “1” sets RSFF98, and the same output C ₀
“1” is inverted via inverter 106
It is fed back to the AND gate 83, and input of the setting pulse ON to the initial tempo setting counter 105 is prohibited thereafter. Then, when RSFF98 is set, its output “0” is output from OR gates 107 and 10.
8, it is inverted to "1" by the inverter 109, and is supplied to the switching input SB of the selector 72.
As a result, the frequency setting data supplied to the tempo clock oscillator 73 is switched from the manual setting data from the tempo setter 74 to the output data of the averaging circuit 71. That is, when the tempo pulse generator 28 is operated with the manual selector switch 82 open, the averaging circuit 7
Until all the two pieces of data necessary for the averaging operation in step 1 are ready, the tempo clock oscillator 73 automatically outputs the tempo clock TCL having the frequency specified by the tempo setter (manual) 74, and the other two At the same time when the data is completely latched in the first and second latch circuits 80 and 81, the tempo clock oscillator automatically generates a tempo clock TCL having a frequency specified by the operation timing of the tempo setting pulse generator 28. become.

Thereafter, the tempo clock oscillator 73 outputs the first,
A tempo clock TCL having a frequency specified by the average value of the cycle data latched in the second latch circuits 80 and 81 is generated, and the tempo setting pulse generator 28 is operated at a fast timing to turn on the tempo setting pulse. When the period is shortened, the frequency of the tempo clock TCL increases accordingly,
On the other hand, if the tempo setting pulse generator 28 is operated at a slower timing to lengthen the cycle of the tempo setting pulse ON, the frequency of the tempo clock TCL will correspondingly decrease.

Also, at this time, as in the case of the _fifth setting pulse ON shown in FIG. , at the time of arrival of the fifth tempo setting pulse ON, it is still
Since the AND gate 103 is in a prohibited state, even if the fifth tempo setting pulse ON arrives, the count value of the tempo counter 70 remains unchanged from the first latch circuit 8.
Therefore, the contents of each memory of the first and second latch circuits 80 and 81 are stored at the time when the fourth setting pulse ON arrives even after the arrival of the fifth setting pulse ON. The data in each latch circuit 80, 81 is updated for the first time only after waiting for the arrival of the sixth setting pulse ON, which is a normal pulse within the allowable range as shown in FIG. Therefore, according to this embodiment, for example, if an attempt is made to operate the tempo setting pulse generator 28 at a fixed timing, the timing is accidentally disturbed, and as a result, the tempo setting pulse generator 28
If the interval between set pulses output from ON becomes shorter than the allowable range, the cycle data representing these pulse intervals is excluded as data for averaging calculation in the averaging circuit 71. As a result, the tempo clock TCL output from the tempo clock oscillator 73
The frequency will be maintained stably regardless of the disturbance in the frequency of the tempo setting pulse ON.

Further, after the selector 72 switches to the averaging circuit 71 side, the first and second latch circuits 80 and 81
If the memory contents of any of the NOR gates 110 and 11 are lost due to an unexpected malfunction,
1 becomes "1", and this "1" signal is supplied to the switching input SA of the selector 72 via the OR gates 112 and 118,
As a result, the frequency setting data supplied to the tempo clock oscillator 73 is switched again from the output data of the averaging circuit 71 to the setting data of the tempo setter (manual) 74. Therefore, according to this embodiment, the memory contents of either of the two latch circuits 80, 81 are lost due to the above-mentioned unforeseen circumstances, which causes the calculation result of the averaging circuit 71 to fluctuate greatly. If the tempo clock
TCL frequency is tempo setter (manual) 7
The tempo clock is only returned to the value corresponding to the setting value of 4, and the tempo clock is returned to the value corresponding to the setting value of 4.
Significant fluctuations in the TCL frequency are reliably prevented.

On the other hand, in this way, each of the first and second latch circuits 8
Even while the cycle data of the tempo setting pulse ON, which is latched at 0 and 81, is averaged by the averaging circuit 71 and the frequency of the tempo clock TCL output from the tempo clock oscillator 73 is being variably controlled by the output of the averaging circuit 71, The AND gate 90,1
In 00, as explained in the case of "fixed correction mode", the arrival timing of the tempo setting pulse ON and the arrival timing of the tempo detection pulse TP are constantly compared, and as mentioned above, the tempo setting pulse ON is If it arrives before the tempo detection pulse TP, the Q output of RSFF88 is “1”.
As a result, the AND gate 102 is disabled, the AND gate 83 is disabled, and the tempo clock generation control circuit 65 outputs the high-speed clock _φH , while the tempo detection pulse TP is turned on before the tempo setting pulse is turned on. If it arrives
The AND gate 85 is inhibited by the Q output "1" of the RSFF 91, and no clock is output from the tempo clock generation control circuit 65.

Therefore, according to this embodiment, after the preparation for automatic performance is completed, the tempo setter (manual) 74 is set to the standard tempo (for example, = 240), and the tempo standard setter 75 is set to "eighth note". death,
Next, if the tempo setting pulse generator 28 is operated at an arbitrary timing, if the operation timing happens to be the same as the standard tempo, the tempo clock generation control circuit 65 will output the standard tempo ( = 240) with a frequency (32 cycles/sec) corresponding to the tempo clock TCL
is output, and automatic performance at the standard tempo is performed. On the other hand, if the tempo setting pulse generator 28 is operated at a timing corresponding to the standard tempo and then the operating timing is suddenly increased, the tempo setting pulse generator 28 will be activated as shown in FIG. 12. At the same time, the tempo clock generation control circuit 65 outputs a high-speed clock _φH .
The difference between the counted value of the tempo detection counter 86 at that time and the numerical data output from the tempo standard setter 75 (hereinafter, this is calculated as the difference between the count value of the tempo detection counter 86
is called the remaining number. ) are output,
Then, with the arrival of the tempo detection pulse TP, the clock output from the control circuit 65 is switched to the tempo clock TCL having a frequency determined by the output data of the averaging circuit 71 at that time, and the above operation is repeated.

On the other hand, as the operating timing of the tempo setting pulse generator 28 is made faster, the cycles of the tempo setting pulse ON become shorter, and the first and second latch circuits 80 and 81 respond to these short cycles. The corresponding numerical data are latched one after another, and as a result, the tempo setting pulse generator 28 instructs the tempo change, and then the third tempo setting pulse is generated.
When ON arrives, the frequency of the tempo clock TCL output from the tempo clock oscillator 73 in response to the calculation result of the averaging circuit 71 becomes a value corresponding to the fast tempo specified by the tempo setting pulse generator 28, and the tempo is set again. The timing of pulse ON and tempo detection pulse TP perfectly matches,
The content of the clock output from the tempo clock generation control circuit 65 is a tempo clock with a regular frequency output from the tempo clock oscillator 73.
Only TCL will be available.

In addition, if the operation timing of the tempo setting pulse generator 28 is suddenly delayed from a state where the tempo setting pulse generator 28 is operated at a timing corresponding to the standard tempo, the tempo setting pulse generator 28
As shown in the figure, no clock is output from the tempo clock generation control circuit 65 only from the time when the tempo detection pulse TP arrives until the time when the tempo setting pulse ON arrives. On the other hand, as the operation timing of the tempo setting pulse generator 28 is delayed and the cycle of the tempo setting pulse ON becomes longer, the first and second latch circuits 8
Numerical data corresponding to these long cycles are sequentially latched at 0 and 81, and as a result, when the third tempo setting pulse ON arrives after the tempo setting pulse generator 28 instructs to change the tempo,
Tempo clock output from tempo clock oscillator 73 in response to the calculation result of averaging circuit 71
The TCL frequency is determined by the tempo setting pulse generator 28
The value corresponds to the slow tempo specified by , and the tempo setting pulse turns ON and the tempo detection pulse TP again.
The timings match perfectly, and the content of the clock output from the tempo clock generation control circuit 65 is only the regular frequency tempo clock TCL output from the tempo clock oscillator 73.

In this way, when the tempo setting pulse generator 28 is operated in the "continuous correction mode", the number by which the note length counter 37 increments is output from the oscillator 73 by the end of one cycle of the tempo setting pulse ON. The fact that the tempo clock TCL is always maintained constant regardless of its frequency is the same as in the "fixed correction mode" described above, but the tempo clock TCL is supplied from the tempo clock generation control circuit 65 to the note length counter 37 and the rhythm counter 9. Focusing on the contents of the clock, the frequency of the clock becomes irregular only for a very short period from the time when the tempo setting pulse generator 28 instructs the tempo to change; after this period, the tempo changes. The clock frequency remains stable unless a new command is given to change it.

Therefore, according to the clock output from the clock generation control circuit 65 in the "continuous correction mode",
Not only automatic performance machines that use a memory that stores performance data after compression, such as the data memory 11, but also automatic performance machines that use a memory that stores performance data that is not compressed, such as the rhythm pattern memory 8. Even in this case, normal automatic performance with regular rhythm and melody can be performed.

In addition, in "continuous correction mode", for example
By using the Q output "1" of the RSFF88 to prohibit the generation of automatic performance sounds only during that period, it is possible to prevent strange noises that occur when changing the tempo. Furthermore, in this embodiment, an averaging operation is employed as an operation for determining the control data of the tempo clock oscillator 73 based on the periodic data latched in the first and second latch circuits 80 and 81. First and second latch circuits 8
Of course, the calculation may be performed by weighting either the periodic data latched at 0 or 81.

Furthermore, in the above embodiments, only three examples were shown as tempo setting pulse generators in FIGS. 4 to 6B, but for example, in the example in FIG. If it is made of a board, the tempo can be indicated with a light touch of the finger, and of course various other configurations can also be adopted. Any device may be used as long as it generates pulses in response to the timing movement of some object that serves as a reference for the tempo during performance. Furthermore, in the above embodiments,
Although the present invention has been described as being applied to an electronic organ with an automatic performance function, the application of the present invention is of course not limited to this, and can be applied to various automatic performance machines that have been previously proposed by the applicant. , for example, it can be widely used in auto bass chord devices, auto arpeggio devices, auto rhythm devices, etc.

As is clear from the above embodiments, according to the present invention, the tempo setting operation in this type of automatic musical instrument, which was conventionally performed by operating a slide type or rotary resistor, etc., can be performed by a person. The tempo can be set to any desired tempo by the action of taking the time signature, and when playing on this type of automatic musical instrument, you can add excitement to the song as you wish, or when using the automatic musical instrument as a teaching device, it can be used to help students. The functionality of this type of automatic musical instrument as a musical instrument can be greatly enriched, such as by being able to change the tempo of a piece of music depending on the level of proficiency, and by having the player play only difficult parts at a leisurely pace. Furthermore, in this invention, a plurality of tempo control data sequentially obtained in response to the operation of an external controller are averaged, and the frequency of the tempo clock is controlled based on this averaged data. Even if the operation timing of a child varies slightly, the performance tempo of an automatic musical instrument does not temporarily change significantly, and the performance tempo can be controlled in a stable state. Furthermore, according to the present invention, since the external controller and the automatic musical instrument are connected via wireless transmission means, problems such as wiring do not occur and the operability is very good. It has excellent effects.

[Brief explanation of drawings]

Fig. 1 is an overall block circuit diagram showing the case where the present invention is applied to an electronic organ with an automatic performance function as an example of an automatic performance machine, and Fig. 2 shows a tempo clock generation control circuit which is the main part of the present invention. FIG. 3 is a block circuit diagram showing the data format in the data memory, FIGS. 4, 5, and 6 are structural diagrams showing an example of the tempo setting pulse generating means, and FIGS. FIG. 13 is a timing chart showing the temporal relationship of each signal in the tempo clock generation control circuit. 28... Tempo setting pulse generating means, 73... Tempo clock generating means, 75, 78, 86... Tempo detecting means, 90, 100... Timing comparing means,
85, 102... Count value correction means.

Claims (1)

[Scope of Claims] 1. External operator means having a pulse generating means that generates pulses in synchronization with operation timing; and an external operator means that is provided on the automatic performance machine body and that generates pulses that are output one after another from the pulse generating means. a measuring means for measuring a time interval and outputting tempo control data corresponding to the measured time interval; and a measuring means provided in the automatic performance machine main body, storing a plurality of the tempo control data sequentially output from the measuring means. a storage means; an averaging means provided on the automatic performance machine body for averaging the values of a plurality of tempo control data stored in the storage means; and an averaging means provided on the automatic performance machine body for averaging the values of the plurality of tempo control data stored in the storage means; tempo clock generating means for generating a tempo clock for controlling the tempo, the frequency of the generated tempo clock being controlled in accordance with the output of the averaging means, and the tempo setting pulse generating means is wirelessly controlled. A tempo control device for an automatic performance machine, characterized in that it is connected to the automatic performance machine main body via a transmission means.