JP2500603B2 - Color signal base clip circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal base clip circuit, and more particularly to a color signal base clip circuit for a video camera.

[0002]

2. Description of the Related Art A base clip circuit is used to cut noise existing near a low level of a signal. In general, the base clip processing for color signals is such that base clip processing is performed independently for each color difference signal. An example of this type of base clip circuit is disclosed in Japanese Patent Laid-Open No. 55-10286, and FIG. 6 shows a circuit diagram of the conventional base clip circuit.

In the figure, this base clip circuit is
Input terminals 62, 63, power supply 64, output terminals 65, 66,
Transistors 67, 68, diodes 69, 70, 7
1, 72, resistors 73, 74, 75, 76, constant current source 7
7,78. The input terminal 62 is connected to the base of the transistor 67, the collector of the transistor 67 is connected to one terminal of the resistor 74, the output terminal 66 and the anode of the diode 71, and the emitter of the transistor 67 is the emitter of the transistor 68 and the constant current source. 78 is connected to one terminal. The cathode of the diode 71 is connected to the cathode of the diode 72 and one terminal of the constant current source 77, and the cathode of the diode 72 is connected to the collector of the transistor 68, one terminal of the resistor 76 and the output terminal 65.

The input terminal 63 is connected to the base of the transistor 68, and the other terminal of the resistor 74 is one terminal of the resistor 73, the anode of the diode 69 and the diode 70.
Connected to the cathode of. The other terminal of the resistor 76 is connected to the cathode of the diode 69, the anode of the diode 70, and one terminal of the resistor 75.
The other terminal of the constant current source 7 is connected to the input terminal 64.
The other terminals of 7, 78 are configured to be grounded.

In FIG. 6, the resistance values of the resistors 74 and 76 are R1, the resistance values of the resistors 73 and 75 are R2, the collector currents i1 and i2 of the transistors 67 and 68, and the constant current source 7 are shown.
The currents of 8,77 are I1, I2, and the input signal voltage Vi =
Let αI1 (where | α | ≤1 / 2).

First, consider the case where the input signal Vi is small. In case of | Vi | <I2 / 2, the diodes 71, 72
Is turned on, the output voltage V0 becomes V0 = 0 ... (1).

When Vi ≧ I2 / 2, the diode 71 is turned off and the diode 72 is turned on, so that i1, i2
Becomes i1 = I1 / 2 + αI1 i2 = I1 / 2 + I2−αI1. Therefore, the output voltage V0 is V0 = (i1−i2) (R1 + R2) = 2αI1 (R1 + R2) −I2 (R1 + R2). 2)

Further, when αI1≤-I2 / 2, the diode 71 is turned on and the diode 72 is turned off, so that i1, i2
Since i1 = I2 / 2 + αI1 + I2 i2 = I1 / 2-αI1, the output voltage V0 is V0 = 2αI1 (R1 + R2) + I2 (R1 + R2) ... (3).

Next, consider the case where the input signal Vi is large. In this case, in order to simplify the description, first consider a case where the constant current source 77 does not work.

When the voltage when the diodes 70 and 69 are on is VD, when I2 / 2≤Vi≤VD1 / 2R2,
Since i1 and i2 are i1 = I1 / 2 + .alpha.I1 i2 = I1 / 2-.alpha.I1, the output voltage V0 is V0 = (R1 + R2) (i1-i2) = 2.alpha.I1 (R1 + R2) ... (4) Become.

When Vi> VD1 / 2R2, the diode 70 is turned on and the diode 69 is turned off, and the output voltage V0 is V0 = R1 (i1-i2) + VD = 2.alpha.I1R1 + VD ... (5) Become.

Here, when the action of the constant current source 77 is added,
Expressions (4) and (5) can be rewritten as in the case of expression (2). That is, V0 = 2.alpha.I1 (R1 + R2) -I2 (R1 + R2) ... (4) 'V0 = 2.alpha.I1 R1 + VD-I2 (R1 + R2) ... (5)'.

Similarly, -I2 / 2≥Vi ≥-
When VD1 / 2R2, the diodes 70 and 69 are both off, so V0 = 2αI1 (R1 + R2) -I2 (R1 + R2) ... (6), and when Vi <-VD1 / 2R2, the diode is 70
Is off and the date 69 is on, the output voltage V
0 becomes V0 = 2αI1 R1 -VD + I2 (R1 + R2) (7).

Then, VD = I2 (R1 + R2)
If equation (5) 'and equation (7) are satisfied, V0 = 2αI1 R1 (8)

Summarizing the above, | V1 | <I2 /
When 2, V0 = 0 ... (9) I2 / 2.ltoreq.Vi.ltoreq.VD1 / 2R2, -I2 / 2.gtoreq.Vi.gtoreq.-.
When VD1 / 2R2, V0 = 2αI1 (R1 + R2) -I2 (R1 + R2) = 2 (R1 + R2) Vi-I2 (R1 + R2) ... (10) Vi> VD1 / 2R2, Vi <-VD1 When / 2R2, V0 = 2αI1 R1 = 2R1 Vi (11). When the expressions (9), (10), and (11) are represented in the figure, the input / output characteristics shown in FIG. 7 are obtained. FIG. 8 shows the relationship between the output signal color phase angles when the input signal voltages are VR-Y and VB-Y in the conventional example shown in FIG.

[0016]

When performing the base clip processing of the coloring signal using the above base clip circuit, individual base clip circuits are provided for the two color difference signals RY and BY. Since the two color difference signals are independently subjected to base clipping for gain adjustment, there is a case in which gain adjustment processing is performed on only one of the color difference signals. In this case, there is a drawback that the original color phase angle of the signal is changed and a phase shift occurs.

When the base clip circuit shown in FIG. 6 is independently applied to the color difference signals RY and BY, the original color phase angle of the input color difference signal is obtained.

For tan ⁻¹ {(2.03 / 1.14) (VR-Y / VB-Y)}, the difference in the color phase angle of the output signal of the base clip circuit as shown in FIG. Is a phase shift.

Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and its purpose is to independently base color difference signals RY and BY. It is an object of the present invention to provide a color signal base clip circuit in which both signals are processed in the same manner, instead of being clipped, to eliminate a phase shift from the original color phase angle.

[0020]

A color signal base clip circuit according to the present invention includes a color saturation degree generating means for generating color saturation degree information according to a color saturation degree of first and second color difference signals, and this color saturation. The subtraction means for subtracting the degree information and the predetermined constant, the zero clamp means for zero clamping and deriving the negative component of the subtraction output, the multiplication means for multiplying the clamp output by a predetermined multiplier, and the predetermined multiplication output. A constant clamp means for clamping and deriving a component equal to or more than a constant to the predetermined constant, and first and second multiplying means for multiplying the clamp output by the first and second color difference signals, respectively, Etc. 1st
And a base clip signal is derived from the output of the second multiplication means.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the present invention, the two color difference signals are represented as 8-bit digital data and are represented as ER-Y and EB-Y. These 8-bit data are input to the 16-bit address of the ROM (Read Only Memory) 1. This ROM
It is assumed that the color saturation information corresponding to the color saturations of the two input color difference signals is stored in advance in 1.

Now, the higher 8 bit address is x, the lower 8
The bit address is y, and the entry contents of each ROM for these 16-bit addresses are values obtained by rounding off the decimal point of Ec = (x ² + y ² ) ^1/2 (12). And

For example, when ER-Y = EB-y = 100, (100 ² +100 ² ) ^1/2 = 14.412 ..., which is rounded off and the color saturation information Ec = which is the output of the ROM 1 is output. 141 (see FIG. 3).

This 9-bit color saturation information Ec becomes an input to the coefficient conversion circuit 2 and undergoes coefficient conversion necessary for base clip processing (Ec1 → Ec2 → Ec3 → Ec4), and then becomes output information Ec5. Derived. The output information Ec5 and the input color difference signals ER-Y and EB-Y are multiplied by multipliers 3 and 4, respectively, and the outputs of these multiplications are gain adjusting circuits 5 and 6 respectively.
Final base clip output ER- derived via
Y'and EB-Y 'are obtained respectively.

In the coefficient conversion circuit 2, the input color saturation information Ec is input to the subtractor 21 and subtracted from the first constant T1. Now, referring to FIG. 2, there is a one-to-one correspondence between the color saturation levels of the two input color difference signals ER-Y and EB-Y and the color saturation level information Ec output from the ROM 1. 2 and the linear proportional relationship shown in FIG.

In this case, when the subtracter 21 performs a subtraction process with the constant T1, the color saturation of the subtraction output Ec1 is translated by T1 in the negative (down) direction of the vertical axis as shown in FIG. 2B. Converted to a straight line. For example, T1 = 30 and EC = 14
If 1, then Ec1 = 141-30 = 111 (see FIG. 3).

The subtraction output EC1 becomes 10 bits of the code 1 bit and the data 9 bits, and the 1-bit code becomes the 1-bit output EC2 via the inverter 22. Each bit of the 9-bit data is one input to the AND gates 23 to 25, and the 1-bit output EC2 is applied to the other inputs of the AND gates 23 to 25.

Now, assuming that the 1-bit code is "0" when EC1 is positive and "1" when it is negative, E
When C1 becomes negative data, EC2 becomes "0", so all the outputs EC3 of the AND gates 23 to 25 are forced to "0".
And if EC1 is positive data, AND gate 23
The data of EC1 is directly output to the output EC3 of .about.25.

Therefore, the inverter 22 and the AND gate 2
3 to 25 form a zero clamp circuit for negative data, and the color saturation of the output EC3 of the AND gates 23 to 25 is converted into a straight line of 0 or more as shown in FIG.

For example, if EC1 = 111, then EC3 = 11
1 and when EC1 = -16 (that is, negative), EC3 = 0
Is clamped to (see FIG. 3).

This signal EC3 is multiplied by the multiplier G in the multiplier 26 to form a multiplication output EC4. With this multiplication processing, the color saturation of the output EC4 has a straight line slope G as shown in FIG.
It will change according to.

For example, G = 15/16 and EC3 = 1
If 11, then E C4 = 111 × 15/16 = 104.0
625, and the number after the decimal point is rounded down to 104 (see FIG. 3).

This multiplication output EC4 is compared with the second constant T2 by the comparator 28, and the selector 27 is controlled by the comparison result. Now, when EC4 exceeds T2, the selector 27 selects T2 and outputs it as EC5.
In the following cases, the selector 27 outputs EC4 as it is, EC5
To choose as.

That is, when EC4≤T2, EC5 = EC4
When Ec4> T2, Ec5 = T2 and T2
E C5 beyond is clamped at T2. EC5 at that time
The degree of color saturation has the relationship shown in FIG.

For example, if T2 = 32 and EC4 = 104, then EC5 = 32, and if EC4 = 10, then EC5 = 10 (see FIG. 3).

This signal EC5 is multiplied by the input color difference signals ER-Y and EB-Y in the multipliers 3 and 4, respectively, and further level-converted in the gain adjusting circuits 5 and 6 so that the gain becomes 1/32. The output color difference signal ER-
Y ', EB-Y' are obtained.

The color saturation of these ER-Y 'and EB-Y' is shown in FIG.
As shown in (F), when the input color saturation is in the range of T1 to α, it is a squared curve because it is the product of the straight lines in FIG. 2 (F) and FIG. 2 (A). , The straight line shown in FIG.

For example, T1 = 30, G = 15/16, T
If 2 = 32 and ER-Y = EB-Y = 100, then ER-Y '=
ER-Y x EC5 / 32 = 3.125, EB-Y '= 12.5, and the fractions below the decimal point are truncated, respectively, and ER-Y' = 3, EB-
Y '= 12 (see FIG. 3).

Although not actually appearing as a signal, for reference, the color phase θ of the color difference signals ER-Y and EB-Y and ER-Y 'and EB-.
The color phase θ ′ of Y ′ is shown in FIG. 3, respectively. The phase angle is θ = tan ⁻¹ {(2.03 / 1.14) (ER-Y / EB-Y)} θ = tan ⁻¹ {(2.03 / 1.14) (ER-Y '/ EB-Y')}, and this formula is based on P.3 of "NHK Television Technology Textbook (above)". 44 is the formula specified.

When the relationship between the color phase angle θ of the input color difference signal and the color phase angle θ ′ of the output color difference signal is obtained, θ ′ = tan ⁻¹ {(2.03 / 1.14) (ER-Y ′ / EB-Y ')} = tan ^-1 {(2.03 / 1.14) (ER-Y * EC5 / 32) / (EB-Y * EC5 / 32)} = tan ^-1 {(2.03 / 1.14) (ER-Y / EB-Y) = θ, and the color phase angles between the input and output signals become equal (however, except for EC5 = 0).

Note that the circuit of FIG. 1 and its timing chart of FIG. 3 do not consider the circuit delay, so that it is necessary to insert a register in FIG. 1 in accordance with the clock frequency of the signal and the circuit operating speed. Therefore, the timing of the timing chart changes according to the register.

In this way, the base clip processing is not performed independently for each color difference signal, but the base clip processing is simultaneously performed using the color saturation information which is the vividness of the color represented by the color difference signal. That is, there will be no phase shift from the original color phase angle of the output color difference signal after the base clip processing.

In the above embodiment, the color saturation of the two color difference signals is calculated by the equation (12), but it is also possible to use the square of the color saturation approximately. FIG. 4 is a block diagram showing an example of this case, and the same portions as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 4, a square calculation circuit 7 is used instead of the ROM 1 (FIG. 1). That is, the multiplier 3
1, 32, the square value of each color difference signal is obtained, and the output thereof is converted into 1/32 by the gain adjusting circuits 33, 32, respectively, and these are approximated to the added color saturation by the adder 35. Seeking an EC.

That is, E C is given by E C = (E R-Y ² + E B-Y ² ) / 32, and if both E R-Y and E B-Y are -128, E C
= 1024 (rounded down after the decimal point). Also, ER-Y
= 40 and EB-Y = 10, EC = 53, and the rest is the same as the example of FIG.

FIG. 5 shows a timing chart of the circuit of FIG. 4 and specific numerical examples.

The numerical examples in each of the above embodiments are merely examples, and various modifications are possible as long as the values are suitable for the base clip.

[0049]

As described above, according to the present invention, the color saturation information is obtained from the input color difference signal, and the input color difference signal is simultaneously gain controlled by this control signal by using this color saturation information as a control signal. Even if the gain changes when the base clip starts to work, the hue angle does not change. That is, there is an effect that deviations of the output color difference signals with respect to the input color difference signal phase angle are eliminated except for the zero clamp state.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIGS. 2A to 2F are diagrams showing the relationship between the color saturation of an input signal and the color saturation of each signal of the block of FIG.

FIG. 3 is a diagram showing specific numerical examples of signals of respective parts of the circuit of FIG.

FIG. 4 is a block diagram of another embodiment of the present invention.

5 is a diagram showing specific numerical examples of signals of respective parts of the block of FIG.

FIG. 6 is a diagram showing an example of a conventional base clip circuit.

7 is an input / output characteristic diagram of the circuit of FIG.

8 is a diagram showing a color phase angle of an output signal of the circuit of FIG.

[Explanation of symbols]

 1 ROM 2 coefficient conversion circuit 3, 4, 26 multiplier 5, 6 gain adjustment circuit 21 subtractor 22 inverter 23-25 AND gate 27 selector 28 comparator

Claims (4)

(57) [Claims] 1. A color saturation generation means for generating color saturation information according to color saturation of the first and second color difference signals, and a subtraction means for subtracting the color saturation information from a predetermined constant. Zero-clamping means for deriving the negative component of the subtraction output by zero-clamping, multiplying means for multiplying the clamp output by a predetermined multiplier, and deriving a component of a predetermined constant or more of the multiplication output by the predetermined constant. Constant clamping means and first and second multiplying means for multiplying the clamp output and the first and second color difference signals, respectively, and outputs the bases from the outputs of the first and second multiplying means. A chrominance signal-based clip circuit, wherein a clip signal is derived. 2. The color saturation generation means is configured to generate color saturation information proportional to the square of the color saturation of the first and second color difference signals. Item 1. The color signal base clip circuit according to Item 1. 3. The color saturation generation means has a memory in which the color saturation information is stored in advance corresponding to each of the first and second color difference signals as an address. The color signal base clip circuit according to claim 1. 4. The color saturation generation means includes first and second multipliers that generate each squared signal of the first and second color difference signals, and first and second multipliers. 3. The color signal base clip circuit according to claim 2, further comprising: coefficient conversion means for converting the coefficient of the sum of the outputs of the above into a predetermined coefficient.