JP2904569B2 - Logical filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a logical filter used for, for example, an edge super generator in a studio device of a broadcasting station.

(Prior Art) In general, in an edge superimposing device, for example, when a character to be superimposed is white, it is difficult to see if the background image is close to white. And the mixing ratio of luminance and saturation between the super signal and the background image signal is controlled by the key signal. This control is generally realized by a logical filter as shown in FIG.

By way shows the block circuit diagram in FIG. 5, an input original signal (key signal) in N delay circuits 11 ₁ to 11 _N, for example, are sequentially one clock by one delay, the delay circuits 11 ₁ to 11 _N
Before and after the delay of the signal is multiplied by a predetermined coefficient in the multiplier 12 ₀ to 12 _N, the maximum value calculator, such as the comparator (MAX) 13 ₁ ~13 _N
, The maximum value is sequentially calculated and output.

In this way, by performing the same operation as that of the filter, for example, when an original signal as shown in FIG. 6A is input, an output as shown in FIG. 6B is obtained. That is, the sixth
When performing a logic operation of the above original signal shown in FIG. (A), FIG. (B) t ₁ parts, as shown in is delayed N clocks
appear in part of t _3, the multipliers 12 ₀ to the portion of t _2, t ₄ before and after
The edge determined by the coefficient of 12 _N is formed stepwise.

Actually, the above-described logical operation is performed in the horizontal and vertical directions. For example, when the original signal shown in FIG. 7A is input, the video effect shown in FIG. 7B is obtained. The original signal is usually white characters, and the edges are colored to make superimposed characters (for example, movie subtitles, time signals, etc.) easier to see.

However, in the above-described conventional logical filter, it is necessary to detect the maximum value of two or more signals.
This maximum value detection circuit can be realized with a relatively simple circuit configuration in an analog circuit, but requires a digital comparator in a digital circuit. Therefore, when trying to generate a signal with a large number of taps (a long edge width), the circuit scale increases and the device becomes large.

(Problems to be Solved by the Invention) As described above, in the conventional logical filter, it is necessary to detect the maximum value of two or more signals, and a signal having a large number of taps (a long edge width) is processed by digital processing. Attempting to generate it increases the circuit scale and the size of the device.

The present invention has been made to solve the above-described problem, and has as its object to provide a small-sized and simple logical filter regardless of the number of taps, that is, an edge width.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a logical filter that adds edges stepwise before and after a rectangular wave signal. A product-sum filter that delays a plurality of stages by the number of clocks, multiplies a signal sequence obtained before and after each delay by a predetermined coefficient sequence, sequentially obtains the sum of the respective operation results, and uses the output of the product-sum filter as an address value in advance. A memory for reading and outputting the corresponding value with reference to the stored look-up table, wherein the coefficient sequence is selected such that the central portion thereof has the maximum value and the values before and after the maximum value become smaller sequentially, and The stored look-up table stores each possible value of the output value of the product-sum filter according to the level by n (n is a natural number of 2 or more).
It is characterized in that the input value is divided into stages and the output value is divided into n stages, and the input and the output are associated with each stage.

(Operation) In the logical filter having the above-described configuration, by using a general product-sum filter formed into an IC that does not require detection of the maximum value, it is possible to cope with an arbitrary edge width by appropriately securing the number of stages in the IC. In the product-sum filter, the coefficient sequence is selected so that the center portion thereof is the maximum value and the values before and after the central portion are smaller in order, so that the input rectangular wave signal portion has the maximum value.
A linear output waveform is obtained in which the output value becomes smaller in order before and after the output value of the product-sum filter is divided into n (n is a natural number of 2 or more) stages according to the level. The linear waveform formed before and after the rectangular wave signal is converted into a step-like edge by referring to a look-up table in which the input and the output are associated with each step.

That is, the edge super generator has a function of adding a symmetrical stepwise edge to a key signal for controlling a mixture ratio of luminance and saturation between a super signal and a background image signal. . To realize this function,
Conventionally, a logical filter having a special circuit configuration using a maximum value detection circuit is used. In an analog circuit, a maximum value detection circuit can be realized with a relatively simple circuit configuration, but a digital circuit requires a digital comparator.
In this case, since a general IC cannot be used, if a signal with a long edge width is to be generated, the circuit scale is considerably increased.

Therefore, in the present invention, the maximum value detection circuit is not used, and a product-sum filter generally used in linear processing is used, so that the number of stages in the IC can be selected according to the edge width. At this time, the edge waveform becomes continuous by the linear processing of the product-sum filter. For this reason, in the present invention, a non-linear process is performed using a look-up table so that the edge waveform becomes stepwise as in the related art.

As described above, the point of the present invention lies in suppressing an increase in circuit scale and reducing costs by using a product-sum filter for linear processing that is easily available as an IC, and using a look-up table. By converting the waveform into a step-like waveform, key signal processing similar to that of a conventional logical filter can be performed.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1 to FIG.

FIG. 1 shows the configuration, in which an input original signal (digital key signal) is supplied to a product-sum filter 21.
The product-sum filter 21 delays the input signal one by one clock by N one-clock delay circuit 22 ₁ through 22 _N, the delay circuits
A very general digital filter that multiplies a signal sequence before and after a delay of 22 _{1 to} 22 _{N by} a predetermined coefficient sequence by multipliers 23 ₀ to 23 _N and obtains a sum thereof by adders 24 _{1 to} 24 _N. A small one is acceptable. The operation result of the product-sum filter 21 is a linear output,
It is supplied to the ROM 25 as an address value. The ROM 25 previously stores a look-up table (hereinafter, referred to as an LUT) for converting a linear output of the product-sum filter 21 into a non-linear output. ROM2 according to the address value from the product-sum filter 21
The data read from 5 is output as a signal with an edge.

The operation of the above configuration will be described below with reference to FIGS. 2 to 4. Note that, here, for simplicity of explanation, it is assumed that the number of taps N is 19, and the same coefficient is used for every three taps in accordance with the current edge super signal.

That is, each of the multipliers 23 ₀ ~ 23 _N of sum-of-products filter 21 registers the coefficient sequence shown in Figure 2. In FIG.
H ₀ , h ₁ , ..., h _{18 in the} upper row represent a signal sequence of 19 taps,
The lower rows a, a, a, b, b, b, c, c, c, d, c, c, c, b, b, b, a, a, a are signal sequences h ₀ , h ₁ ,…, represents a coefficient sequence that corresponds to h _18. The same factor by three taps is registered in the multiplier 23 ₀ ~ 23 _N As can be seen from FIG. Note that a, b, c, and d are supposed to satisfy b> 3a, c> 3a + 3b, and d> 3a + 3b + 3c, respectively.

On the other hand, the ROM 25 stores 0.00 (0%), 0.25 (25%), 0.50 (50%), 0.75 (7
Register LUTs that output values of 5%) and 1.00 (100%).

0 0.00 a to 3a 0.25 b to 3a + 3b 0.50 c to 3a + 3b + 3c 0.75 d to 1.00 Now, if the original signal “1” is input for one clock,
If the first stage in FIG. 3 is output from the integration filter 21 in order from the left and two clocks are input, the result of addition up to the second stage in FIG. 3 is output in order from the left, and so on. Assuming that clocks have been input, the results of addition up to the n-th stage in FIG. 3 are output sequentially from the left.

As an example, a case where an original signal for 10 clocks is input as shown in FIG. 4A will be described.
Are added up to the 10th stage, and the results are output in order from the left. As a result of this addition, according to one clock, a, 2a, 3a, b + 3a, 2b + 3a, 3b + 3a, c + 3b + 3a, 2c + 3b + 3a, 3c + 3b + 3a, d + 3c + 3b + 3a,... 2a and a are output in this order. These are sent to the ROM 25 as address values, and the LUT is referred to. FIG. 4 (b)
9 is a clock delay portion of t ₅ of the original signal as shown in
appear in portions of the t _9, stepped edge of t _6, t _7, t ₈ in front is, so that the stepped edge of t _10, t _11, t ₁₂ behind is added. t _{6 to} t ₈ and t _{10 to} t ₁₂ each correspond to three clocks, and a total of stepwise edges for nine clocks are added before and after.

Therefore, the logical filter according to the above configuration can be realized only by the ROM for storing the normative product-sum filter and the LUT, so that the configuration is extremely simple, and in particular, the existing inexpensive IC can be used for the product-sum filter. , Miniaturization and cost reduction can be realized.

Although the number of taps is set to 19 and the threshold value of the LUT is set to 4 in the above embodiment, it is needless to say that they can be set arbitrarily. Further, in the above embodiment, the case of realizing with a hardware configuration has been described, but it is also possible to replace with software. In addition, various changes can be made without departing from the spirit of the present invention.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a small and simple logical filter regardless of the number of taps.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a logical filter according to the present invention, FIG. 2 is a diagram showing coefficient values of the embodiment, and FIG. 3 explains the operation of the product-sum filter of the embodiment. FIG. 4 is a waveform diagram showing an output value of the embodiment, FIG. 5 is a block diagram showing a configuration of a conventional logical filter, FIG. 6 is a waveform diagram showing an output example of a conventional logical filter, FIG. 7 is a diagram showing a superimposed image by an edge superimposing device using a logical filter. 11 _{1 to} 11 _N ...... Delay circuit, 12 _{0 to} 12 _N ...... Multiplier, 13 _{1 to} 13 _N
…… Maximum calculator, 21… Product-sum filter, 22 _{1 to} 22 _N ……
1 clock delay circuit, 23 ₀ to 23 _N ... multiplier, 24 _{1 to} 24 _N ...
... adder, 25 ... ROM.

Continued on front page (72) Inventor Masaru Kogure 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Komukai Plant, Toshiba Corporation (72) Inventor Katsumi Kubo 1st, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock (72) Inventor Kazumasa Enami 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (72) Inventor Kazuo Fukui 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Broadcasting Research Institute (72) Nobuyuki Yagi 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (72) Ryoichi Yajima 1-10-11 Kinuta, Setagaya-ku, Tokyo (56) References JP-A-1-125070 (JP, A) (58) Fields studied (Int. Cl. ⁶ , DB name) H04N 5/262-5/28

Claims (4)

(57) [Claims] 1. A logical filter for adding edges stepwise before and after a rectangular wave signal, wherein the rectangular wave signal is sequentially delayed by a predetermined number of clocks by a plurality of stages, and a predetermined sequence is added to a signal sequence obtained before and after each delay. A product-sum filter that multiplies the coefficient sequence and sequentially obtains the sum of the respective operation results; and a memory that reads out and outputs the corresponding value by referring to a previously stored look-up table with the output of the product-sum filter as an address value. The coefficient sequence is selected such that the central part thereof has a maximum value and the values before and after the central part become smaller sequentially. The lookup table stored in the memory is a table in which each value that the output value of the product-sum filter can take is obtained. Is divided into n (n is a natural number of 2 or more) stages according to the level, the output value is divided into n stages, and the input and the output are associated with each stage. Logical filter. 2. The multiply-accumulate filter according to claim 1, further comprising: a plurality of delay means for sequentially delaying the rectangular wave signal by a predetermined clock, and a predetermined coefficient string added to a signal string extracted from each input / output tap of the plurality of delay means. 2. The logical filter according to claim 1, comprising: a plurality of multiplying means for multiplying; and a calculating means for sequentially calculating a sum of multiplication results of the plurality of multiplying means and outputting the sum of the product-sum filter. 3. The product-sum filter performs a linear process, and a look-up table stored in the memory divides possible values of the output value of the product-sum filter into n stages, and assigns an output value to each stage to obtain a nonlinear process. The logical filter according to claim 1, wherein the logical filter performs processing. 4. The logical filter according to claim 1, wherein said rectangular wave signal is a key signal for inserting a super signal into a background image signal.