JP2025541490A - 複数層メタライゼーションを含むパワー半導体デバイス - Google Patents

複数層メタライゼーションを含むパワー半導体デバイス

Info

Publication number
JP2025541490A
JP2025541490A JP2025537123A JP2025537123A JP2025541490A JP 2025541490 A JP2025541490 A JP 2025541490A JP 2025537123 A JP2025537123 A JP 2025537123A JP 2025537123 A JP2025537123 A JP 2025537123A JP 2025541490 A JP2025541490 A JP 2025541490A
Authority
JP
Japan
Prior art keywords
metallization layer
semiconductor device
gate
layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2025537123A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025541490A5 (https=
Inventor
サード トーマス エドガー ハリントン
ブライス マクファーソン
スコット アレン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Wolfspeed Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wolfspeed Inc filed Critical Wolfspeed Inc
Publication of JP2025541490A publication Critical patent/JP2025541490A/ja
Publication of JP2025541490A5 publication Critical patent/JP2025541490A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/936—Multiple bond pads having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/721—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having structure or size changed during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/732—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having shape changed during the connecting

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2025537123A 2022-12-22 2023-12-08 複数層メタライゼーションを含むパワー半導体デバイス Pending JP2025541490A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US202263434782P 2022-12-22 2022-12-22
US63/434,782 2022-12-22
US18/160,765 US20240213196A1 (en) 2022-12-22 2023-01-27 Power Semiconductor Devices Including Multiple Layer Metallization
US18/160,765 2023-01-27
PCT/US2023/083034 WO2024137213A1 (en) 2022-12-22 2023-12-08 Power semiconductor devices including multiple layer metallization

Publications (2)

Publication Number Publication Date
JP2025541490A true JP2025541490A (ja) 2025-12-18
JP2025541490A5 JP2025541490A5 (https=) 2026-03-17

Family

ID=91583990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2025537123A Pending JP2025541490A (ja) 2022-12-22 2023-12-08 複数層メタライゼーションを含むパワー半導体デバイス

Country Status (5)

Country Link
US (1) US20240213196A1 (https=)
EP (1) EP4639626A1 (https=)
JP (1) JP2025541490A (https=)
CN (1) CN120548611A (https=)
WO (1) WO2024137213A1 (https=)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661315A (en) * 1995-12-28 1997-08-26 Asea Brown Boveri Ag Controllable power semiconductor component
US7705436B2 (en) * 2007-08-06 2010-04-27 Infineon Technologies Ag Semiconductor device with semiconductor chip and method for producing it
US10522675B2 (en) * 2012-01-25 2019-12-31 Infineon Technologies Ag Integrated circuit including field effect transistor structures with gate and field electrodes and methods for manufacturing and operating an integrated circuit
JP6416142B2 (ja) * 2016-03-11 2018-10-31 株式会社東芝 半導体装置
EP3531457B1 (en) * 2018-02-26 2022-07-20 Infineon Technologies Austria AG Transistor device with gate resistor
EP3686929B1 (en) * 2019-01-24 2023-09-20 Infineon Technologies Dresden GmbH & Co . KG Semiconductor die
US11164813B2 (en) * 2019-04-11 2021-11-02 Cree, Inc. Transistor semiconductor die with increased active area
US10950699B2 (en) * 2019-08-05 2021-03-16 Vishay-Siliconix, LLC Termination for vertical trench shielded devices
US11211324B2 (en) * 2019-09-18 2021-12-28 Intel Corporation Via contact patterning method to increase edge placement error margin
EP3817066A1 (en) * 2019-10-30 2021-05-05 Infineon Technologies Austria AG Semiconductor devices
CN117015852A (zh) * 2021-03-15 2023-11-07 沃孚半导体公司 具有传感器元件的宽带隙半导体器件

Also Published As

Publication number Publication date
CN120548611A (zh) 2025-08-26
US20240213196A1 (en) 2024-06-27
WO2024137213A1 (en) 2024-06-27
EP4639626A1 (en) 2025-10-29

Similar Documents

Publication Publication Date Title
CN104380463B (zh) 用于将多个功率晶体管安装在其上的衬底和功率半导体模块
US20240047431A1 (en) Method of Forming a Semiconductor Module
US12009290B2 (en) Semiconductor module having a multi-branch switch node connector
CN113764372A (zh) 具有信号分配元件的半导体封装
US7274092B2 (en) Semiconductor component and method of assembling the same
US11876041B2 (en) Semiconductor device having a metallization structure
US20230420454A1 (en) Semiconductor device
US11158569B2 (en) Semiconductor component and semiconductor package
US9373566B2 (en) High power electronic component with multiple leadframes
JP2009164288A (ja) 半導体素子及び半導体装置
US11211310B1 (en) Package structures
JP2025541490A (ja) 複数層メタライゼーションを含むパワー半導体デバイス
EP3975244A1 (en) Semiconductor package and method of manufacturing a semiconductor package
CN118899289A (zh) 一种塑封功率模块结构
EP4113605B1 (en) Power semiconductor module arrangement
US12604518B2 (en) Semiconductor device
CN118899288B (zh) 一种塑封功率模块结构
JP2025541490A5 (https=)
US20240297118A1 (en) Semiconductor element and semiconductor device
US20240421112A1 (en) Semiconductor element and semiconductor device
US20210287964A1 (en) Semiconductor devices including parallel electrically conductive layers
CN119767771A (zh) 用于DrMOS的分布式栅极驱动
CN121795152A (zh) 半导体装置
JP2024173373A (ja) 信号伝達装置
JP2024143376A (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20260309

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20260309