JP2025509901A - 信号ルーティング容量を増加させるためのパッド金属化層を採用するパッケージ基板、並びに関連する集積回路（ｉｃ）パッケージ及び製造方法 - Google Patents

信号ルーティング容量を増加させるためのパッド金属化層を採用するパッケージ基板、並びに関連する集積回路（ｉｃ）パッケージ及び製造方法 Download PDF

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JP2025509901A
JP2025509901A JP2024555978A JP2024555978A JP2025509901A JP 2025509901 A JP2025509901 A JP 2025509901A JP 2024555978 A JP2024555978 A JP 2024555978A JP 2024555978 A JP2024555978 A JP 2024555978A JP 2025509901 A JP2025509901 A JP 2025509901A
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metal
layer
pad
metallization layer
package substrate
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Pending
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JP2024555978A
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Japanese (ja)
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JP2025509901A5 (enExample
Inventor
ジョアン・レイ・ヴィラルバ・ビュオ
ジジエ・ワン
アニケット・パティル
ホン・ボク・ウィ
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クアルコム，インコーポレイテッド
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Publication of JP2025509901A publication Critical patent/JP2025509901A/ja
Publication of JP2025509901A5 publication Critical patent/JP2025509901A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
JP2024555978A 2022-03-25 2023-02-24 信号ルーティング容量を増加させるためのパッド金属化層を採用するパッケージ基板、並びに関連する集積回路（ｉｃ）パッケージ及び製造方法 Pending JP2025509901A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/656,477 US20230307336A1 (en) 2022-03-25 2022-03-25 Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods
US17/656,477 2022-03-25
PCT/US2023/063216 WO2023183692A1 (en) 2022-03-25 2023-02-24 Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods

Publications (2)

Publication Number Publication Date
JP2025509901A true JP2025509901A (ja) 2025-04-11
JP2025509901A5 JP2025509901A5 (enExample) 2026-02-19

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JP2024555978A Pending JP2025509901A (ja) 2022-03-25 2023-02-24 信号ルーティング容量を増加させるためのパッド金属化層を採用するパッケージ基板、並びに関連する集積回路（ｉｃ）パッケージ及び製造方法

Country Status (7)

Country Link
US (1) US20230307336A1 (enExample)
EP (1) EP4500590A1 (enExample)
JP (1) JP2025509901A (enExample)
KR (1) KR20240161103A (enExample)
CN (1) CN118786524A (enExample)
TW (1) TW202407815A (enExample)
WO (1) WO2023183692A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250309168A1 (en) * 2024-03-29 2025-10-02 Micron Technology, Inc. Semiconductor package having an array of multi-sized interconnect structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5150518B2 (ja) * 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
US9603247B2 (en) * 2014-08-11 2017-03-21 Intel Corporation Electronic package with narrow-factor via including finish layer
US9431351B2 (en) * 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9420695B2 (en) * 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
KR102065943B1 (ko) * 2015-04-17 2020-01-14 삼성전자주식회사 팬-아웃 반도체 패키지 및 그 제조 방법
US10475736B2 (en) * 2017-09-28 2019-11-12 Intel Corporation Via architecture for increased density interface
US11769719B2 (en) * 2018-06-25 2023-09-26 Intel Corporation Dual trace thickness for single layer routing
US20200027728A1 (en) * 2018-07-23 2020-01-23 Intel Corporation Substrate package with glass dielectric
US11488918B2 (en) * 2018-10-31 2022-11-01 Intel Corporation Surface finishes with low rBTV for fine and mixed bump pitch architectures
US11948877B2 (en) * 2020-03-31 2024-04-02 Qualcomm Incorporated Hybrid package apparatus and method of fabricating
US11605595B2 (en) * 2020-08-14 2023-03-14 Qualcomm Incorporated Packages with local high-density routing region embedded within an insulating layer

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Publication number Publication date
WO2023183692A1 (en) 2023-09-28
EP4500590A1 (en) 2025-02-05
CN118786524A (zh) 2024-10-15
US20230307336A1 (en) 2023-09-28
TW202407815A (zh) 2024-02-16
KR20240161103A (ko) 2024-11-12

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