JP2025107910A - 電界効果トランジスタ - Google Patents

電界効果トランジスタ

Info

Publication number
JP2025107910A
JP2025107910A JP2024001457A JP2024001457A JP2025107910A JP 2025107910 A JP2025107910 A JP 2025107910A JP 2024001457 A JP2024001457 A JP 2024001457A JP 2024001457 A JP2024001457 A JP 2024001457A JP 2025107910 A JP2025107910 A JP 2025107910A
Authority
JP
Japan
Prior art keywords
region
type
contact
type impurity
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024001457A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025107910A5 (https=
Inventor
龍太 鈴木
Ryuta Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Toyota Motor Corp
Mirise Technologies Corp
Original Assignee
Denso Corp
Toyota Motor Corp
Mirise Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp, Toyota Motor Corp, Mirise Technologies Corp filed Critical Denso Corp
Priority to JP2024001457A priority Critical patent/JP2025107910A/ja
Priority to US18/959,932 priority patent/US20250227955A1/en
Priority to CN202510020022.2A priority patent/CN120302682A/zh
Publication of JP2025107910A publication Critical patent/JP2025107910A/ja
Publication of JP2025107910A5 publication Critical patent/JP2025107910A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2024001457A 2024-01-09 2024-01-09 電界効果トランジスタ Pending JP2025107910A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2024001457A JP2025107910A (ja) 2024-01-09 2024-01-09 電界効果トランジスタ
US18/959,932 US20250227955A1 (en) 2024-01-09 2024-11-26 Field effect transistor and manufacturing method of the same
CN202510020022.2A CN120302682A (zh) 2024-01-09 2025-01-07 场效应晶体管及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2024001457A JP2025107910A (ja) 2024-01-09 2024-01-09 電界効果トランジスタ

Publications (2)

Publication Number Publication Date
JP2025107910A true JP2025107910A (ja) 2025-07-22
JP2025107910A5 JP2025107910A5 (https=) 2026-04-20

Family

ID=96263512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024001457A Pending JP2025107910A (ja) 2024-01-09 2024-01-09 電界効果トランジスタ

Country Status (3)

Country Link
US (1) US20250227955A1 (https=)
JP (1) JP2025107910A (https=)
CN (1) CN120302682A (https=)

Also Published As

Publication number Publication date
CN120302682A (zh) 2025-07-11
US20250227955A1 (en) 2025-07-10

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