JP2024543081A - パッドレススタックビアのための凹部構造体 - Google Patents

パッドレススタックビアのための凹部構造体 Download PDF

Info

Publication number
JP2024543081A
JP2024543081A JP2024529232A JP2024529232A JP2024543081A JP 2024543081 A JP2024543081 A JP 2024543081A JP 2024529232 A JP2024529232 A JP 2024529232A JP 2024529232 A JP2024529232 A JP 2024529232A JP 2024543081 A JP2024543081 A JP 2024543081A
Authority
JP
Japan
Prior art keywords
stacked
recess
layer
vias
electrically coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024529232A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024543081A5 (https=
Inventor
ホン・ボク・ウィ
ジョアン・レイ・ヴィラルバ・ビュオ
アニケット・パティル
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2024543081A publication Critical patent/JP2024543081A/ja
Publication of JP2024543081A5 publication Critical patent/JP2024543081A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2024529232A 2021-11-18 2022-10-25 パッドレススタックビアのための凹部構造体 Pending JP2024543081A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/455,576 2021-11-18
US17/455,576 US12230552B2 (en) 2021-11-18 2021-11-18 Recess structure for padless stack via
PCT/US2022/078641 WO2023091846A1 (en) 2021-11-18 2022-10-25 Recess structure for padless stack via

Publications (2)

Publication Number Publication Date
JP2024543081A true JP2024543081A (ja) 2024-11-19
JP2024543081A5 JP2024543081A5 (https=) 2025-10-27

Family

ID=84389276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024529232A Pending JP2024543081A (ja) 2021-11-18 2022-10-25 パッドレススタックビアのための凹部構造体

Country Status (7)

Country Link
US (1) US12230552B2 (https=)
EP (1) EP4434083A1 (https=)
JP (1) JP2024543081A (https=)
KR (1) KR20240101566A (https=)
CN (1) CN118215994A (https=)
TW (1) TW202339155A (https=)
WO (1) WO2023091846A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12198977B2 (en) * 2022-05-24 2025-01-14 Nanya Technology Corporation Manufacturing method of semiconductor structure having elastic member within via
US20250248034A1 (en) * 2024-01-29 2025-07-31 Sandisk Technologies Llc Three-dimensional memory device with a staircase isolation ridge and methods of forming the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689985B2 (en) * 2001-01-17 2004-02-10 Orbotech, Ltd. Laser drill for use in electrical circuit fabrication
JP2007042662A (ja) 2003-10-20 2007-02-15 Renesas Technology Corp 半導体装置
JP5014632B2 (ja) 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
KR101412225B1 (ko) * 2012-08-10 2014-06-25 이비덴 가부시키가이샤 배선판 및 그 제조 방법
US9281242B2 (en) * 2012-10-25 2016-03-08 Nanya Technology Corp. Through silicon via stacked structure and a method of manufacturing the same
US9627318B2 (en) 2014-06-16 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure with footing region
US10325855B2 (en) 2016-03-18 2019-06-18 Qualcomm Incorporated Backside drill embedded die substrate
KR102681797B1 (ko) 2018-12-04 2024-07-03 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
US11362035B2 (en) 2020-03-10 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion barrier layer for conductive via to decrease contact resistance

Also Published As

Publication number Publication date
US20230154829A1 (en) 2023-05-18
CN118215994A (zh) 2024-06-18
US12230552B2 (en) 2025-02-18
KR20240101566A (ko) 2024-07-02
WO2023091846A1 (en) 2023-05-25
TW202339155A (zh) 2023-10-01
EP4434083A1 (en) 2024-09-25

Similar Documents

Publication Publication Date Title
US11757423B2 (en) High harmonic performance radio frequency filter
JP2024543081A (ja) パッドレススタックビアのための凹部構造体
CN115315898A (zh) 具有被划分到多个电耦合基板的混合三维电感器的滤波器封装件
EP4264738B1 (en) Antenna module
US20250062246A1 (en) Structure for delamination mitigation in a semiconductor device
US20260096494A1 (en) Hybrid silicon cap lsc to increase bga density
US20260033364A1 (en) Package interconnect structure
US12155373B2 (en) Backend and acoustic process integration for high-Q filter
JP7797515B2 (ja) 円形ボンドフィンガーパッド
US20240276739A1 (en) Discrete device interconnections between stacked substrates
US20250096094A1 (en) Io interconnect cage structure for package form reduction
US20260090414A1 (en) ADHERED SAP SUBSTRATE FOR CuBOL ASSEMBLY PACKAGE
US20250259937A1 (en) Square thermal via
TW202610002A (zh) 基材中之垂直耦接電感器
TW202314577A (zh) 半導體器件熱凸塊
TW202614429A (zh) 用於ＣｕＢＯＬ裝配封裝的黏著ＳＡＰ基材

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20251008

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20251008