JP2024534046A5 - - Google Patents

Info

Publication number
JP2024534046A5
JP2024534046A5 JP2024509126A JP2024509126A JP2024534046A5 JP 2024534046 A5 JP2024534046 A5 JP 2024534046A5 JP 2024509126 A JP2024509126 A JP 2024509126A JP 2024509126 A JP2024509126 A JP 2024509126A JP 2024534046 A5 JP2024534046 A5 JP 2024534046A5
Authority
JP
Japan
Prior art keywords
scan line
profile
shape profile
gapi
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2024509126A
Other languages
English (en)
Japanese (ja)
Other versions
JP7760704B2 (ja
JP2024534046A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2022/039785 external-priority patent/WO2023022898A1/en
Publication of JP2024534046A publication Critical patent/JP2024534046A/ja
Publication of JP2024534046A5 publication Critical patent/JP2024534046A5/ja
Priority to JP2025135179A priority Critical patent/JP2025166173A/ja
Application granted granted Critical
Publication of JP7760704B2 publication Critical patent/JP7760704B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2024509126A 2021-08-16 2022-08-09 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法 Active JP7760704B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025135179A JP2025166173A (ja) 2021-08-16 2025-08-14 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163260295P 2021-08-16 2021-08-16
US63/260,295 2021-08-16
PCT/US2022/039785 WO2023022898A1 (en) 2021-08-16 2022-08-09 Systems and methods for processing semiconductor wafers using front-end processed wafer geometry metrics

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025135179A Division JP2025166173A (ja) 2021-08-16 2025-08-14 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法

Publications (3)

Publication Number Publication Date
JP2024534046A JP2024534046A (ja) 2024-09-18
JP2024534046A5 true JP2024534046A5 (enExample) 2025-08-04
JP7760704B2 JP7760704B2 (ja) 2025-10-27

Family

ID=83188446

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2024509126A Active JP7760704B2 (ja) 2021-08-16 2022-08-09 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法
JP2025135179A Pending JP2025166173A (ja) 2021-08-16 2025-08-14 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025135179A Pending JP2025166173A (ja) 2021-08-16 2025-08-14 フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法

Country Status (7)

Country Link
US (3) US12385850B2 (enExample)
EP (2) EP4388579B1 (enExample)
JP (2) JP7760704B2 (enExample)
KR (2) KR20250124260A (enExample)
CN (1) CN117999643A (enExample)
TW (1) TW202544952A (enExample)
WO (1) WO2023022898A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12385850B2 (en) * 2021-08-16 2025-08-12 Globalwafers Co., Ltd. Semiconductor wafers using front-end processed wafer global geometry metrics
US20250290745A1 (en) * 2024-03-15 2025-09-18 Tokyo Electron Limited Apparatus and method for determining the surface profile of a semiconductor substrate using a laser scanning technique
WO2026015590A1 (en) 2024-07-10 2026-01-15 Globalwafers Co., Ltd. Systems and methods for analyzing nanotopography of front-end processed semiconductor wafers

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3838341B2 (ja) * 2001-09-14 2006-10-25 信越半導体株式会社 ウェーハの形状評価方法及びウェーハ並びにウェーハの選別方法
US9102033B2 (en) 2010-11-24 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for target thickness and surface profile uniformity control of multi-head chemical mechanical polishing process
JP2012117811A (ja) * 2010-11-29 2012-06-21 Kunitoshi Nishimura ウエハ平坦度測定法
WO2013178459A1 (en) 2012-05-31 2013-12-05 Asml Netherlands B.V. Gradient-based pattern and evaluation point selection
US20140078495A1 (en) 2012-09-14 2014-03-20 Stmicroelectronics, Inc. Inline metrology for attaining full wafer map of uniformity and surface charge
US9430593B2 (en) 2012-10-11 2016-08-30 Kla-Tencor Corporation System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
US10401279B2 (en) 2013-10-29 2019-09-03 Kla-Tencor Corporation Process-induced distortion prediction and feedforward and feedback correction of overlay errors
US9645097B2 (en) * 2014-06-20 2017-05-09 Kla-Tencor Corporation In-line wafer edge inspection, wafer pre-alignment, and wafer cleaning
KR102184033B1 (ko) 2014-06-24 2020-11-27 케이엘에이 코포레이션 반도체 프로세스 제어를 위한 패터닝된 웨이퍼 지오메트리 측정
US9870928B2 (en) 2014-10-31 2018-01-16 Veeco Precision Surface Processing Llc System and method for updating an arm scan profile through a graphical user interface
US10024654B2 (en) 2015-04-06 2018-07-17 Kla-Tencor Corporation Method and system for determining in-plane distortions in a substrate
KR102620998B1 (ko) * 2018-05-25 2024-01-04 삼성전자주식회사 기판 검사 방법, 기판 처리 방법 및 이를 수행하기 위한 기판 처리 시스템
WO2020043525A1 (en) * 2018-08-28 2020-03-05 Asml Netherlands B.V. Systems and methods of optimal metrology guidance
JP6899080B2 (ja) * 2018-09-05 2021-07-07 信越半導体株式会社 ウェーハ形状データ化方法
US12385850B2 (en) * 2021-08-16 2025-08-12 Globalwafers Co., Ltd. Semiconductor wafers using front-end processed wafer global geometry metrics

Similar Documents

Publication Publication Date Title
JP2024534046A5 (enExample)
JP6312370B2 (ja) ウェーハジオメトリ計測ツールによるウェーハ表面フィーチャの検出、分類および定量化のためのシステムおよび方法
CN107683475A (zh) 使用图案化晶片几何测量的过程引发的非对称检测、量化及控制
US20150298282A1 (en) Patterned Wafer Geometry Measurements for Semiconductor Process Controls
CN114631171B (zh) 半导体晶圆的评价方法、半导体晶圆的分选方法及器件的制造方法
JP7010166B2 (ja) ワークの両面研磨装置および両面研磨方法
KR20150033640A (ko) 반도체 웨이퍼의 평가 방법 및 제조 방법
JP7760704B2 (ja) フロントエンド処理されたウェハの形状測定基準を用いて半導体ウェハを処理するためのシステムおよび方法
TWI859807B (zh) 矽晶圓處理方法
KR101870701B1 (ko) 폴리싱 측정 장치 및 그의 연마 시간 제어 방법, 및 그를 포함한 폴리싱 제어 시스템
CN111952208B (zh) 侦测晶圆设定范围内平整度变化的方法
US10643853B2 (en) Wafer thinning apparatus having feedback control and method of using
KR102896814B1 (ko) 워크의 양면 연마 장치 및 양면 연마 방법
CN111587164B (zh) 工件的双面抛光装置及双面抛光方法
JP2017521866A5 (enExample)
TWI921592B (zh) 使用經前端處理之晶圓之幾何度量來處理半導體晶圓之系統及方法