JP2024518963A - Method, apparatus and storage medium for establishing a chip model from a chip layout - Google Patents

Abstract

This application discloses a method, apparatus and storage medium for establishing a chip model from a chip layout, the method includes the steps of: determining a mask in the layout of the chip to be modeled, identifying the process step where the mask is currently located (S1); determining the correlation between the diffusion concentration distribution of the ion implantation material or deposition material corresponding to the mask in the semiconductor substrate material or on the surface and the distance index by using a concentration calculation method adapted to the process step (S2); identifying the process structure shape on the mask, and establishing a diffusion model corresponding to the process structure shape according to the correlation, and the combination of the diffusion model and the process structure shape is the modeling result of the chip to be modeled (S3). The technical solution of this application can make the modeling result of the chip consistent with the actual structure of the chip, and achieve a more accurate modeling effect.

Description

This application claims priority to a Chinese patent application bearing application number 202110964800.5 and entitled "Modeling method for establishing a three-dimensional diffusion model of a chip with EDA software," filed with the China Patent Office on August 23, 2021, the entire contents of which are incorporated herein by reference.

This application relates to the technical field of electrical digital data processing, and more particularly to a method, apparatus, and storage medium for establishing a chip model from a chip layout.

In conventional EDA (Electronic Design Automation) software for rendering chip layouts, it is usually only possible to generate the structure of the mask (or called mask) of each layer in the chip layout, or to simulate a three-dimensional model of the chip using some predefined regular shapes. However, in the actual manufacturing process of a chip, due to the influence of the process, irregular shapes often appear in or on the surface of the semiconductor substrate material, and such irregular shapes cannot be predicted and modeled by conventional EDA software. As a result, when conventional EDA software models a chip, the modeling results obtained do not always match the actual structure of the chip, and a more accurate modeling effect cannot be achieved.

In view of this, the embodiments of the present application provide a method, an apparatus, and a storage medium for establishing a chip model from a chip layout that can match the modeling results of the chip with the actual structure of the chip and achieve a more accurate modeling effect.

According to a first aspect of the present application, a method for establishing a chip model from a chip layout is provided, the method including the steps of: determining a mask in a layout of a chip to be modeled, and identifying a process step in which the mask is currently located; determining a correlation between a diffusion concentration distribution of an ion implantation material or deposition material corresponding to the mask in or on a semiconductor substrate material and a distance index using a concentration calculation method adapted to the process step; identifying a process structure shape on the mask, establishing a diffusion model corresponding to the process structure shape based on the correlation, and determining a combination of the diffusion model and the process structure shape as a modeling result of the chip to be modeled.

In one embodiment, the step of determining a mask in the layout of the chip to be modeled includes the steps of identifying a type of each component in the chip to be modeled, obtaining a submask that matches each component based on the type of each component, combining the submasks that match each component to form the layout of the chip to be modeled, and then automatically generating a multi-layer mask, and determining the automatically generated multi-layer mask as the determined mask.

In one embodiment, identifying the process step in which the mask is currently located includes naming the mask according to the function that the mask realizes, and designating the process step corresponding to the name of the mask as the process step in which the mask is currently located, the process step having a corresponding number.

In one embodiment, the step of determining the correlation between the diffusion concentration distribution of the ion implantation or deposition material corresponding to the mask in or on the semiconductor substrate material and the distance indicator comprises, when the process step is an ion implantation process, the steps of calculating a first ion concentration distribution generated during ion implantation in the semiconductor substrate material, and calculating a second ion concentration distribution generated during an annealing period after ion implantation based on a diffusion effect in the semiconductor substrate material, the second ion concentration distribution having a corresponding relationship with a diffusion coefficient and an annealing time.
The method includes a step of generating a correlation between a diffusion concentration distribution in the semiconductor substrate material and a distance index representing a distance from a center position of ion implantation based on the first ion concentration distribution and the second ion concentration distribution.

前記第２イオン濃度分布は次の式で表され、

前記拡散濃度分布と距離指標との相関関係は次の式で表され、

ここで、Ｃ₁（ｘ）は前記第１イオン濃度分布、Ｃ₂（ｘ）は前記第２イオン濃度分布、Ｃ（ｘ，ｔ）は前記拡散濃度分布と距離指標との相関関係、ｘは前記距離指標、ｔはアニール時間、Ｄは拡散係数、Ｑはイオンの注入量、Ｒｐは平均投影範囲、ΔＲｐは平均投影範囲の標準偏差を表す。 In one embodiment, the first ion concentration distribution is represented by the following formula:

The second ion concentration distribution is expressed by the following formula:

The correlation between the diffusion concentration distribution and the distance index is expressed by the following formula:

Here, _C1 (x) represents the first ion concentration distribution, _C2 (x) represents the second ion concentration distribution, C(x,t) represents the correlation between the diffusion concentration distribution and the distance index, x represents the distance index, t represents the annealing time, D represents the diffusion coefficient, Q represents the ion implantation amount, Rp represents the average projection range, and ΔRp represents the standard deviation of the average projection range.

In one embodiment, the step of determining the correlation between the diffusion concentration distribution of the ion implantation material or deposition material corresponding to the mask in or on the surface of the semiconductor substrate material and the distance index includes, when the process step is a deposition process, calculating the external diffusion concentration distribution and the self-diffusion concentration distribution of the surface of the semiconductor substrate material, respectively, and generating a correlation between the diffusion concentration distribution after deposition on the surface of the semiconductor substrate material and the distance index representing the distance from the surface of the deposited molding to the surface of the substrate based on the external diffusion concentration distribution and the self-diffusion concentration distribution.

前記自己拡散濃度分布は次の式で表され、

前記堆積された後の拡散濃度分布と距離指標との相関関係は次の式で表され、

ここで、Ｃ_e（ｘ，ｔ₁）は前記外部拡散濃度分布、Ｃ_zは前記自己拡散濃度分布、Ｃ（ｘ，ｔ₁）は堆積された後の拡散濃度分布と距離指標との相関関係、ｅｒｆｃは相補誤差関数、ｘは前記距離指標、ｔ₁は堆積時間、Ｃは基板濃度、Ｄ₁は堆積時の拡散係数、Ｃ_sは有効基板表面濃度、Ｌは拡散長さ、Ｃ（ｂａｃｋ）は裏面の自己拡散による濃度定数を表す。 In one embodiment, the outward diffusion concentration profile is represented by the following formula:

The self-diffusion concentration distribution is expressed by the following formula:

The correlation between the diffusion concentration distribution after deposition and the distance index is expressed by the following formula:

Here, C _e (x, t ₁ ) is the external diffusion concentration distribution, C _z is the self-diffusion concentration distribution, C(x, t ₁ ) is the correlation between the diffusion concentration distribution after deposition and the distance index, erfc is the complementary error function, x is the distance index, t ₁ is the deposition time, C is the substrate concentration, D ₁ is the diffusion coefficient during deposition, C _s is the effective substrate surface concentration, L is the diffusion length, and C(back) is the concentration constant due to self-diffusion on the back surface.

In one embodiment, the step of establishing a diffusion model corresponding to the process geometry comprises:
determining a reference concentration value for the process feature based on the correlation;
dividing the reference density value into a plurality of discrete density values and calculating corresponding discrete distances of each of the discrete density values based on the correlation;
generating sub-diffusion models for each of the discrete distances, and combining the sub-diffusion models into a diffusion model corresponding to the process structure shape.

In one embodiment, the step of generating a sub-diffusion model for each said discrete distance comprises:
The method includes the steps of selecting a plurality of reference points on a surface of the process structure shape, generating hemispheres corresponding to the reference points by using the reference points as the center of a sphere, the discrete distance as the radius, and the surface of the process structure shape as a diameter surface, and setting the union of the hemispheres corresponding to each of the reference points as a sub-diffusion model of the discrete distance.

In one embodiment, the step of generating a sub-diffusion model for each of the discrete distances includes the steps of selecting a plurality of first reference points on the surface of the process structure shape and selecting a plurality of second reference points on the vertices and edges of the process structure shape; forming vertical line segments corresponding to the first reference points with the first reference points as endpoints, the discrete distances as lengths, and the surface of the process structure shape as vertical planes, and constructing one or more triangular surfaces based on the endpoints on each of the vertical line segments that are away from the process structure shape; generating a hemisphere corresponding to the second reference point with the second reference point as a sphere center, the discrete distance as a radius, and the surface of the process structure shape as a diameter plane; and defining the union of each of the triangular surfaces and each of the hemispheres corresponding to each of the second reference points as the sub-diffusion model for the discrete distance.

According to a second aspect of the present application, there is provided an apparatus for establishing a chip model from a chip layout, comprising a memory and a processor, the memory being adapted to store a computer program that, when executed by the processor, implements any one of the methods according to the first aspect.

According to a third aspect of the present application, there is provided a non-volatile computer-readable storage medium storing computer-executable instructions that, when executed by an electronic device, cause the electronic device to implement any one of the methods according to the first aspect.

The technical solution of the present application can select an appropriate concentration calculation method for a mask in the layout of the chip to be modeled according to the process step in which the mask is actually located, and determine the correlation between the diffusion concentration distribution of the ion implantation material or deposition material corresponding to the mask in the semiconductor substrate material or on the surface and the distance index. Then, the process structure shape on the mask and the above correlation can be combined to establish a diffusion model corresponding to the process structure shape. The combination of the diffusion model and the process structure shape can be the modeling result of the chip to be modeled. As can be seen from this, the present application takes into account the actual diffusion concentration distribution in the semiconductor substrate material or on the surface when modeling the chip to be modeled, and the diffusion model determined based on the diffusion concentration distribution can match the actual process step, thereby establishing a more accurate chip model.

The features and advantages of the present application can be more clearly understood by referring to the drawings, which are schematic and should not be construed as limiting the present application.

FIG. 2 is a schematic diagram of a method for establishing a chip model from a chip layout in accordance with an embodiment of the present application. FIG. 2 is a schematic diagram of concentration distribution in an ion implantation process in accordance with an embodiment of the present application. FIG. 2 is a schematic diagram of concentration distribution during a deposition process in accordance with an embodiment of the present application. FIG. 2 is a schematic diagram of modeling of a neutron diffusion model in one embodiment of the present application. FIG. 1 is a schematic diagram of a hardware configuration of an electronic device according to an embodiment of the present application.

In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application are described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without any creative efforts fall within the scope of protection of the present application.

Referring to FIG. 1, a method for establishing a chip model from a chip layout according to an embodiment of the present application may include multiple steps, namely, steps S1 to S3.

S1: Determine a mask within the layout of the chip to be modeled and identify the process step in which the mask is currently located.

In this embodiment, when a researcher uses the EDA software to render the layout of the chip to be modeled, the EDA software automatically identifies each component in the layout and obtains a submask corresponding to each component according to the type of each component. In the case of a MOS transistor, the multi-layer structure may usually include a P-type substrate, an N-type well, a P-type base region, an N-type highly doped diffusion region, and a P-type highly doped diffusion region, and the multi-layer structure is composed of multi-layer submasks. After that, the submasks corresponding to each component are combined to form the complete layout of the chip to be modeled, and the EDA software automatically generates a multi-layer mask, and the automatically generated multi-layer mask is the mask determined by the layout of the chip to be modeled.

In this embodiment, the EDA software can continue to identify the function of the mask after obtaining the mask. According to the function that the mask realizes, the EDA software can automatically name the mask. For example, the mask of each layer can be named as TOP layer, P-separator, first metal layer, second metal layer, contact hole layer, N+ injection layer, capacitor dielectric layer, P-buried layer, P-type base region layer, deep N-well layer, P-active region layer, P+ injection layer, PAD oxide layer opening layer, N-type buried layer, and through-hole layer. Different names can correspond to different process steps in the process flow. The process step corresponding to the name of the mask can be the process step where the mask is currently located. Usually, there are multiple process steps in a process flow, and these process steps can be performed in a predetermined order. In view of this, the mask can be numbered according to the order of the process steps of the mask in the process flow. The smaller the number, the earlier the process step is performed.

S2: Using a concentration calculation method adapted to the process step, determine the correlation between the diffusion concentration distribution of the ion implantation material or deposition material corresponding to the mask within or at the surface of the semiconductor substrate material and the distance index.

In this embodiment, during the chip manufacturing process, most of the irregular shapes in or on the semiconductor substrate material are caused by ion implantation or deposition, so three-dimensional modeling can be performed for the irregular shapes caused by ion implantation or deposition, respectively. In practical applications, each mask can be grouped according to the ion implantation process or deposition process. For example, the N+ implantation layer and the P+ implantation layer, etc. are both in the ion implantation group, and the first metal layer and the second metal layer, etc. are both in the deposition group. For different types of process steps, the chip to be modeled on the substrate can be modeled in various ways.

One of the reasons for the formation of irregular shapes after ion implantation is the different concentrations of ions in the semiconductor substrate material, where the higher the concentration, the higher the position (i.e., the closer to the center of the ion implantation, the higher the concentration) and the lower the concentration, the lower the position (i.e., the further away from the center of the ion implantation, the lower the concentration). In light of this, by calculating the concentration distribution of ions in the semiconductor substrate material, three-dimensional modeling can be effectively performed for the chip to be modeled.

ここで、Ｃ₁（ｘ）は前記第１イオン濃度分布、ｘは半導体基板材料における現在の検出点とイオン注入の中心位置との距離を表す距離指標、Ｑはイオンの注入量、Ｒｐは平均投影範囲、ΔＲｐは平均投影範囲の標準偏差を表す。 In a specific application example, when the process step corresponding to the mask is an ion implantation process, a generated first ion concentration distribution of the ion implantation material corresponding to the mask in the semiconductor substrate material during ion implantation can be calculated, which can be expressed as the following formula:

Here, _C1 (x) is the first ion concentration distribution, x is a distance index representing the distance between the current detection point in the semiconductor substrate material and the center position of ion implantation, Q is the ion implantation amount, Rp is the average projection range, and ΔRp is the standard deviation of the average projection range.

In practical applications, the peak concentration after ion implantation is usually in the average projection range, and the larger the ion implantation amount, the higher the peak concentration. In addition, the faster the ion implantation speed and the higher the temperature, the larger the average projection range and the standard deviation of the projection range, and the lower the peak concentration. Therefore, the first ion concentration distribution after ion implantation is related to the ion implantation amount, ion implantation speed, ion implantation temperature, etc., and the specific values of each of the above parameters can be provided by the chip manufacturer to ensure the accuracy and reliability of the three-dimensional modeling.

In this embodiment, after ion implantation, as time passes, ion diffusion effects occur due to the self-action of ions and interactions between ions. Such diffusion effects are particularly noticeable during annealing. In view of this, in order to accurately indicate the distribution of ions in the semiconductor substrate material, a second ion concentration distribution of the ion implanted material generated based on the diffusion effect in the semiconductor substrate material during the annealing period after ion implantation can be calculated. The second ion concentration distribution has a corresponding relationship with the diffusion coefficient and the annealing time.

ここで、Ｃ₂（ｘ）は前記第２イオン濃度分布、ｔはアニール時間、Ｄは拡散係数を表す。 In a specific application example, the second ion concentration distribution can be expressed by the following formula:

Here, C ₂ (x) represents the second ion concentration distribution, t represents the annealing time, and D represents the diffusion coefficient.

The final ion distribution state in the semiconductor substrate material is determined by both the first ion concentration distribution and the second ion concentration distribution. In this embodiment, a correlation between the final diffusion concentration distribution in the semiconductor substrate material and the distance index can be generated based on the first ion concentration distribution and the second ion concentration distribution.

ここで、Ｃ（ｘ，ｔ）は前記拡散濃度分布と距離指標との相関関係を表す。 Specifically, the correlation can be expressed by the following formula:

Here, C(x, t) represents the correlation between the diffusion concentration distribution and the distance index.

In order to ensure the accuracy and reliability of the three-dimensional modeling, the specific values of the annealing times mentioned above are also provided by the chip manufacturer.

Referring to FIG. 2, both the first ion concentration distribution after ion implantation and the final diffusion concentration distribution can decay as the distance index increases, which indicates that the concentration of ions decreases the further away from the center position of the ion implantation.

In another specific application example, when the mask process step is a deposition process, one of the causes of the formation of irregular shapes on the surface of the semiconductor substrate material after deposition is the occurrence of concentration differences depending on the position due to the outward diffusion effect and the self-diffusion effect. In view of this, in this embodiment, three-dimensional modeling can be performed based on the concentration of the deposited material after it is deposited on the surface of the semiconductor substrate material. Specifically, the outward diffusion concentration distribution and the self-diffusion concentration distribution of the deposited material on the surface of the semiconductor substrate material can be calculated, respectively.

ここで、Ｃ_e（ｘ，ｔ₁）は前記外部拡散濃度分布、ｅｒｆｃは相補誤差関数、ｘは堆積された成形物の表面から基板の表面までの距離を表す距離指標、ｔ₁は堆積時間、Ｃは基板濃度、Ｄ₁は堆積時の拡散係数を表す。 The external diffusion concentration distribution can be expressed by the following formula:

Here, C _e (x, t ₁ ) is the external diffusion concentration distribution, erfc is the complementary error function, x is a distance index representing the distance from the surface of the deposited molding to the surface of the substrate, t ₁ is the deposition time, C is the substrate concentration, and D ₁ is the diffusion coefficient during deposition.

ここで、Ｃ_zは前記自己拡散濃度分布を表し、Ｃ_sは有効基板表面濃度を表し、該有効基板表面濃度はチップの製造メーカーによって提供でき、Ｌは拡散長さを表し、該拡散長さは通常０．２５μｍとしてもよい。 After deposition, the self-diffusion effect also causes a change in the concentration of the deposited material on the surface of the semiconductor substrate material. Specifically, the self-diffusion concentration distribution due to the self-diffusion effect can be expressed as follows:

Here, _Cz represents the self-diffusion concentration distribution, _Cs represents the effective substrate surface concentration, which can be provided by the chip manufacturer, and L represents the diffusion length, which may typically be 0.25 μm.

ここで、Ｃ（ｘ，ｔ₁）は堆積された後の拡散濃度分布と距離指標との相関関係、Ｃ（ｂａｃｋ）は裏面の自己拡散による濃度定数を表し、Ｃ（ｂａｃｋ）は通常定数であり、ここでは、１×１０¹⁵ｃｍ^-3に設定できる。 In practical application, the final concentration distribution of the deposition material after being deposited on the surface of the semiconductor substrate material can be determined by both the external diffusion concentration distribution and the self-diffusion concentration distribution. Specifically, based on the external diffusion concentration distribution and the self-diffusion concentration distribution, a correlation can be generated between the diffusion concentration distribution of the deposition material after being deposited on the surface of the semiconductor substrate material and the distance index. The correlation can be expressed by the following formula:

Here, C(x,t ₁ ) is the correlation between the diffusion concentration distribution after deposition and the distance index, C(back) is the concentration constant due to self-diffusion on the back surface, and C(back) is a normal constant, which can be set to 1×10 ¹⁵ cm ⁻³ here.

Referring to Figure 3, the diffusion concentration distribution after deposition can decay as the distance index increases, eventually stabilizing at a concentration represented by C(back), which indicates that the greater the distance from the surface of the deposited molding to the surface of the substrate, the lower the diffusion concentration after deposition.

S3: Identify the process structure shape on the mask, establish a diffusion model corresponding to the process structure shape based on the correlation, and use the combination of the diffusion model and the process structure shape as the modeling result for the chip to be modeled.

In this embodiment, after determining the correlation between the diffusion concentration distribution in the semiconductor substrate material or at the surface and the distance index for different process steps, a diffusion model corresponding to the process structure shape on the mask can be established based on the correlation.

The process structure shape on the mask may be a rectangular parallelepiped or an irregular concave body, etc., and here, a rectangular parallelepiped is taken as an example to explain how to establish a diffusion model corresponding to the process structure shape based on the above correlation. Note that the length and width of the rectangular parallelepiped can be determined by the parameters on the mask, that is, by the circuit design parameters of the research and development engineers. The height of the rectangular parallelepiped is determined by the manufacturing process, and therefore the specific value of the height of the rectangular parallelepiped is also provided by the chip manufacturer.

First, a reference concentration value in the process structure shape can be determined based on the correlation, and the reference concentration value can be the maximum value of the diffusion concentration distribution. For example, in the case of an ion implantation process, the reference concentration value can be C(M) in FIG. 2, where M is a value infinitesimally close to 0, and in the case of a deposition process, the reference concentration value can be the difference between C/2 and C(back) in FIG. 3. In order to model the diffusion situation at different distance indices, the reference concentration value can be divided into multiple discrete concentration values, and the corresponding discrete distances of each discrete concentration value can be calculated based on the correlation. The maximum discrete concentration value obtained by the division is the reference concentration value, and the reference concentration value does not need to be calculated during the subsequent calculation of the discrete distance.

Specifically, assuming that the number of discrete concentration values is N, each discrete concentration value (excluding the reference concentration value) obtained by division in the ion implantation process can be expressed as follows:

In the deposition process, each discrete concentration value (except for the reference concentration value) obtained by division can be expressed as follows:

In practical applications, the discrete concentration values can be substituted as the diffuse concentration distribution into the correlation between the diffuse concentration distribution and the distance index determined in step S2, thereby allowing the corresponding discrete distance of the discrete concentration values to be calculated.

For the corresponding discrete distance of each discrete concentration value, a sub-diffusion model of the discrete distance can be generated. Specifically, in one embodiment, a number of reference points can be randomly selected on the surface of the process structure shape. These reference points can be distributed as uniformly as possible on the surface of the process structure shape. The number of reference points can be set according to actual needs. When the requirement for modeling accuracy is high, the number of reference points can be appropriately increased, and when the requirement for modeling speed is high, the number of reference points can be appropriately reduced.

Referring to FIG. 4, taking a rectangular parallelepiped as an example, after selecting a reference point on the surface of the process structure shape, a hemisphere corresponding to the reference point is generated with the reference point as the center of the sphere, the discrete distance as the radius, and the surface of the process structure shape as the diameter surface. In this way, each reference point can correspond to one hemisphere, and the hemisphere can represent the diffusion trajectory in the ion implantation process or deposition process. A sub-diffusion model of the current discrete distance can be obtained by finding the union of the hemispheres corresponding to each reference point.

Following the above method, each discrete distance can correspond to a respective sub-diffusion model, and finally, the combination of each sub-diffusion model can be made into a diffusion model corresponding to the process structure shape.

The mask for each layer includes one or more process structure shapes, and a combination of diffusion models corresponding to the multiple process structure shapes obtained according to the above method can be part of the three-dimensional modeling result of the chip to be modeled obtained based on the layer mask.

By following the above method and performing three-dimensional modeling based on the masks of each layer of the chip to be modeled, it is possible to finally obtain a three-dimensional model of the entire chip to be modeled.

In one embodiment, in order to increase the modeling speed of the three-dimensional model, the selection of the reference points can be further limited when generating the sub-diffusion model for each discrete distance. Specifically, a plurality of first reference points can be selected on the surface of the process structure shape, and these first reference points do not have to be located at the vertices and edges of the process structure shape, and then a plurality of second reference points can be selected at the vertices and edges of the process structure shape. These two different types of reference points can be processed in different ways. Specifically, for the first reference point, a vertical line segment corresponding to the first reference point is formed with the first reference point as an end point, the discrete distance as a length, and the surface of the process structure shape as a vertical plane, and one or more triangular faces are formed based on the end points on each vertical line segment that are away from the process structure shape. For example, among the end points that are away from the process structure shape, three adjacent end points can be three vertices of a triangular face. In this way, every three end points can form one triangular face. For a second reference point, a hemisphere corresponding to the second reference point can be generated according to the above hemisphere rendering process, with the second reference point as the sphere center, the discrete distance as the radius, and the surface of the process structure shape as the diameter surface. In this way, the first reference point can finally obtain a plurality of corresponding triangular surfaces, and the second reference point can obtain a plurality of corresponding hemispheres, and the union of these triangular surfaces and the hemisphere can be the corresponding sub-diffusion model of the current discrete distance. Similarly, each discrete distance can correspond to a respective sub-diffusion model, and the combination of these sub-diffusion models can be the diffusion model corresponding to the process structure shape.

Note that when performing three-dimensional modeling for the above ion implantation process and deposition process, the specific values of the independent variables are merely examples, and do not mean that modeling must be performed according to the above specific values. Although the modeling method for the ion implantation material or deposition material corresponding to the mask of each layer in or on the surface of the semiconductor substrate material is the same, the values of each independent variable may be different because the specific structures formed by different masks are different. In practical applications, it is necessary to assign values to the independent variables according to the specific structures in order to perform a reasonable calculation and modeling process.

In this application, after performing three-dimensional modeling for each layer mask in the layout of the chip to be modeled and obtaining a three-dimensional model of the chip to be modeled, the researcher can place the mouse at any position on the three-dimensional model, slide the mouse to cut the current position, and then view the cross sections of the XY plane, XZ plane, and YZ plane at that position, facilitating comprehensive detection and verification of each part of the chip.

In the present application, the display method of the three-dimensional model can be made more flexible. For example, in the EDA software, the mask of any layer can be turned off to display only the three-dimensional models of the ion implantation material/deposition material and the semiconductor substrate material corresponding to the mask of a specific layer or layers. In addition, the three-dimensional models of the specific type or types of ion implantation material/deposition material at specific concentrations can be further displayed. This model confirmation method allows researchers to quickly confirm the model of each layer, improving the detection efficiency.

Using this application, researchers can complete 3D modeling in EDA software, and the model can fully display the positional relationship of each part of the chip after ion implantation and deposition. By simply detecting each part, researchers can know whether the chip design complies with the rules and whether a failure situation will occur during the manufacturing process, such as adjacent parts being connected due to diffusion effects due to ion implantation or deposition, thereby improving yield.

As can be seen from this, the technical solution of the present application can select an appropriate concentration calculation method for a mask in the layout of the chip to be modeled according to the process step in which the mask is actually located, and determine the correlation between the diffusion concentration distribution of the ion implantation material or deposition material corresponding to the mask in the semiconductor substrate material or on the surface and the distance index. Then, the process structure shape on the mask and the above correlation can be combined to establish a diffusion model corresponding to the process structure shape. The combination of the diffusion model and the process structure shape can be the modeling result of the chip to be modeled. As can be seen from this, when modeling the chip to be modeled, the present application takes into account the actual diffusion concentration distribution in the semiconductor substrate material or on the surface, and the diffusion model determined based on the diffusion concentration distribution can match the actual process step, thereby establishing a more accurate chip model.

One embodiment of the present application is
a process step identification unit for determining a mask within the layout of the chip to be modeled and for identifying the process step in which said mask is currently located;
a correlation determination unit for determining a correlation between a distance indicator and a diffusion concentration distribution of an ion implantation or deposition material corresponding to said mask in or on a semiconductor substrate material using a concentration calculation method adapted to said process step;
The present invention further provides a system for establishing a chip model from a chip layout, the system including: a modeling unit for identifying process structure shapes on the mask, establishing a diffusion model corresponding to the process structure shapes based on the correlation, and making a combination of the diffusion model and the process structure shapes into a modeling result of the chip to be modeled.

An embodiment of the present application further provides an apparatus for establishing a chip model from a chip layout, the apparatus including a memory and a processor, the memory being adapted to store a computer program that, when executed by the processor, implements the method for establishing a chip model from a chip layout described above.

The processor may be a Central Processing Unit (CPU). The processor may also be other general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other chips, or a combination of the above chips.

The memory, as a non-transitory computer-readable storage medium, can store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions/modules corresponding to the methods in the embodiments of the present application. The processor executes the non-transitory software programs, instructions and modules stored in the memory to perform the various functional applications and data processing of the processor, i.e., to realize the methods in the above method embodiments.

The memory may include a program storage area capable of storing an operating system, application programs required for at least one function, and a data storage area capable of storing data created by the processor. The memory may also include high-speed random access memory, and may further include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may selectively include memory that is remotely located relative to the processor, and these remote memories may be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, a corporate intranet, a local area network, a mobile communications network, and combinations thereof.

An embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions that, when executed by an electronic device, cause the electronic device to implement the method for establishing a chip model from a chip layout described above.

Figure 5 is a schematic diagram of a hardware configuration of an electronic device that executes a method for establishing a chip model from a chip layout according to an embodiment of the present application. As shown in Figure 5, the device includes one or more processors 510 and a memory 520. In Figure 5, one processor 510 is taken as an example. The device that executes the method for establishing a chip model from a chip layout may further include an input device 530 and an output device 540.

The processor 510, memory 520, input device 530, and output device 540 may be connected by a bus or other method, but FIG. 5 shows an example of connection by a bus.

The memory 520 can be used as a non-volatile computer readable storage medium to store non-volatile software programs, non-volatile computer executable programs and modules, such as corresponding program instructions/modules of the method for establishing a chip model from a chip layout in the embodiment of the present application. The processor 510 executes the non-volatile software programs, instructions and modules stored in the memory 520 to execute various functional applications and data processing of the server, i.e., to realize the method for establishing a chip model from a chip layout in the above method embodiment.

The memory 520 may include a program storage area capable of storing an operating system, an application program required for at least one function, and a data storage area capable of storing data generated based on use of the device for establishing a chip model from a chip layout, etc. The memory 520 may also include high-speed random access memory, and may further include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 520 may selectively include memory located remotely relative to the processor 510, and these remote memories may be connected to the device for establishing a chip model from a chip layout via a network. Examples of such networks include, but are not limited to, the Internet, a corporate intranet, a local area network, a mobile communication network, and combinations thereof.

The input device 530 can receive input numeric or textual information and generate key signal inputs related to user settings and function control of the device that establishes the chip model from the chip layout. The output device 540 can include a display device such as a display screen.

The one or more modules are stored in the memory 520 and, when executed by the one or more processors 510, perform a method for establishing a chip model from a chip layout of any of the method embodiments described above.

The above product can execute the method according to the embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in the present embodiment, reference can be made to the method according to the embodiment of the present application.

Electronic devices according to embodiments of the present application may exist in a variety of forms, including but not limited to the following:
(1) Mobile communication devices: These devices are characterized by having mobile communication functions and are primarily intended to provide voice and data communications. Such terminals include smartphones (e.g., iPhone), multimedia mobile phones, functional mobile phones, and low-end mobile phones.
(2) Highly Mobile Personal Computer Devices: These devices fall under the category of personal computers and have computing and processing capabilities, and generally also have mobile Internet characteristics. Such terminals include PDAs, MIDs, and UMPC devices, such as the iPad.
(3) Portable Entertainment Devices: These devices can display and play multimedia content, including audio and video players (e.g., iPod), portable game consoles, e-books, smart toys, and portable car navigation devices.
(4) Server: A server is a device that provides computing services. It includes a processor, a hard disk, memory, a system bus, etc. The server is similar to a general-purpose computer architecture, but because it needs to provide highly reliable services, it has high requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc.
(5) Other electronic devices with data interaction capabilities.

The above-mentioned device embodiments are merely exemplary, and the units described as separate components may or may not be physically separated, and the components shown as units may not be physical units, i.e., may be located in one place or may be distributed among multiple network units. The objective of the solution of the present embodiment can be realized by selecting some or all of its modules according to actual needs.

As will be apparent to those skilled in the art from the above description of the embodiments, each embodiment can be realized by software and a general-purpose hardware platform, and of course, can be realized by hardware. Based on this understanding, the above technical means or the part that contributes to the related technology can essentially be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes some instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute the method described in each embodiment or part of the embodiment.

An embodiment of the present application further provides a computer program that, when executed by a processor, realizes the method for establishing a chip model from the above chip layout.

As can be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be realized by issuing instructions to relevant hardware by a computer program, and the program may be stored in a computer-readable storage medium, which, when executed, may include the processes of the above embodiments of the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), and the storage medium may further include a combination of the above types of memory.

Although the embodiments of the present application have been described with reference to the drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims (12)

1. A method for establishing a chip model from a chip layout, the method comprising:
determining a mask within the layout of the chip to be modeled and identifying a process step in which the mask is currently located, the process step including an ion implantation process or a deposition process;
determining a correlation between a diffusion concentration distribution of an ion implantation material corresponding to the mask in a semiconductor substrate material and a distance index using a concentration calculation method adapted to the process step, and determining a correlation between a diffusion concentration distribution of a deposition material corresponding to the mask in a surface of the semiconductor substrate material and a distance index;
identifying process structure shapes on the mask, establishing a diffusion model corresponding to the process structure shapes based on the correlation, and defining a combination of the diffusion model and the process structure shapes as a modeling result of the chip to be modeled. The step of determining a mask in a layout of a chip to be modeled comprises:
2. The method of claim 1, further comprising the steps of: identifying a type of each component in the chip to be modeled; obtaining a submask matching each of the components based on the type of each component; combining the submasks matching each of the components to form a layout of the chip to be modeled; and automatically generating a multi-layer mask, the automatically generated multi-layer mask being the determined mask. The step of identifying a process step in which the mask is currently located comprises:
2. The method of claim 1, further comprising the steps of naming the mask according to the function it realizes and designating the process step corresponding to the name of the mask as the process step in which the mask is currently located, the process step having a corresponding number. The step of determining a correlation between a diffusion concentration distribution of an ion implantation material corresponding to the mask in a semiconductor substrate material and a distance index includes:
calculating a first ion concentration distribution produced during ion implantation in the semiconductor substrate material;
Calculating a second ion concentration distribution generated based on a diffusion effect in the semiconductor substrate material during an annealing period after ion implantation, the second ion concentration distribution having a corresponding relationship with a diffusion coefficient and an annealing time;
2. The method of claim 1, further comprising: generating a correlation between a diffusion concentration distribution in the semiconductor substrate material and a distance index representing a distance from a center position of ion implantation based on the first ion concentration distribution and the second ion concentration distribution. The first ion concentration distribution is expressed by the following formula:

The second ion concentration distribution is expressed by the following formula:

The correlation between the diffusion concentration distribution and the distance index is expressed by the following formula:

The method according to claim 4, wherein _C1 (x) represents the first ion concentration distribution, _C2 (x) represents the second ion concentration distribution, C(x,t) represents the correlation between the diffusion concentration distribution and the distance index, x represents the distance index, t represents the annealing time, D represents the diffusion coefficient, Q represents the ion implantation amount, Rp represents the average projection range, and ΔRp represents the standard deviation of the average projection range. The step of determining a correlation between a diffusion concentration distribution of a deposition material corresponding to the mask on a surface of a semiconductor substrate material and a distance index includes:
calculating the out-diffusion concentration profile and the self-diffusion concentration profile of the surface of the semiconductor substrate material, respectively;
2. The method of claim 1, further comprising: generating a correlation between a diffusion concentration distribution after deposition on the surface of the semiconductor substrate material and a distance index representing a distance from a surface of the deposited molding to a surface of the substrate based on the external diffusion concentration distribution and the self-diffusion concentration distribution. The external diffusion concentration distribution is expressed by the following formula:

The self-diffusion concentration distribution is expressed by the following formula:

The correlation between the diffusion concentration distribution after deposition and the distance index is expressed by the following formula:

Here, C _e (x, t ₁ ) represents the external diffusion concentration distribution, C _z represents the self-diffusion concentration distribution, C(x, t ₁ ) represents the correlation between the diffusion concentration distribution after deposition and the distance index, erfc is the complementary error function, x is the distance index, t ₁ is the deposition time, C is the substrate concentration, D ₁ is the diffusion coefficient during deposition, C _s is the effective substrate surface concentration, L is the diffusion length, and C(back) represents the concentration constant due to self-diffusion on the back surface. Establishing a diffusion model corresponding to the process geometry comprises:
determining a reference concentration value for the process feature based on the correlation;
dividing the reference density value into a plurality of discrete density values and calculating corresponding discrete distances of each of the discrete density values based on the correlation;
2. The method of claim 1, further comprising: generating a sub-diffusion model for each of the discrete distances; and combining the sub-diffusion models into a diffusion model corresponding to the process structure shape. The step of generating a sub-diffusion model for each of the discrete distances comprises:
selecting a plurality of reference points on a surface of the process structure shape, and generating a hemisphere corresponding to the reference points, the reference points being the sphere center, the discrete distance being the radius, and the surface of the process structure shape being the diameter surface;
and determining the union of hemispheres corresponding to each of the reference points as the discrete distance sub-diffusion model. The step of generating a sub-diffusion model for each of the discrete distances comprises:
selecting a first plurality of reference points on a surface of the process structure shape and a second plurality of reference points on vertices and edges of the process structure shape;
forming vertical line segments corresponding to the first reference points using the first reference points as endpoints, the discrete distances as lengths, and a surface of the process structure shape as a vertical plane, and constructing one or more triangular faces based on endpoints of each of the vertical line segments that are away from the process structure shape;
generating a hemisphere corresponding to the second reference point, with the second reference point as a sphere center, the discrete distance as a radius, and a surface of the process structure shape as a diameter surface;
and determining the union of each of the triangular surfaces and a hemisphere corresponding to each of the second reference points as the discrete distance sub-diffusion model. An apparatus for establishing a chip model from a chip layout, comprising a memory and a processor, the memory being used to store a computer program that, when executed by the processor, implements the method according to any one of claims 1 to 10. A non-volatile computer-readable storage medium storing computer-executable instructions that, when executed by an electronic device, cause the electronic device to implement the method according to any one of claims 1 to 10.

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