WO2023024872A1 - Method and apparatus for establishing chip model in layout of chip, and storage medium - Google Patents

Abstract

Disclosed in the present application are a method and apparatus for establishing a chip model in a layout of a chip, and a storage medium. The method comprises: determining a mask in a layout of a chip to be modeled, and identifying the current process step of the mask (S1); by using a concentration calculation mode that is adapted to the process step, determining an association relationship between the diffusion concentration distribution, in or on the surface of a semiconductor substrate material, of an injected or deposited material corresponding to the mask and a distance index (S2); and identifying a technological structure shape on the mask, establishing, on the basis of the association relationship, a diffusion model corresponding to the technological structure shape, and taking a combination of the diffusion model and the technological structure shape as a modeling result of the chip to be modeled (S3). By means of the technical solution provided in the present application, a modeling result of a chip can be consistent with the actual structure of the chip, thereby achieving a more accurate modeling effect.

Description

A method, device and storage medium for building a chip model from a chip layout

This application claims the priority of the Chinese patent application with the application number 202110964800.5 and the title "a modeling method for establishing a three-dimensional diffusion model of a chip in EDA software" submitted to the China Patent Office on August 23, 2021, the entire content of which Incorporated in this application by reference.

technical field

The present application relates to the technical field of electrical digital data processing, in particular to a method, device and storage medium for establishing a chip model from a chip layout.

Background technique

In the existing EDA (Electronic design automation, electronic design automation) software for drawing chip layout, usually only the structure of each layer mask (or mask) in the chip layout can be generated, or some predefined Regular shape to simulate the three-dimensional model of the chip. However, in the actual manufacturing process of the chip, affected by the process flow, it often leads to irregular shapes in or on the surface of the semiconductor substrate material, and this irregular shape cannot be expected and ignored in the existing EDA software. modeled. As a result, when the existing EDA software models the chip, the obtained modeling results often do not match the actual structure of the chip, thus failing to achieve a more accurate modeling effect.

Contents of the invention

In view of this, the embodiments of the present application provide a method, device and storage medium for establishing a chip model from a chip layout, which can make the modeling result of the chip consistent with the actual structure of the chip, thereby achieving a more accurate modeling effect.

According to the first aspect of the present application, there is provided a method for establishing a chip model from a chip layout, the method comprising: determining a mask in the layout of the chip to be modeled, and identifying the current process of the mask Step: Determine the relationship between the diffusion concentration distribution and the distance index of the implanted or deposited material corresponding to the mask plate in the semiconductor substrate material or on the surface by using a concentration calculation method suitable for the process steps; The shape of the process structure on the mask plate, and based on the association relationship, establish a diffusion model corresponding to the shape of the process structure, and use the combination of the diffusion model and the shape of the process structure as the chip to be modeled modeling results.

In one embodiment, determining the mask plate in the layout of the chip to be modeled includes: identifying the type of each component in the chip to be modeled, and obtaining the matching mask for each component according to the type of each component. sub-masks, after combining the sub-masks matching the various components to form the layout of the chip to be modeled, a multi-layer mask is automatically generated, and the automatically generated multi-layer mask as a definitive mask.

In one embodiment, identifying the current process step of the reticle includes: naming the reticle according to the function realized by the reticle, and assigning the name of the reticle to the corresponding process The step is used as the current process step of the mask plate; wherein, the process step has a corresponding number.

In one embodiment, determining the relationship between the diffusion concentration distribution of the implanted or deposited material corresponding to the mask in the semiconductor substrate material or on the surface and the distance index includes: if the process step is an ion implantation process, calculating The first ion concentration distribution generated during ion implantation in the semiconductor substrate material; during the annealing period after ion implantation, calculating the second ion concentration distribution based on the diffusion effect in the semiconductor substrate material; wherein, the The second ion concentration distribution has a corresponding relationship with the diffusion coefficient and annealing time; according to the first ion concentration distribution and the second ion concentration distribution, a relationship between the diffusion concentration distribution and the distance index in the semiconductor substrate material is generated. ; Wherein, the distance index represents the distance from the ion implantation center.

In one embodiment, the first ion concentration distribution is represented by the following formula:

The second ion concentration distribution is expressed by the following formula:

The relationship between the diffusion concentration distribution and the distance index is expressed by the following formula:

Wherein, C ₁ (x) represents the first ion concentration distribution, C ₂ (x) represents the second ion concentration distribution, C(x,t) represents the relationship between the diffusion concentration distribution and the distance index, x represents the distance index, t represents the annealing time, D represents the diffusion coefficient, Q represents the ion implantation dose, R _p represents the average projected range, and ΔR _p represents the standard deviation of the average projected range.

In one embodiment, determining the relationship between the diffusion concentration distribution of the implanted or deposited material corresponding to the mask plate in the semiconductor substrate material or on the surface and the distance index includes: if the process step is a deposition process, respectively Calculating the out-diffusion concentration distribution and self-diffusion concentration distribution on the surface of the semiconductor substrate material; according to the out-diffusion concentration distribution and the self-diffusion concentration distribution, generating the diffusion concentration distribution and The correlation relationship of the distance index; wherein, the distance index represents the distance from the surface of the deposition shaped body to the surface of the substrate.

In one embodiment, the out-diffusion concentration distribution is represented by the following formula:

The self-diffusion concentration distribution is expressed by the following formula:

The relationship between the diffusion concentration distribution and the distance index after the deposition is expressed by the following formula:

Wherein, C _e (x, t ₁ ) represents the outer diffusion concentration distribution, C _z represents the self-diffusion concentration distribution, C (x, t ₁ ) represents the relationship between the diffusion concentration distribution after deposition and the distance index, erfc represents the complementary error function, x represents the distance index, t ₁ represents the deposition time, C represents the substrate concentration, D ₁ represents the diffusion coefficient during deposition, C _s represents the effective substrate surface concentration, L represents the diffusion length, C( back) represents the concentration constant resulting from back self-diffusion.

In one embodiment, establishing the diffusion model corresponding to the shape of the process structure includes: determining a reference concentration value in the shape of the process structure based on the association relationship; dividing the reference concentration value into a plurality of discrete concentration values, And based on the association relationship, respectively calculate the discrete distance corresponding to each of the discrete concentration values; generate the sub-diffusion models of each of the discrete distances, and use the combination of each of the sub-diffusion models as the corresponding to the shape of the process structure Diffusion model.

In one embodiment, generating the sub-diffusion models of each of the discrete distances includes: selecting a plurality of reference points on the surface of the process structure shape, taking the reference points as the center of the sphere, and taking the discrete distance as the radius , using the surface of the process structure shape as a diameter surface to generate a hemisphere corresponding to the reference point; using the union of the hemispheres corresponding to each of the reference points as the sub-diffusion model of the discrete distance.

In one embodiment, generating the sub-diffusion models of each of the discrete distances includes: selecting a plurality of first reference points on the surface of the process structure shape, and selecting a plurality of first reference points on the vertices and edges of the process structure shape The second reference point; using the first reference point as an end point, taking the discrete distance as a length, and using the surface of the process structure shape as a vertical plane, forming a vertical line segment corresponding to the first reference point, and according to each One or more triangular surfaces are formed by the endpoints of the vertical line segment away from the shape of the process structure; with the second reference point as the center of the sphere, the discrete distance as the radius, and the surface of the shape of the process structure A hemisphere corresponding to the second reference point is generated for a diameter surface; a union of each of the triangular surfaces and the hemisphere corresponding to each of the second reference points is used as a sub-diffusion model of the discrete distance.

According to the second aspect of the present application, there is provided an apparatus for establishing a chip model from a chip layout, the apparatus includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, Any method according to the first aspect is implemented.

According to a third aspect of the present application, a non-volatile computer-readable storage medium is provided, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by an electronic device, cause the electronic device to Any method according to the first aspect is implemented.

In the technical solution provided by this application, for the mask plate in the layout of the chip to be modeled, the appropriate concentration calculation method can be selected according to the actual process steps of the mask plate to determine the corresponding injection or deposition of the mask plate. The relationship between the diffusion concentration distribution of the deposited material in the semiconductor substrate material or on the surface and the distance index. Subsequently, in combination with the shape of the process structure on the mask and the above-mentioned correlation, a diffusion model corresponding to the shape of the process structure can be established. The combination of the diffusion model and the shape of the process structure can be used as the modeling result of the chip to be modeled. It can be seen that the present application considers the actual diffusion concentration distribution in or on the surface of the semiconductor substrate material when modeling the chip to be modeled, and the diffusion model determined based on the diffusion concentration distribution can be consistent with the actual process steps, thereby establishing A more accurate chip model is produced.

Description of drawings

The features and advantages of the present application will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the application in any way. In the accompanying drawings:

FIG. 1 shows a schematic diagram of a method for establishing a chip model from a chip layout in one embodiment of the present application;

Figure 2 shows a schematic diagram of the concentration distribution under the ion implantation process in one embodiment of the present application;

FIG. 3 shows a schematic diagram of the concentration distribution under the deposition process in one embodiment of the present application;

Fig. 4 shows a modeling schematic diagram of a neutron diffusion model in an embodiment of the present application

FIG. 5 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the application. Obviously, the described embodiments It is a part of embodiment of this application, and is not all embodiment. Based on the implementation manners in this application, all other implementation manners obtained by those skilled in the art without creative efforts shall fall within the scope of protection of this application.

Referring to FIG. 1 , a method for establishing a chip model from a chip layout provided by an embodiment of the present application may include the following steps.

S1: Determine the mask in the layout of the chip to be modeled, and identify the current process step of the mask.

In this embodiment, when the R&D personnel draw the layout of the chip to be modeled in the EDA software, the EDA software automatically recognizes each component in the layout, and obtains the sub-mask corresponding to each component according to the type of each component. The stencil, for a MOS transistor, usually includes a multi-layer structure such as a P-type substrate, an N-type well, a P-type base region, an N-type heavily doped diffusion region, and a P-type heavily doped diffusion region. The layer structure is composed of multi-layer sub-masks; after combining the sub-masks corresponding to each component to form a complete layout of the chip to be modeled, the EDA software automatically generates a multi-layer mask, and the automatically generated multi-layer The mask plate is used as the mask plate determined in the layout of the chip to be modeled.

In this embodiment, after the EDA software obtains the mask, it can continue to identify the function of the mask. According to the functions realized by the mask, the EDA software can automatically name the mask. For example, the masks of each layer can be named: TOP layer, P-isolation layer, first metal layer, second metal layer, contact hole layer, N+ injection layer, capacitor dielectric layer, P-buried layer, P-type base region layer, deep N well layer, P-active region layer, P+ injection layer, PAD oxide layer opening layer, N-type buried layer and via layer, etc. Wherein, different names may correspond to different process steps in the process flow. The process step corresponding to the mask name can be used as the current process step of the mask. Generally speaking, there are multiple process steps in the process flow, and these process steps can be executed sequentially in a specified order. In view of this, the mask plates can be numbered according to the order of the process steps of the mask plates in the process flow. Wherein, the smaller the number, the earlier the execution order of the process steps.

S2: Determine the relationship between the diffusion concentration distribution and the distance index of the implanted or deposited material corresponding to the mask plate in the semiconductor substrate material or on the surface by using a concentration calculation method suitable for the process steps.

In this embodiment, considering that most of the irregular shapes in or on the surface of the semiconductor substrate material are caused by ion implantation and deposition during the chip manufacturing process, the ion implantation and deposition bands can be respectively 3D modeling of irregular shapes. In practical applications, each mask can be grouped according to ion implantation process or deposition process. For example, the N+ implantation layer and the P+ implantation layer are both ion implantation groups, and the first metal layer and the second metal layer are both deposition groups. For different types of process steps, different methods can be used to model the chip to be modeled on the substrate.

After ion implantation, one of the reasons for the formation of irregular shapes is that there is a difference in the concentration of ions in the semiconductor substrate material. The higher the concentration, the higher the concentration (that is, the closer to the ion implantation center, the higher the concentration), and the lower the concentration, the higher the concentration. In view of this, by calculating the concentration distribution of ions in the semiconductor substrate material, three-dimensional modeling of the chip to be modeled can be effectively carried out.

In a specific application example, if the process step corresponding to the mask plate is an ion implantation process, the first ion concentration distribution generated by the implant material corresponding to the mask plate in the semiconductor substrate material during ion implantation can be calculated first . Wherein, the first ion concentration distribution can be expressed by the following formula:

Wherein, C ₁ (x) represents the first ion concentration distribution, x represents a distance index, and the distance index represents the distance between the current detection point in the semiconductor substrate material and the ion implantation center position, and Q represents the ion implantation dose , R _p represents the average projected range, and ΔR _p represents the standard deviation of the average projected range.

In practical applications, the peak concentration after ion implantation is usually at the average projected range, and the greater the ion implantation dose, the higher the peak concentration. In addition, the faster the ion implantation speed and the higher the temperature, the larger the average projected range and the standard deviation of the projected range will be, and the lower the peak concentration will be. Therefore, the first ion concentration distribution of ions after implantation is related to the dose of ion implantation, the speed of ion implantation, and the temperature of ion implantation. In order to ensure the accuracy and authenticity of three-dimensional modeling, the specific parameters of the above parameters The value can be provided by the chip manufacturer.

In this embodiment, after the ion implantation, as time goes by, the ion's own action and the interaction between the ions will cause the diffusion effect of the ions. This diffusion effect is especially pronounced during annealing. In view of this, in order to accurately represent the distribution of ions in the semiconductor substrate material, the second ion concentration distribution generated by the implanted material in the semiconductor substrate material based on the diffusion effect can be calculated during the annealing period after the ion implantation. Wherein, the second ion concentration distribution has a corresponding relationship with the diffusion coefficient and the annealing time.

In a specific application example, the second ion concentration distribution can be expressed by the following formula:

Wherein, C ₂ (x) represents the second ion concentration distribution, t represents the annealing time, and D represents the diffusion coefficient.

The final ion distribution in the semiconductor substrate material is jointly determined by the above-mentioned first ion concentration distribution and the second ion concentration distribution. In this embodiment, the relationship between the final diffusion concentration distribution in the semiconductor substrate material and the above-mentioned distance index can be generated based on the above-mentioned first ion concentration distribution and the second ion concentration distribution.

Specifically, the association relationship can be expressed by the following formula:

Wherein, C(x, t) represents the relationship between the diffusion concentration distribution and the distance index.

It should be noted that, in order to ensure the accuracy and authenticity of the three-dimensional modeling, the specific value of the above-mentioned annealing time is also provided by the chip manufacturer.

Please refer to Fig. 2, both the first ion concentration distribution and the final diffusion concentration distribution after ion implantation can attenuate with the increase of the distance index, indicating that the farther away from the center of ion implantation, the lower the concentration of ions.

In another specific application example, if the process step of the mask plate is a deposition process, one of the reasons why the surface of the semiconductor substrate material forms an irregular shape after deposition is that the external diffusion effect and the self-diffusion effect lead to different positions. concentration difference. In view of this, in this embodiment, three-dimensional modeling can be performed according to the concentration of the deposition material after deposition on the surface of the semiconductor substrate material. Specifically, the out-diffusion concentration distribution and the self-diffusion concentration distribution of the deposited material on the surface of the semiconductor substrate material can be calculated respectively.

Wherein, the outer diffusion concentration distribution can be expressed by the following formula:

Among them, C _e (x, t ₁ ) represents the concentration distribution of the outer diffusion, erfc represents the complementary error function, x represents the distance index, which represents the distance from the surface of the deposited shaped body to the surface of the substrate, and t ₁ represents the deposition time , C represents the substrate concentration, and _D1 represents the diffusion coefficient during deposition.

After deposition, the self-diffusion effect will also lead to changes in the concentration of the deposited material on the surface of the semiconductor substrate material. Specifically, the self-diffusion concentration distribution caused by the self-diffusion effect can be expressed by the following formula:

Wherein, C _z represents the self-diffusion concentration distribution, C _s represents the effective substrate surface concentration, which can also be provided by the chip manufacturer, and L represents the diffusion length, which can usually be 0.25 μm.

In practical applications, the final concentration distribution of the deposition material after deposition on the surface of the semiconductor substrate material can be jointly determined by the aforementioned out-diffusion concentration distribution and self-diffusion concentration distribution. Specifically, according to the out-diffusion concentration distribution and the self-diffusion concentration distribution, the relationship between the diffusion concentration distribution and the distance index after the deposition material is deposited on the surface of the semiconductor substrate material can be generated. Among them, the relationship can be expressed as:

Among them, C(x,t ₁ ) represents the relationship between the diffusion concentration distribution after deposition and the distance index, C(back) represents the concentration constant produced by self-diffusion on the back surface, and C(back) is usually a constant, where Set to 1×10 ¹⁵ cm ⁻³ .

Please refer to Figure 3, the diffusion concentration distribution after deposition can attenuate with the increase of the distance index, and finally stabilize at the concentration represented by C(back), indicating that the farther the distance from the surface of the deposited molded body to the surface of the substrate, The lower the diffusion concentration after deposition.

S3: Identify the shape of the process structure on the mask, and based on the association, establish a diffusion model corresponding to the shape of the process structure, and use the combination of the diffusion model and the shape of the process structure as the target Modeling results of the modeled chip.

In this embodiment, after determining the relationship between the diffusion concentration distribution in the semiconductor substrate material or on the surface and the distance index for different process steps, the process structure shape on the mask can be established based on the relationship. The corresponding diffusion model.

The shape of the process structure on the mask can be a cuboid or an irregular concave, etc. Here, a cuboid is taken as an example to illustrate how to establish a diffusion model corresponding to the shape of the process structure based on the above-mentioned correlation. It should be noted that the length and width of the cuboid can be determined by the parameters on the mask, that is, by the circuit design parameters of the developer. The height of the cuboid is determined by the manufacturing process, therefore, the specific value of the height of the cuboid is also provided by the chip manufacturer.

Firstly, a reference concentration value in the shape of the process structure may be determined based on the association relationship, and the reference concentration value may be the maximum value of the diffusion concentration distribution. For example, for the ion implantation process, the reference concentration value can be C(M) in FIG. 2, wherein M is a value infinitely close to 0; and for the deposition process, the reference concentration value can be The difference between C/2 and C(back) in Figure 3. In order to model the diffusion situation at different distance indicators, the reference concentration value can be divided into multiple discrete concentration values, and based on the above-mentioned correlation, the respective discrete distances corresponding to each discrete concentration value are calculated. Wherein, the maximum discrete concentration value obtained by division is the above-mentioned reference concentration value, and the reference concentration value may not be calculated when calculating the discrete distance later.

Specifically, assuming that the number of discrete concentration values is N, then under the ion implantation process, each discrete concentration value obtained by division (except the reference concentration value) can be expressed as:

Under the deposition process, each discrete concentration value obtained by division (except the reference concentration value) can be expressed as:

In practical applications, the discrete concentration value can be used as the diffusion concentration distribution and substituted into the relationship between the diffusion concentration distribution and the distance index determined in step S2, so that the discrete distance corresponding to the discrete concentration value can be calculated.

For the discrete distance corresponding to each discrete concentration value, a sub-diffusion model of the discrete distance can be generated. Specifically, in one embodiment, multiple reference points may be randomly selected on the surface of the process structure shape. These reference points can be distributed as evenly as possible on the surface of the technological structure shape. Wherein, the number of reference points may be set according to actual requirements. If the modeling accuracy is high, the number of reference points can be appropriately increased; if the modeling speed is high, the number of reference points can be appropriately reduced.

Please refer to Fig. 4, taking the cuboid as an example, after the reference point is selected on the surface of the process structure shape, the reference point is used as the center of the sphere, the discrete distance is used as the radius, and the surface of the process structure shape is used as the diameter surface to generate The reference point corresponds to the hemisphere. In this way, each reference point can correspond to a hemisphere, which can represent the diffusion trajectory under the ion implantation process or deposition process. By taking the union of the hemispheres corresponding to each reference point, the sub-diffusion model of the current discrete distance can be obtained.

According to the above method, each discrete distance can correspond to its own sub-diffusion model, and finally the combination of each sub-diffusion model can be used as the diffusion model corresponding to the shape of the process structure.

Each mask plate includes one or more process structure shapes, and the combination of the diffusion models corresponding to the multiple process structure shapes obtained in the above manner can be used as a part of the three-dimensional chip to be modeled based on the mask plate of this layer modeling results.

According to the above method, three-dimensional modeling is carried out according to the masks of each layer of the chip to be modeled, and finally the overall three-dimensional model of the chip to be modeled can be obtained.

In one embodiment, in order to speed up the modeling speed of the three-dimensional model, when generating the sub-diffusion models of each discrete distance, the selection of reference points may also be limited. Specifically, a plurality of first reference points may be selected on the surface of the process structure shape, these first reference points may not be located on the vertices and edges of the process structure shape, and then may be located on the vertices and edges of the process structure shape Select multiple second reference points on . These two different types of reference points can be handled in different ways. Specifically, for the first reference point, with the first reference point as the end point, the discrete distance as the length, and the surface of the process structure shape as the vertical plane, a vertical line segment corresponding to the first reference point is formed , and one or more triangular surfaces are formed according to the endpoints of each of the vertical line segments away from the shape of the technological structure. For example, among the endpoints of the shape far away from the process structure, three adjacent endpoints may be used as the three vertices of the triangular surface. In this way, every three endpoints can form a triangular face. For the second reference point, according to the above-mentioned process of drawing a hemisphere, the second reference point can be used as the center of the sphere, the discrete distance can be used as the radius, and the surface of the process structure shape can be used as the diameter surface to generate the second reference point. Two reference points correspond to the hemisphere. In this way, the first reference point can finally get the corresponding multiple triangular faces, and the second reference point can get the corresponding multiple hemispheres, and the union of these triangular faces and hemispheres can be used as the sub-diffusion corresponding to the current discrete distance Model. Similarly, each discrete distance can correspond to its own sub-diffusion model, and the combination of these sub-diffusion models can be used as the diffusion model corresponding to the shape of the process structure.

It should be noted that when performing three-dimensional modeling on the ion implantation process and the deposition process, the specific values of the independent variables are just examples, and it does not mean that the modeling must be carried out according to the above specific values. Although the modeling methods for the implanted or deposited materials corresponding to each layer of masks in the semiconductor substrate material or surface are the same, but because the specific structures formed by different masks are different, the values of the respective independent variables It may also be different. In practical applications, it is necessary to assign values to independent variables according to the specific structure, so as to carry out reasonable calculation and modeling process.

In this application, three-dimensional modeling is carried out for each mask plate in the layout of the chip to be modeled. After obtaining the three-dimensional model of the chip to be modeled, the research and development personnel can place the mouse on any position of the three-dimensional model, After using the mouse to slide and cut the current position, you can see the XY plane section, XZ plane section and YZ plane section at this position, so as to facilitate the comprehensive inspection and verification of each part of the chip.

In this application, the display mode of the three-dimensional solid model can also be more flexible. For example, the mask plate of any layer can be closed in the EDA software, so that only the injection material/deposit corresponding to a certain layer or several layers of mask plates can be displayed. 3D solid models of bulk materials and semiconductor substrate materials. In addition, it can also display the three-dimensional model of one or several specific concentrations of injected materials/deposited materials. This model viewing method allows developers to quickly view each layer of the model and improve inspection efficiency.

After adopting this application, the R&D personnel can complete the three-dimensional modeling in the EDA software, and the model can completely display the positional relationship of each part of the chip after ion implantation and deposition, and the R&D personnel only need to check each part. It can be known whether the chip design conforms to the rules, and whether there will be failures such as ion implantation or deposition that cause adjacent parts to be connected due to diffusion and other reasons during the manufacturing process, thereby improving the yield.

It can be seen that in the technical solution provided by this application, for the mask plate in the layout of the chip to be modeled, the appropriate concentration calculation method can be selected according to the actual process steps of the mask plate to determine the corresponding injection of the mask plate. Or the relationship between the diffusion concentration distribution of the deposited material in the semiconductor substrate material or the surface and the distance index. Subsequently, in combination with the shape of the process structure on the mask and the above-mentioned correlation, a diffusion model corresponding to the shape of the process structure can be established. The combination of the diffusion model and the shape of the process structure can be used as the modeling result of the chip to be modeled. It can be seen that the present application considers the actual diffusion concentration distribution in or on the surface of the semiconductor substrate material when modeling the chip to be modeled, and the diffusion model determined based on the diffusion concentration distribution can be consistent with the actual process steps, thereby establishing A more accurate chip model is produced.

An embodiment of the present application also provides a system for building a chip model from a chip layout, the system comprising:

A process step identification unit, configured to determine the mask plate in the layout of the chip to be modeled, and identify the current process step of the mask plate;

The correlation determination unit is used to determine the concentration distribution and distance index of the implanted or deposited material corresponding to the mask plate in the semiconductor substrate material or on the surface by using a concentration calculation method suitable for the process steps. connection relation;

a modeling unit, configured to identify the shape of the process structure on the mask, and based on the association, establish a diffusion model corresponding to the shape of the process structure, and combine the diffusion model with the shape of the process structure As the modeling result of the chip to be modeled.

An embodiment of the present application also provides a device for establishing a chip model from a chip layout, the device includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, the above-mentioned A method for building a chip model from a chip layout.

Wherein, the processor may be a central processing unit (Central Processing Unit, CPU). The processor can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application-specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate array (Field-Programmable Gate Array, FPGA) or other Chips such as programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above-mentioned types of chips.

As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions/modules corresponding to the methods in the embodiments of the present application. The processor executes various functional applications and data processing of the processor by running non-transitory software programs, instructions, and modules stored in the memory, that is, implements the methods in the above method implementation manners.

The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created by the processor, and the like. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include memory located remotely from the processor, and such remote memory may be connected to the processor via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

An embodiment of the present application also provides a non-volatile computer storage medium, the computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by an electronic device, the electronic device realizes the above slave chip layout Method for building chip models.

FIG. 5 is a schematic diagram of the hardware structure of an electronic device that executes the method for establishing a chip model from a chip layout provided by an embodiment of the present application. As shown in FIG. 5 , the device includes: one or more processors 510 and a memory 520. In FIG. Take a processor 510 as an example; the device for executing the method for establishing a chip model from a chip layout may further include: an input device 530 and an output device 540 .

The processor 510, the memory 520, the input device 530, and the output device 540 may be connected via a bus or in other ways, and connection via a bus is taken as an example in FIG. 5 .

The memory 520, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs and modules, such as the method of establishing a chip model from a chip layout in an embodiment of the present application. The program instruction/module to which the method corresponds. The processor 510 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 520, that is, implements the method of establishing a chip model from the chip layout in the above method embodiment.

The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; data etc. In addition, the memory 520 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices. In some implementations, the memory 520 may optionally include memory located remotely relative to the processor 510, and these remote memories may be connected to the device for building a chip model from a chip layout through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 530 can receive input numbers or character information, and generate key signal inputs related to user settings and function control of the device for building a chip model from a chip layout. The output device 540 may include a display device such as a display screen.

The one or more modules are stored in the memory 520, and when executed by the one or more processors 510, execute the method for establishing a chip model from a chip layout in any method implementation above.

The above-mentioned products can execute the methods provided in the embodiments of the present application, and have corresponding functional modules and beneficial effects for executing the methods. For technical details that are not exhaustively described in this implementation manner, refer to the method provided in the implementation manner of this application.

Electronic devices in the embodiments of the present application exist in various forms, including but not limited to:

(1) Mobile communication equipment: This type of equipment is characterized by mobile communication functions, and its main goal is to provide voice and data communication. Such terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.

(2) Ultra-mobile personal computer equipment: This type of equipment belongs to the category of personal computers, has computing and processing functions, and generally has the characteristics of mobile Internet access. Such terminals include: PDA, MID and UMPC equipment, such as iPad.

(3) Portable entertainment equipment: This type of equipment can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

(4) Server: A device that provides computing services. The composition of a server includes a processor, hard disk, memory, system bus, etc. The server is similar to a general-purpose computer architecture, but due to the need to provide high-reliability services, it is important in terms of processing power and stability. , Reliability, security, scalability, manageability and other aspects have high requirements.

(5) Other electronic devices with data interaction function.

The device implementations described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solutions or the part that contributes to related technologies can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, disk , CD, etc., including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute the method described in each embodiment or some parts of the embodiment.

An embodiment of the present application further provides a computer program, which, when executed by a processor, implements the above-mentioned method for establishing a chip model from a chip layout.

Those skilled in the art can understand that all or part of the process in the method of the above-mentioned embodiment can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. During execution, it may include the procedures of the implementation manners of the above-mentioned methods. Wherein, the storage medium can be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a flash memory (Flash Memory), a hard disk (Hard Disk) Disk Drive, abbreviation: HDD) or solid-state hard drive (Solid-State Drive, SSD) etc.; The storage medium can also include the combination of above-mentioned types of memory.

Although the embodiment of the application has been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall into the scope of the appended claims. within the limited range.

Claims (12)

1. A method for establishing a chip model from a chip layout, characterized in that the method comprises:

   Determining the mask plate in the layout of the chip to be modeled, and identifying the current process step of the mask plate; the process step includes an ion implantation process or a deposition process;

   Using a concentration calculation method adapted to the process steps, determine the relationship between the diffusion concentration distribution of the ion implantation material corresponding to the mask in the semiconductor substrate material and the distance index, and determine the corresponding The relationship between the diffusion concentration distribution of the deposited material on the surface of the semiconductor substrate material and the distance index;

   Identify the shape of the process structure on the mask, and based on the association, establish a diffusion model corresponding to the shape of the process structure, and use the combination of the diffusion model and the shape of the process structure as the to-be-modeled Chip modeling results.
2. The method according to claim 1, wherein determining the mask plate in the layout of the chip to be modeled comprises:

   Identify the type of each component in the chip to be modeled, obtain a sub-mask matching the each component according to the type of each component, and obtain a sub-mask matching the each component After the layout of the chip to be modeled is formed by combination, a multi-layer mask is automatically generated, and the automatically generated multi-layer mask is used as a determined mask.
3. The method according to claim 1, wherein identifying the current process step of the mask comprises:

   Name the mask according to the function realized by the mask, and use the process step corresponding to the name of the mask as the current process step of the mask; wherein, the process step have a corresponding number.
4. The method according to claim 1, wherein determining the relationship between the diffusion concentration distribution and the distance index of the ion implantation material corresponding to the mask plate in the semiconductor substrate material comprises:

   calculating a first ion concentration distribution generated during ion implantation in the semiconductor substrate material;

   During annealing after ion implantation, calculating a second ion concentration distribution based on a diffusion effect in the semiconductor substrate material; wherein, the second ion concentration distribution has a corresponding relationship with a diffusion coefficient and an annealing time;

   According to the first ion concentration distribution and the second ion concentration distribution, generate the correlation relationship between the diffusion concentration distribution in the semiconductor substrate material and the distance index; wherein, the distance index represents the distance between the ion implantation center position and distance.
5. The method according to claim 4, wherein the first ion concentration distribution is represented by the following formula:

   

   The second ion concentration distribution is expressed by the following formula:

   

   The relationship between the diffusion concentration distribution and the distance index is expressed by the following formula:

   

   Wherein, C ₁ (x) represents the first ion concentration distribution, C ₂ (x) represents the second ion concentration distribution, C(x,t) represents the relationship between the diffusion concentration distribution and the distance index, x represents the distance index, t represents the annealing time, D represents the diffusion coefficient, Q represents the ion implantation dose, R _p represents the average projected range, and ΔR _p represents the standard deviation of the average projected range.
6. The method according to claim 1, wherein determining the relationship between the diffusion concentration distribution and the distance index of the deposition material corresponding to the mask plate on the surface of the semiconductor substrate material comprises:

   Calculating the out-diffusion concentration distribution and the self-diffusion concentration distribution on the surface of the semiconductor substrate material respectively;

   According to the out-diffusion concentration distribution and the self-diffusion concentration distribution, the relationship between the diffusion concentration distribution and the distance index after deposition on the surface of the semiconductor substrate material is generated; distance from the substrate surface.
7. The method according to claim 6, wherein the outer diffusion concentration distribution is expressed by the following formula:

   

   The self-diffusion concentration distribution is expressed by the following formula:

   

   The relationship between the diffusion concentration distribution and the distance index after the deposition is expressed by the following formula:

   

   Wherein, C _e (x, t ₁ ) represents the outer diffusion concentration distribution, C _z represents the self-diffusion concentration distribution, C (x, t ₁ ) represents the relationship between the diffusion concentration distribution after deposition and the distance index, erfc represents the complementary error function, x represents the distance index, t ₁ represents the deposition time, C represents the substrate concentration, D ₁ represents the diffusion coefficient during deposition, C _s represents the effective substrate surface concentration, L represents the diffusion length, C( back) represents the concentration constant resulting from back self-diffusion.
8. The method according to claim 1, wherein establishing a diffusion model corresponding to the shape of the process structure comprises:

   determining a reference concentration value in the shape of the process structure based on the association relationship;

   Dividing the reference concentration value into a plurality of discrete concentration values, and based on the association relationship, respectively calculating the discrete distance corresponding to each of the discrete concentration values;

   Sub-diffusion models of each of the discrete distances are generated, and a combination of the sub-diffusion models is used as a diffusion model corresponding to the shape of the process structure.
9. The method according to claim 8, wherein generating the sub-diffusion models of each of the discrete distances comprises:

   Select a plurality of reference points on the surface of the process structure shape, and use the reference points as the center of the sphere, use the discrete distance as the radius, and use the surface of the process structure shape as a diameter surface to generate the reference points the corresponding hemisphere;

   The union of the hemispheres corresponding to each of the reference points is used as the sub-diffusion model of the discrete distance.
10. The method according to claim 8, wherein generating the sub-diffusion models of each of the discrete distances comprises:

    selecting a plurality of first reference points on the surface of the process structure shape, and selecting a plurality of second reference points on the vertices and edges of the process structure shape;

    Taking the first reference point as an end point, taking the discrete distance as a length, and taking the surface of the process structure shape as a vertical plane, forming a vertical line segment corresponding to the first reference point, and according to each of the vertical line segments The endpoints of the shapes far away from the technological structure form one or more triangular surfaces;

    Using the second reference point as the center of the sphere, using the discrete distance as the radius, and using the surface of the process structure shape as a diameter surface, generate a hemisphere corresponding to the second reference point;

    A union of hemispheres corresponding to each of the triangular faces and each of the second reference points is used as a sub-diffusion model of the discrete distance.
11. A device for establishing a chip model from a chip layout, characterized in that the device includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, the above claim 1 is realized - the method described in any one of 10.
12. A non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions cause the electronic equipment to implement A method as claimed in any one of the preceding claims 1-10.

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