JP2024515633A - METALIZED SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - Patent application - Google Patents

METALIZED SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - Patent application Download PDF

Info

Publication number
JP2024515633A
JP2024515633A JP2023563004A JP2023563004A JP2024515633A JP 2024515633 A JP2024515633 A JP 2024515633A JP 2023563004 A JP2023563004 A JP 2023563004A JP 2023563004 A JP2023563004 A JP 2023563004A JP 2024515633 A JP2024515633 A JP 2024515633A
Authority
JP
Japan
Prior art keywords
die
metallization
contact
metal cap
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023563004A
Other languages
Japanese (ja)
Inventor
メヘルダード シェイガンプアー，
ギュンター アフレンツァー，
ダフォーア トマシェヴィッチ，
トーマス フェイシティンガー，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
TDK Electronics AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Electronics AG filed Critical TDK Electronics AG
Publication of JP2024515633A publication Critical patent/JP2024515633A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
    • H01C17/281—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thick film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • H01G13/006—Apparatus or processes for applying terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/148—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals embracing or surrounding the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H01L2224/03422—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05199—Material of the matrix
    • H01L2224/0529—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05698—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05798—Fillers
    • H01L2224/05799—Base material
    • H01L2224/058—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05801—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05811—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本発明は、半導体ダイ（２）であって、半導体材料を含むベース本体（２０）と、ダイ（２）を電気的に接触させることができる接触パッド（６）が設けられた２つの接触領域（４）を有する表面と、接触パッド（６）に直接適用される２つの金属キャップ（１１）とを備える、半導体ダイ（２）を構成する。【選択図】図３The present invention constitutes a semiconductor die (2) comprising a base body (20) containing a semiconductor material, a surface having two contact areas (4) provided with contact pads (6) by which the die (2) can be electrically contacted, and two metal caps (11) applied directly to the contact pads (6). [Selected Figure]

Description

本発明は、金属化半導体ダイ、並びに半導体ダイを製造及び金属化する方法に関する。 The present invention relates to metallized semiconductor dies and methods for manufacturing and metallizing semiconductor dies.

消費者電子デバイスにおいて、ＥＳＤ（静電放電）保護は、過酷な過渡環境における堅牢性を確保するために不可欠となる。表面実装型デバイス（ＳＭＤ）又はチップサイズパッケージ（ＣＳＰ）デバイスとして製造される過渡電圧抑制（ＴＶＳ）ダイオードは、システムレベルで電子デバイスを保護する広範囲に及ぶ。将来のデバイスの小型化目標を達成するために、ウェハレベルチップスケールパッケージング（ＷＬＣＳＰ）技術によって製造されるＣＳＰデバイスは、半導体部品の小型化のために益々使用されている。 In consumer electronic devices, ESD (electrostatic discharge) protection is essential to ensure robustness in harsh transient environments. Transient voltage suppression (TVS) diodes, fabricated as surface mounted devices (SMD) or chip size package (CSP) devices, are widely used to protect electronic devices at the system level. To meet future device miniaturization goals, CSP devices fabricated by wafer level chip scale packaging (WLCSP) technology are increasingly being used to miniaturize semiconductor components.

最先端の半導体ダイは、幾つかのステップで異なるパッシベーション層及び接触領域を伴って製造される。 State-of-the-art semiconductor dies are manufactured with different passivation layers and contact areas in several steps.

独国特許第１０２００５００４１６０号明細書は、パッシベーション層と、電気接触領域と、電気接触領域に適用される接触パッドとを備える、ＷＬＣＳＰ技術によって製造される半導体素子を開示する。 DE 102005004160 discloses a semiconductor element manufactured by WLCSP technology, comprising a passivation layer, electrical contact areas and contact pads applied to the electrical contact areas.

米国特許出願公開第２０１４／２６４８８号明細書は、ダイを個片化した後に不動態化ステップによるウェハからの半導体ダイの製造を記載する。各半導体ダイの表面に２つの接触パッドが形成され、その後、半導体ダイがウェハから個片化される。パッシベーション層が、個片化されたダイに適用されるが、接触パッドを覆わない。 U.S. Patent Application Publication No. 2014/26488 describes the manufacture of semiconductor dies from a wafer with a passivation step after singulating the dies. Two contact pads are formed on the surface of each semiconductor die, and then the semiconductor dies are singulated from the wafer. A passivation layer is applied to the singulated dies but does not cover the contact pads.

米国特許出願公開第２０１２／１０４４１４号明細書は、ウェハから半導体ダイを製造する他の方法を記載する。各半導体ダイの一方の表面に２つの接触パッドが適用され、ウェハの反対側の表面にパッシベーション層が形成される。その後、ダイがウェハから分離される。 U.S. Patent Application Publication No. 2012/104414 describes another method of manufacturing semiconductor dies from a wafer. Two contact pads are applied to one surface of each semiconductor die, and a passivation layer is formed on the opposing surface of the wafer. The dies are then separated from the wafer.

国際特許出願公開第２０１８／１５１４０５号明細書は、半導体チップが絶縁体に埋め込まれるチップパッケージについて記載する。 WO 2018/151405 describes a chip package in which a semiconductor chip is embedded in an insulator.

独国特許出願公開第１０２０１１０５６５１５号明細書は、外部接触パッド及び金属キャップが適用される、内部電極を有する不動態化セラミック又は半導体本体に基づく電気ＳＭＤ部品を開示する。 DE 10 2011 056 515 A1 discloses an electrical SMD component based on a passivated ceramic or semiconductor body with internal electrodes to which external contact pads and a metal cap are applied.

特開２０１２－４４８０号公報は、多層セラミック本体に外部メタライゼーションを適用し、その後にメタライゼーション層を硬化させるためのプロセスに関する。特に、金属ペーストが、セラミック本体の側面にスクリーン印刷によって塗布され、その後、硬化のために乾燥され、高温で焼結される。 JP 2012-4480 A relates to a process for applying external metallization to a multilayer ceramic body and subsequently curing the metallization layer. In particular, a metal paste is applied by screen printing to the sides of the ceramic body, and then dried and sintered at high temperature for curing.

特開２００２－１８４６４５号公報は、チップの端部が銀の導体ペースト中に浸漬されてコーティング膜を形成し、このコーティング膜が乾燥された後に６００℃以上で焼結される、端子電極の製造方法に関する。その後、ニッケル又はスズコーティングが塗布される。 JP 2002-184645 A relates to a method for manufacturing terminal electrodes in which the end of a chip is immersed in a silver conductor paste to form a coating film, which is dried and then sintered at 600°C or higher. A nickel or tin coating is then applied.

最新技術の方法の欠点に鑑みて、本発明の目的は、改良された半導体ダイ及び半導体ダイの製造方法を開示することである。 In view of the shortcomings of state of the art methods, it is an object of the present invention to disclose an improved semiconductor die and method for manufacturing the semiconductor die.

この目的は、開示された半導体ダイ及び製造方法によって少なくとも部分的に解決される。 This objective is at least partially achieved by the disclosed semiconductor die and manufacturing method.

半導体ダイは、半導体材料を含むベース本体と、ダイを電気的に接触させることができる接触パッドが設けられた２つの接触領域を有する表面と、接触パッドに直接適用される２つの金属キャップとを備える。 The semiconductor die comprises a base body containing a semiconductor material, a surface having two contact areas with contact pads to which the die can be electrically contacted, and two metal caps applied directly to the contact pads.

ダイのベース本体は半導体材料を含む。ベース本体は主に半導体材料からなることができる。半導体材料は、シリコン（Ｓｉ）材料を含んでもよい。半導体材料をベースとするダイは、ＥＳＤ保護用途のためのＴＶＳダイオードとして使用することができる。更なる実施形態において、ダイは、異なる用途のための微小電気機械システム（ＭＥＭＳ）デバイスとして使用されてもよい。これに代えて又は加えて、ダイは鉱物材料を含んでもよい。鉱物材料がセラミックを含んでもよい。ダイは、コンデンサ、バリスタ又はサーミスタとして使用されてもよい。 The base body of the die comprises a semiconductor material. The base body can consist primarily of the semiconductor material. The semiconductor material may comprise a silicon (Si) material. The die based on the semiconductor material can be used as a TVS diode for ESD protection applications. In further embodiments, the die may be used as a microelectromechanical system (MEMS) device for different applications. Alternatively or additionally, the die may comprise a mineral material. The mineral material may comprise a ceramic. The die may be used as a capacitor, a varistor or a thermistor.

金属キャップを接触パッドに適用することには幾つかの利点がある。 Applying metal caps to contact pads has several advantages:

第１に、ダイは、接触パッドよりもかなり大きな外面を有する金属キャップによって外部から電気的に接触され得る。パッシベーション層により、金属キャップとダイの接触パッド以外の領域との間の電流の発生を防止することができる。 First, the die can be electrically contacted from the outside by a metal cap that has an outer surface significantly larger than the contact pads. A passivation layer can prevent the generation of electrical currents between the metal cap and areas of the die other than the contact pads.

更に、接触パッドの寸法を縮小することさえ可能である。接触パッドが小さいほど、接触パッド間の距離を大きくすることができる。接触パッド間の距離が長くなると、リーク電流や寄生容量などの望ましくない影響が低減される。 It is even possible to reduce the dimensions of the contact pads: the smaller the contact pads, the greater the distance between them can be. A greater distance between contact pads reduces undesirable effects such as leakage currents and parasitic capacitance.

更に、金属キャップの大きな外表面積に起因して、ＰＣＢ（プリント回路基板）などの他のデバイス上でのダイの組み立てプロセスが単純化される。記載された金属キャップは、好ましくは優れたはんだぬれ特性を示す。 Furthermore, due to the large external surface area of the metal cap, the assembly process of the die on other devices, such as a PCB (printed circuit board), is simplified. The described metal cap preferably exhibits excellent solder wetting properties.

金属キャップによって与えられるダイの更なる金属化は、それらの安定性、特にダイ全体の曲げ強度及びせん断強度を更に高める。 The additional metallization of the dies provided by the metal caps further increases their stability, particularly the bending and shear strength of the entire die.

要約すると、ＴＶＳダイオードなどのダイの電気接触領域に金属キャップを適用することによって、ダイの電気特性を改善することができ、ＰＣＢ上のダイの組み立てプロセスが単純化され、ダイと外部デバイスとの間の安定した安全な電気接触が達成され得る。 In summary, by applying a metal cap to the electrical contact area of a die such as a TVS diode, the electrical properties of the die can be improved, the assembly process of the die on the PCB can be simplified, and stable and secure electrical contact between the die and external devices can be achieved.

ダイは、６つの長方形の側面を伴う直方体形状を有することができる。 The die may have a rectangular shape with six rectangular sides.

好ましくは、ベース本体は、モノリシックであり、更なる構成要素又は構造要素を備えない。 Preferably, the base body is monolithic and does not include any further components or structural elements.

一実施形態において、半導体ダイは、接触領域を接触パッドと接続する２つの中間層を更に備える。 In one embodiment, the semiconductor die further comprises two intermediate layers connecting the contact regions with the contact pads.

接触領域、任意選択的な中間層、及び接触パッドはそれぞれ、導電性材料を含む。好ましくは、接触領域、任意選択的な中間層、及び接触パッドは導電性金属又は金属の混合物を含む。記載された３つの構造要素のそれぞれの材料の組成は、互いに異なる。例えば、接触領域は、アルミニウム又は銅から選択される材料を含み、接触パッドは、銅、ニッケル又は金から選択される材料を含む。 The contact area, the optional intermediate layer, and the contact pad each comprise a conductive material. Preferably, the contact area, the optional intermediate layer, and the contact pad comprise a conductive metal or mixture of metals. The material composition of each of the three described structural elements differs from each other. For example, the contact area comprises a material selected from aluminum or copper, and the contact pad comprises a material selected from copper, nickel, or gold.

接触領域はベース本体の半導体材料に電気的に接触するように構成されるが、接触パッドは外部電気接点に接触するように構成される。中間層は、接触領域と接触パッドとを電気的及び機械的に接続するように構成される。中間層により、接触パッドと接触領域との間の接続を最適化することができる。 The contact regions are configured to electrically contact the semiconductor material of the base body, while the contact pads are configured to contact external electrical contacts. The intermediate layer is configured to electrically and mechanically connect the contact regions and the contact pads. The intermediate layer allows for optimizing the connection between the contact pads and the contact regions.

更に、幾つかのステップを含む半導体ダイを製造及び金属化する方法が開示される。以下のステップの番号付けは、ステップが実行される順序を規定しない。各ステップは、番号順に実行されてもよい。 Furthermore, a method of fabricating and metallizing a semiconductor die is disclosed that includes several steps. The numbering of the steps below does not dictate the order in which the steps are performed. Each step may be performed in numerical order.

前述した半導体ダイのあらゆる特徴は、以下の方法で製造される半導体ダイに適用することができる。一方、以下の方法で製造される半導体ダイのあらゆる特徴は、前述した半導体ダイにも適用することができる。 All features of the semiconductor die described above may be applied to the semiconductor die manufactured by the method below. Conversely, all features of the semiconductor die manufactured by the method below may be applied to the semiconductor die described above.

第１のステップにおいて、半導体材料を含むベース本体と、ダイに電気的に接触するための２つの接触領域を有する表面とを備えるダイが用意される。ダイは、ダイオードとして、例えばＴＶＳダイオードとして機能するように構成されてもよい。 In a first step, a die is provided that comprises a base body containing a semiconductor material and a surface having two contact areas for electrically contacting the die. The die may be configured to function as a diode, for example as a TVS diode.

接触領域には、接触領域に適用される接触パッドが設けられる。接触パッドは、外部接点とダイの接触領域又は任意選択的な中間層との間の電気接触要素として機能する。外部接点は、例えば、プリント回路基板（ＰＣＢ）上の電気接点である。 The contact areas are provided with contact pads that are applied to the contact areas. The contact pads serve as electrical contact elements between the external contacts and the contact areas of the die or optional intermediate layers. The external contacts are, for example, electrical contacts on a printed circuit board (PCB).

第２のステップでは、電気的不動態化のためのパッシベーション層がダイの表面に適用される。パッシベーション層は、非不動態化領域を除いて、ダイの表面全体を覆ってもよい。それにより、各接触パッドへの外部アクセスを可能にする、パッシベーションのない領域、すなわち、前記非不動態化領域が設けられる。パッシベーション層は、ダイの表面を電気的に絶縁する。更に、パッシベーション層は、環境への影響又は物理的及び化学的反応からダイを保護する。好ましくは、接触パッドを除くダイの表面全体又は各接触パッドの少なくとも一部が不動態化される。 In a second step, a passivation layer for electrical passivation is applied to the surface of the die. The passivation layer may cover the entire surface of the die, except for the non-passivated areas, thereby providing areas without passivation, i.e. the non-passivated areas, that allow external access to each contact pad. The passivation layer electrically insulates the surface of the die. Furthermore, the passivation layer protects the die from environmental influences or physical and chemical reactions. Preferably, the entire surface of the die, except for the contact pads, or at least a part of each contact pad, is passivated.

好ましい実施形態において、パッシベーション層は、ＡＬＤ（原子層堆積）プロセス又はＣＶＤ（化学気相堆積）プロセスによって適用されてもよい。不動態化されないようになっている領域（非不動態化領域）は、不動態化プロセス中に保護テープで覆われ得る。 In a preferred embodiment, the passivation layer may be applied by an ALD (atomic layer deposition) process or a CVD (chemical vapor deposition) process. Areas that are not to be passivated (non-passivated areas) may be covered with a protective tape during the passivation process.

第３のステップでは、ダイの表面の一部がメタライゼーションプロセスによって金属キャップで覆われる。金属キャップは接触パッドに直接接触する。 In the third step, a portion of the die's surface is covered with a metal cap through a metallization process. The metal cap makes direct contact with the contact pads.

好ましい実施形態では、ステップが記載された順序で実行される。 In a preferred embodiment, the steps are performed in the order listed.

一実施形態において、ダイの前面は、ダイの第１の側面の近くに配置された少なくとも第１の接触領域と、ダイの第２の側面の近くに配置された第２の接触領域とを備える。好ましい実施形態では、第２の側面が第１の側面の反対側に配置され、第１の側面及び第２の側面が前面に対して垂直である。 In one embodiment, the front surface of the die comprises at least a first contact area disposed near a first side of the die and a second contact area disposed near a second side of the die. In a preferred embodiment, the second side is disposed opposite the first side, and the first and second sides are perpendicular to the front surface.

ダイは、６つの長方形の側面を伴う直方体形状を有することができる。 The die may have a rectangular shape with six rectangular sides.

記載された形状は、例えばＰＣＢ上にダイを組み立てるのに有利である。 The described shapes are advantageous for assembling the die onto a PCB, for example.

一実施形態において、金属化するステップは、幾つかの更なるステップを含むことができる。 In one embodiment, the metallizing step may include several further steps.

第１の更なるステップにおいて、ダイは、第１の面で第１のメタライゼーションテープに装填される。メタライゼーションテープは、接着層を伴うポリマーテープであってもよい。接着層は、熱剥離性を有していてもよい。このことは、所定の温度に加熱することによってテープをダイから剥離できることを意味する。メタライゼーションテープは、ダイを支持し、第１のメタライゼーションステップ中に第１の側面を保護する。 In a first further step, the die is loaded on a first side into a first metallization tape. The metallization tape may be a polymer tape with an adhesive layer. The adhesive layer may be thermally releasable, meaning that the tape can be peeled off from the die by heating to a predefined temperature. The metallization tape supports the die and protects the first side during the first metallization step.

次のステップでは、少なくとも１つの接触パッドを含む、第１のメタライゼーションテープによって覆われないダイの連続領域が金属化される。 In the next step, the continuous areas of the die not covered by the first metallization tape, including at least one contact pad, are metallized.

好ましくは、ダイの前面の領域が金属化される。更に、第２の側面及び第２の側面に隣接する他の側面の部分が金属化されてもよい。 Preferably, an area on the front surface of the die is metallized. Additionally, portions of the second side and other sides adjacent to the second side may be metallized.

その後、第１の側面が第１のメタライゼーションテープから解放される。 The first side is then released from the first metallization tape.

一実施形態において、金属化するステップは、ダイを第１の側面で第１のメタライゼーションテープに装填するステップと、少なくとも１つの接触パッドを含む第１のメタライゼーションテープによって覆われないダイの連続領域を金属化するステップと、ダイを第２の側面で第２のメタライゼーションテープに装填するステップと、少なくとも１つの接触パッドを含む第２のメタライゼーションテープによって覆われないダイの連続領域を金属化するステップとを含む。 In one embodiment, the metallizing step includes loading the die on a first side into a first metallization tape, metallizing a continuous area of the die not covered by the first metallization tape including at least one contact pad, loading the die on a second side into a second metallization tape, and metallizing a continuous area of the die not covered by the second metallization tape including at least one contact pad.

好ましい実施形態において、金属化するステップは、ダイの第１の面を第１のメタライゼーションテープに装填し、ダイの前面及び第２の側面の連続領域を金属化し、第２の側面を第２のメタライゼーションテープに装填し、ダイの前面及び第１の側面の連続領域を金属化するステップを含むことができる。ここで、前記連続領域は、前面に第２の接触パッドを備える。第２の接触パッドはダイの第２の接触領域に接触する。 In a preferred embodiment, the metallizing step may include loading a first surface of the die onto a first metallization tape, metallizing a continuous area of the front and second side of the die, loading the second side onto a second metallization tape, and metallizing a continuous area of the front and first side of the die, wherein the continuous area comprises a second contact pad on the front surface. The second contact pad contacts the second contact area of the die.

２つの接触パッドを設けることにより、電気回路を設計することができる。更なる実施形態において、ダイオードは、接触パッドを有する幾つかの接触領域を備える。 By providing two contact pads, an electrical circuit can be designed. In a further embodiment, the diode comprises several contact areas with contact pads.

接触パッドは、銅、ニッケル又は金のような導電性金属を含む。 The contact pads comprise a conductive metal such as copper, nickel or gold.

一実施形態において、方法は、第１の金属化ステップの後にダイの第２の側面の金属キャップを硬化させ、第２の金属化ステップの後にダイの第１の側面の金属キャップを硬化させる更なるステップを含む。 In one embodiment, the method includes the further steps of hardening the metal cap on the second side of the die after the first metallization step, and hardening the metal cap on the first side of the die after the second metallization step.

硬化ステップは、例えばダイを特定の温度で特定の期間にわたって保持することによって、熱処理により実施されてもよい。 The hardening step may be performed by heat treatment, for example by holding the die at a particular temperature for a particular period of time.

一実施形態において、方法は、第１の金属化ステップの後に第１のメタライゼーションテープから第１の側面を解放し、第２の金属化ステップの後に第２のメタライゼーションテープから第２の側面を解放する更なるステップを含む。 In one embodiment, the method includes the further steps of releasing the first side from the first metallization tape after the first metallization step and releasing the second side from the second metallization tape after the second metallization step.

第１のメタライゼーションテープは、第２のメタライゼーションステップの前に解放される。したがって、第１のメタライゼーションテープは、第２のメタライゼーションテープとして使用することができる。両方のメタライゼーションテープは、熱剥離性接着層を備えることができ、したがって加熱によって剥離することができる。解放ステップは、前述の硬化ステップの後に実行されてもよい。 The first metallization tape is released before the second metallization step. Thus, the first metallization tape can be used as the second metallization tape. Both metallization tapes can be provided with a heat-releasable adhesive layer and can therefore be peeled off by heating. The release step may be performed after the aforementioned curing step.

好ましい実施形態において、接触パッドは、金属化後に金属キャップによって完全に覆われる。したがって、ダイは、信頼性が高く安全な態様で金属キャップを介して外部接触される。より正確には、金属キャップは、ダイを外部電気接点に電気的に接続するように構成される。 In a preferred embodiment, the contact pads are completely covered by a metal cap after metallization. Thus, the die is externally contacted through the metal cap in a reliable and safe manner. More precisely, the metal cap is configured to electrically connect the die to external electrical contacts.

一実施形態では、金属キャップがパッシベーション層に直接適用される。接触パッドとパッシベーション層との間に更なる層は存在しない。接触パッドの直接的な適用は、ダイに対するそれらの取り付けを改善する。 In one embodiment, the metal cap is applied directly to the passivation layer. There are no additional layers between the contact pads and the passivation layer. The direct application of the contact pads improves their attachment to the die.

一実施形態において、金属キャップは、前面に対して垂直な端面と、ダイの端面に隣接する４つの側面とに連続して適用される。 In one embodiment, the metal cap is applied continuously to the edge perpendicular to the front face and to the four side faces adjacent to the edge face of the die.

金属キャップが各ダイの幾つかの側面に適用されるため、ＴＶＳダイオードを配向要件なく更に組み立てることができる。 Because metal caps are applied to several sides of each die, the TVS diodes can be further assembled without orientation requirements.

一実施形態では、金属キャップが浸漬プロセスによって適用される。浸漬プロセスは、単純で同等の安価な方法でダイの金属化を可能にする。 In one embodiment, the metal cap is applied by an immersion process, which allows for metallization of the die in a simple and equally inexpensive manner.

一実施形態において、金属キャップは、２つ又は３つの金属化ステップによって、例えば２つ又は３つの浸漬ステップによって適用される２つ又は３つの異なる層を含む。メタライゼーション層は、好ましくは、互いに積み重ねられる。 In one embodiment, the metal cap comprises two or three different layers applied by two or three metallization steps, for example by two or three immersion steps. The metallization layers are preferably stacked on top of each other.

接触パッド及び周囲のパッシベーション層に直接適用される第１の層は、Ａｇ又はＣｕとポリマーとを含む軟質メタライゼーション混合物を含んでもよい。第１の層の材料の軟質特性は、ダイとパッシベーション層との間又はパッシベーション層と金属キャップとの間の界面における亀裂の発生のような機械的又は熱機械的応力効果を低減又は防止する。 The first layer, which is applied directly to the contact pads and the surrounding passivation layer, may comprise a soft metallization mixture including Ag or Cu and a polymer. The soft nature of the first layer material reduces or prevents mechanical or thermomechanical stress effects such as the development of cracks at the interface between the die and the passivation layer or between the passivation layer and the metal cap.

第１の層に直接適用される第２の層は、ＣｕもしくはＮｉ又はＡｇ－Ｐｄ合金のような良好な導電体を含み、第１の層を環境への影響及び化学的又は物理的反応から保護する。 The second layer, applied directly to the first layer, contains a good electrical conductor such as Cu or Ni or an Ag-Pd alloy and protects the first layer from environmental influences and chemical or physical reactions.

第２の層上に直接適用される第３の層は、酸化保護層として構成され、Ａｕ又はＳｎのような適切な金属を含む。 The third layer, applied directly onto the second layer, is configured as an oxidation protection layer and comprises a suitable metal such as Au or Sn.

３つの層は全て導電性である。 All three layers are conductive.

一実施形態において、金属キャップは、例えばＮｉ及び／又はＣｕ及び／又はＡｕを含む接触パッドの金属又は金属の混合物とは異なる金属又は金属の混合物を含む。好ましい実施形態において、金属キャップの第１の層は、接触パッド以外の別の金属を含む。 In one embodiment, the metal cap comprises a metal or mixture of metals different from the metal or mixture of metals of the contact pad, e.g., Ni and/or Cu and/or Au. In a preferred embodiment, the first layer of the metal cap comprises another metal than the contact pad.

一実施形態において、パッシベーション層は、原子層堆積プロセスによって適用される。好ましくは、原子層堆積プロセスは、８０℃未満の温度で、より好ましくは室温で行なわれる。 In one embodiment, the passivation layer is applied by an atomic layer deposition process. Preferably, the atomic layer deposition process is carried out at a temperature below 80° C., more preferably at room temperature.

いわゆるＣＶＤ（化学気相堆積）プロセスにおいて、反応種は、制御された雰囲気及び高温下において気相中で反応して層を堆積させる。ＣＶＤプロセスは、通常、ガス雰囲気から堆積材料の層へ不純物を潜在的に導入し得る比較的高い温度で実行される。技術的には、ＣＶＤプロセスに必要なそのような高い堆積温度は、プロセスに関与するテープを含む材料の選択、したがって機能性を制限する。 In the so-called CVD (Chemical Vapor Deposition) process, reactive species react in the gas phase under controlled atmosphere and high temperature to deposit a layer. CVD processes are usually carried out at relatively high temperatures that can potentially introduce impurities from the gas atmosphere into the layer of deposited material. Technically, such high deposition temperatures required for CVD processes limit the choice of materials, including the tapes, involved in the process, and therefore the functionality.

一方、ＡＬＤプロセスは、高い均一性及び品質で低温領域に層を堆積することができるという主な利点を有する。一般に、ＣＶＤプロセスの変形としてのＡＬＤは、任意の標的基板上への単層の堆積を含む。堆積チャンバへのガス状前駆体の投入、ターゲットの表面とガス状前駆体との反応、及びチャンバを不活性ガスで洗浄して化学吸着されていない前駆体をパージすることを含むサイクルを体系的に繰り返すことによって、複数の単層を堆積させることができる。本方法では、導入されたテープと、パッシベーション層に求められる重要な特性（電気的、機械的等）に起因して必要とされる特定のパッシベーション材料とを考慮すると、ＡＬＤプロセスが好ましい。 On the other hand, the ALD process has the main advantage of being able to deposit layers in low temperature regions with high uniformity and quality. In general, ALD, as a variant of the CVD process, involves the deposition of monolayers on any target substrate. By systematically repeating a cycle that involves the introduction of gaseous precursors into the deposition chamber, the reaction of the gaseous precursors with the surface of the target, and purging the non-chemisorbed precursors by flushing the chamber with an inert gas, the ALD process is preferred in this method, taking into account the tape introduced and the specific passivation material required due to the important properties (electrical, mechanical, etc.) required for the passivation layer.

一実施形態において、ダイは、ウェハレベルチップスケールパッケージングプロセスによって製造される。 In one embodiment, the die is manufactured using a wafer-level chip-scale packaging process.

ウェハレベルチップスケールパッケージングプロセスでは、ウェハ、例えばシリコンウェハに含まれる複数のダイを並行して製造することができる。 In a wafer-level chip-scale packaging process, multiple dies contained on a wafer, e.g. a silicon wafer, can be manufactured in parallel.

ダイは、ダイ上に電気部品を組み立てた後にウェハから個片化されてもよい。 The dies may be singulated from the wafer after the electrical components are assembled on the die.

好ましくは、ダイは、研削（ＤＢＧ）プロセスの前にダイシングで個片化される。研削プロセス前のダイシングでは、まず、ウェハが、電気部品を保持するその前面側からダイへとハーフカットされる。ダイシングステップ後、ダイが依然としてそれらの背面で接続される。第２のステップでは、前面が保護テープによって覆われる。更なるステップにおいて、ダイは、背面からの研削によって完全に個片化される。ダイが個片化された後、保護テープを取り外すことができる。 Preferably, the dies are singulated by dicing before the grinding (DBG) process. In the dicing before grinding process, the wafer is first half-cut from its front side, which holds the electrical components, into dies. After the dicing step, the dies are still connected at their back side. In a second step, the front side is covered by a protective tape. In a further step, the dies are completely singulated by grinding from the back side. After the dies are singulated, the protective tape can be removed.

更なる不動態化ステップ及び金属化ステップを、単一のウェハから個片化された全てのダイに対して並行して同時に実行することができる。 Further passivation and metallization steps can be performed simultaneously in parallel on all die singulated from a single wafer.

したがって、ウェハレベルチップスケールパッケージプロセスは、記載された製造プロセスを簡略化して加速する。 Thus, the wafer-level chip-scale packaging process simplifies and accelerates the described manufacturing process.

以下、添付図面を参照して、本発明の実施形態をより詳細に説明する。図中の類似又は見かけ上同一の要素は、同じ参照符号で示される。図面及び図面の比率はスケーラブルではない。本発明は、以下の実施形態に限定されない。 Hereinafter, the embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Similar or apparently identical elements in the figures are indicated with the same reference numerals. The figures and the proportions of the figures are not to scale. The present invention is not limited to the following embodiments.

ウェハレベルチップスケールパッケージングプロセスにおけるＴＶＳダイオードの製造プロセスを概略的に示す。1 illustrates a schematic diagram of a manufacturing process of a TVS diode in a wafer level chip scale packaging process. ＴＶＳダイオードの第１の実施形態の断面図を示す。1 shows a cross-sectional view of a first embodiment of a TVS diode. ＴＶＳダイオードの第２の実施形態の断面図を示す。1 shows a cross-sectional view of a second embodiment of a TVS diode.

いわゆるバックエンドプロセスの第１のステップにおいて、ＴＶＳダイオード半導体ウェハ１が用意される。ウェハ１は、幾つかの直方体のＴＶＳダイオードダイ２に分離されるように構成される。ウェハは、シリコンベースの本体と、本体によって取り囲まれた又はいわゆるフロントエンドプロセスで本体の前面に適用された電気部品３とを備える。ＴＶＳダイオードウェハ１は、幾つかの直方体のＴＶＳダイオードダイ２へと後に分離される幾つかの同一のセクションを備える。ＴＶＳダイオード２は、半導体チップとして構成される。 In a first step of the so-called back-end process, a TVS diode semiconductor wafer 1 is prepared. The wafer 1 is configured to be separated into several cuboid TVS diode dies 2. The wafer comprises a silicon-based body and electrical components 3 surrounded by the body or applied to the front side of the body in a so-called front-end process. The TVS diode wafer 1 comprises several identical sections that are subsequently separated into several cuboid TVS diode dies 2. The TVS diodes 2 are configured as semiconductor chips.

第２のステップでは、ウェハ１の前面に金属層４がスパッタされる。金属層４は、少なくともチタン及び／又は銅を含む。前面として、電気部品３が適用されるウェハ１の側面が画定される。スパッタされた金属層４に基づいて、ＴＶＳダイオードを外部接点に電気的に接触させるための電気接触領域が設計される。 In a second step, a metal layer 4 is sputtered onto the front side of the wafer 1. The metal layer 4 comprises at least titanium and/or copper. As the front side, the side of the wafer 1 is defined, on which the electrical component 3 is applied. On the basis of the sputtered metal layer 4, electrical contact areas are designed for electrically contacting the TVS diode to external contacts.

第３のステップでは、フォトリソグラフィにより前面にマスク層５が適用される。マスク層５は、次のステップで接触パッド６が適用される接触領域の領域を除いて、前面の表面全体を覆う。 In a third step, a mask layer 5 is applied to the front surface by photolithography. The mask layer 5 covers the entire front surface except in the area of the contact regions where the contact pads 6 will be applied in the next step.

次のステップでは、電気めっきにより接触パッド６が接触領域上に適用される。電解めっきを行なった後、剥離プロセスによりマスク層５が除去される。 In a next step, contact pads 6 are applied onto the contact areas by electroplating. After electroplating, the mask layer 5 is removed by a stripping process.

前述のステップにより、外部電気接点用の接触パッド６を有するＴＶＳダイオードウェハ１が用意される。 The above steps prepare a TVS diode wafer 1 having contact pads 6 for external electrical contacts.

別の数のステップを含む以下の手順によって、ウェハ１が半導体ダイ２へと個片化され、ダイが電気的に不動態化される。 The following procedure, which includes another number of steps, singulates the wafer 1 into semiconductor dies 2 and electrically passivates the dies.

第１のステップでは、ウェハ１が前面からダイシングソーによりハーフカットダイに分割される。研削前（研削プロセス前のダイシング、ＤＢＧ）にダイシングが行なわれる。別のプロセスでは、ウェハ１が別の方法で分離されてもよい。 In a first step, the wafer 1 is separated into half-cut dies from the front side by a dicing saw. Dicing is performed before grinding (dicing before grinding process, DBG). In different processes the wafer 1 may be separated in different ways.

ハーフカットダイシングが行なわれた後、第２のステップにおいて、ウェハ１の前面が背面研削テープ７によって覆われる。背面研削テープ７は、研削中の損傷からウェハ１の前面及び適用された電気構造を保護する。第３のステップにおいて、ウェハ１は、前面の反対側であるウェハ１の背面から研削することによって直方体ダイへと完全に個片化される。 After the half-cut dicing is performed, in a second step, the front side of the wafer 1 is covered by a back grinding tape 7. The back grinding tape 7 protects the front side of the wafer 1 and the applied electrical structures from damage during grinding. In a third step, the wafer 1 is completely singulated into rectangular dies by grinding from the back side of the wafer 1, which is opposite to the front side.

別のプロセスでは、円筒形又は異なる形状のダイ２を製造することができる。 In another process, a cylindrical or differently shaped die 2 can be produced.

次のステップにおいて、転写テープ８が、研削されたダイ２の背面に積層される。転写テープ８は、背面研削テープ７からフィルムフレームキャリア９にダイ２を転写するために使用される。フィルムフレームキャリア９は、背面研削テープ７と同様のテープである。しかしながら、異なる接着層に起因して、フィルムフレームキャリア９は、個片化されたダイ２の前面全体を覆わない。背面研削テープ７とは対照的に、フィルムフレームキャリア９は、ダイ２の前面の接触パッド６の接触領域のみを覆う。ダイ２も支持するフィルムフレームキャリア９によって接触領域が覆われた後、転写テープ８が剥離される。 In the next step, a transfer tape 8 is laminated to the back side of the ground die 2. The transfer tape 8 is used to transfer the die 2 from the back side grinding tape 7 to a film frame carrier 9. The film frame carrier 9 is a similar tape to the back side grinding tape 7. However, due to the different adhesive layers, the film frame carrier 9 does not cover the entire front side of the singulated die 2. In contrast to the back side grinding tape 7, the film frame carrier 9 only covers the contact areas of the contact pads 6 on the front side of the die 2. After the contact areas are covered by the film frame carrier 9, which also supports the die 2, the transfer tape 8 is peeled off.

以下のプロセスでは、個片化されたダイ２の６つの側面の全てが、ＡＬＤ（原子層堆積）プロセスによって１つのステップで不動態化される。フィルムフレームキャリア９によって覆われた接触パッド６の接触領域のみが、ＡＬＤプロセス中に不動態化されない。ＡＬＤプロセスの利点は、プロセスが８０℃未満の低温、好ましくは室温で実施され得ることである。 In the following process, all six sides of the singulated die 2 are passivated in one step by an ALD (Atomic Layer Deposition) process. Only the contact areas of the contact pads 6 covered by the film frame carrier 9 are not passivated during the ALD process. The advantage of the ALD process is that it can be carried out at low temperatures below 80°C, preferably at room temperature.

不動態化プロセスが完了した後、ダイ２が熱剥離テープ１０によって支持され、フィルムフレームキャリア９が剥離される。側壁不動態化ＴＶＳダイオードは、所定の温度まで加熱することによって熱剥離テープ１０から剥離され得る。 After the passivation process is completed, the die 2 is supported by the thermal release tape 10 and the film frame carrier 9 is peeled off. The sidewall passivated TVS diode can be peeled off from the thermal release tape 10 by heating it to a predetermined temperature.

以下のステップは、金属キャップ１１を半導体ダイ２に適用する手順を説明する。各ダイ２は、その前面に接触領域を設ける２つの接触パッド６を備える６面不動態化直方体ＴＶＳダイオードとして構成される。 The following steps describe the procedure for applying the metal caps 11 to the semiconductor dies 2. Each die 2 is configured as a six-sided passivated rectangular TVS diode with two contact pads 6 providing contact areas on its front side.

一方の接触パッド６は、前面でダイ２の第１の側面の近くに配置され、他方の接触パッドは、前面でダイ２の第２の側面の近くに配置される。第１の側面及び第２の側面は、前面に対して垂直であり、互いに反対である。 One contact pad 6 is disposed near a first side of the die 2 on the front surface, and the other contact pad is disposed near a second side of the die 2 on the front surface. The first side and the second side are perpendicular to the front surface and opposite each other.

金属キャップ１１を適用するために、前面に対して垂直なダイ２の第１の側面が熱剥離テープ１０に装填される。幾つかのダイ２を同時に熱剥離テープ１０に装填することができる。例えば、単一のウェハ１から分離された全てのダイ２を同時に熱剥離テープ１０に装填することができる。 To apply the metal cap 11, a first side of the die 2 perpendicular to the front surface is loaded onto the thermal release tape 10. Several dies 2 can be loaded onto the thermal release tape 10 at the same time. For example, all dies 2 separated from a single wafer 1 can be loaded onto the thermal release tape 10 at the same time.

次に、全てのダイ２に同時に金属キャップ１１を適用するために、熱剥離テープ１０によってそれらの第１の側面で支持された半導体ダイ２が金属ペーストに浸漬される。 Next, the semiconductor dies 2 supported on their first sides by the thermal release tape 10 are dipped into the metal paste to apply the metal caps 11 to all the dies 2 simultaneously.

第１の浸漬ステップにおいてダイ２を金属ペーストに浸漬することにより、金属キャップ１１が、少なくとも第２の側面に、及び少なくとも第２の側面の近くの接触パッドを備える第２の側面に対して垂直なダイの側面の部分に適用される。浸漬によって塗布された金属キャップ１１は、高温で１０～６０分間乾燥される。 By dipping the die 2 in a metal paste in a first dipping step, a metal cap 11 is applied to at least the second side and to a portion of the side of the die perpendicular to the second side, including at least the contact pads near the second side. The metal cap 11 applied by dipping is dried at an elevated temperature for 10 to 60 minutes.

以下において、ダイ２は、ダイ２の第２の側面に貼り付けられた別の熱剥離テープ１０に転写され、ダイ２の第１の側面は、既に金属化された第２の側面とは反対側のダイ２の第１の側面を金属化するために、第２の浸漬ステップにおいて金属溶融物中に浸漬される。一実施形態では、同じ熱剥離テープ１０を両方の浸漬ステップで使用することができる。第１の側面を金属溶融物中に浸漬した後、金属キャップ１１は、少なくとも第１の側面と、これまで金属キャップ１１によって覆われていない、第１の側面の近くに少なくとも接触パッドを備える第１の側面に対して垂直な側面の部分とに適用される。浸漬によって塗布された金属キャップ１１は、第２の乾燥ステップで乾燥される。 In the following, the die 2 is transferred to another thermal release tape 10 applied to the second side of the die 2, and the first side of the die 2 is immersed in a metal melt in a second immersion step to metallize the first side of the die 2 opposite the already metallized second side. In one embodiment, the same thermal release tape 10 can be used in both immersion steps. After immersing the first side in the metal melt, a metal cap 11 is applied to at least the first side and to the part of the side perpendicular to the first side that is not covered by the metal cap 11 so far, comprising at least a contact pad near the first side. The metal cap 11 applied by immersion is dried in a second drying step.

両方の金属キャップ１１が乾燥された後、ダイ２は、温度を上昇させることによって熱剥離テープ１０から外される。金属キャップ１１は、以下の熱処理ステップによって硬化させることができる。 After both metal caps 11 are dried, the die 2 is released from the thermal release tape 10 by increasing the temperature. The metal caps 11 can be hardened by the following heat treatment steps.

金属キャップ１１は、導電性であり、接触パッド６の接触領域と直接接触している。 The metal cap 11 is conductive and is in direct contact with the contact area of the contact pad 6.

図２は、前述のプロセスによって製造された直方体のＴＶＳダイオードダイ２を示す。ＴＶＳダイオードダイ２の寸法は、長さ３００－１０００μｍ、幅１００－５００μｍ、高さ５０－２００μｍである。寸法は、好ましくは６００×３００×１５０μｍ又は４００×２００×１００μｍ（長さ×幅×高さ）である。 Figure 2 shows a rectangular TVS diode die 2 manufactured by the process described above. The dimensions of the TVS diode die 2 are 300-1000 μm long, 100-500 μm wide, and 50-200 μm high. The dimensions are preferably 600 x 300 x 150 μm or 400 x 200 x 100 μm (length x width x height).

ここで、長さは、第１の側面と第２の側面との間のＴＶＳダイオードダイの寸法である。幅は、第１の側面と前面との間又は第２の側面と前面との間の縁部の寸法である。高さは、前面に対して垂直な第１又は第２の側面の縁部の寸法である。 Here, length is the dimension of the TVS diode die between the first side and the second side. Width is the dimension of the edge between the first side and the front face or the second side and the front face. Height is the dimension of the edge of the first or second side perpendicular to the front face.

ＴＶＳダイオードダイ２は、好ましくはシリコン系材料及びシリコン系材料に埋め込まれた電気部品を備える半導体ベース本体２０を備える。シリコン系材料は、少なくともシリコン及び更なる任意選択的な要素を含む。 The TVS diode die 2 preferably comprises a semiconductor-based body 20 comprising a silicon-based material and electrical components embedded in the silicon-based material. The silicon-based material comprises at least silicon and further optional elements.

ベース本体２０は直方体状である。２つの接触パッド６は、ベース本体２０の前面に適用され、ベース本体２０に埋め込まれた電気部品に電気的に接触する。接触パッド６は、前面の２つの対向する縁部の近くに適用される。第１の接触パッド６Ａは、前側と第１の側面２Ａとの間の縁部付近に配置され、第２の接触パッド６Ｂは、前側と第２の側面２Ｂとの間の縁部付近に配置される。 The base body 20 is rectangular. Two contact pads 6 are applied to the front surface of the base body 20 and electrically contact the electrical components embedded in the base body 20. The contact pads 6 are applied near two opposite edges of the front surface. The first contact pad 6A is located near the edge between the front side and the first side surface 2A, and the second contact pad 6B is located near the edge between the front side and the second side surface 2B.

接触パッド６は、銅、ニッケル又は金のような導電性金属を含む。接触パッド６の寸法は、例えば、幅方向に３００μｍまで、長さ方向に１００μｍまで、高さ方向に５μｍ～１０μｍ程度、例えば６．５μｍである。長さ方向における２つの接触パッド６の間の距離は、例えば３００μｍ、又は好ましくは４００μｍを超える。 The contact pads 6 comprise a conductive metal such as copper, nickel or gold. The dimensions of the contact pads 6 are, for example, up to 300 μm in width, up to 100 μm in length and about 5 μm to 10 μm in height, for example 6.5 μm. The distance between two contact pads 6 in the length direction is, for example, 300 μm, or preferably more than 400 μm.

ダイオードは、例えばＡｌ２Ｏ３及び／又はＴｉＯ２を含むパッシベーション層２１を更に有する。パッシベーション層２１の厚さは１００ｎｍ－２００ｎｍである。パッシベーション層２１は、接触パッド６の接触領域を除いて、直方体ダイオードの六面全てに適用される。接触領域は、接触パッド６の表面の全面又は部分を含むことができる。 The diode further comprises a passivation layer 21, for example comprising Al2O3 and/or TiO2. The thickness of the passivation layer 21 is 100 nm-200 nm. The passivation layer 21 is applied to all six sides of the rectangular diode, except for the contact area of the contact pad 6. The contact area can include the entire surface or a part of the surface of the contact pad 6.

２つの接触パッド６の間で、漏れ電流又は寄生容量の影響が発生する可能性がある。より小さい接触パッド６は、接触パッド６間の距離を増加させることを可能にし、したがって前記寄生効果を減少させる。 Between two contact pads 6, leakage currents or parasitic capacitance effects can occur. Smaller contact pads 6 allow to increase the distance between the contact pads 6, thus reducing said parasitic effects.

ダイオードは、ダイオードの第１の側面及び第２の側面に、並びに第１の側面及び第２の側面に隣接する第１の側面及び第２の側面に対して垂直な側面の部分に適用される金属キャップ１１を更に備える。 The diode further comprises a metal cap 11 applied to the first and second sides of the diode and to portions of the sides perpendicular to the first and second sides that are adjacent to the first and second sides.

金属キャップ１１は、例えば直方体キャップの形状を有する。 The metal cap 11 has, for example, the shape of a rectangular cap.

金属キャップ１１は、異なる材料からなる幾つかの層を含む。例えば、金属キャップ１１は３つの層を備える。第１の層は、接触パッド及び／又はパッシベーション層２１と直接接触している。第１の層は、Ａｇ又はＣｕとポリマーとを含む軟質金属化混合物を含んでもよい。 The metal cap 11 includes several layers of different materials. For example, the metal cap 11 includes three layers. The first layer is in direct contact with the contact pad and/or the passivation layer 21. The first layer may include a soft metallization mixture including Ag or Cu and a polymer.

第２の層は、Ｃｕ又はＮｉのような導電性金属を含む。 The second layer comprises a conductive metal such as Cu or Ni.

第３の層は、酸化保護層として構成され、Ａｕ又はＳｎのような適切な金属を含む。 The third layer is configured as an oxidation protection layer and includes a suitable metal such as Au or Sn.

パッシベーション層（例えば、材料及び厚さ）を変更することによって、及びＳｉ基板のタイプ（例えば、非エピ材料又は低ドープ材料の選択）を変更することによっても、ＴＶＳダイオードの電気的性能（例えば、容量）を調整することができることに言及すべきである。これらの調整は、適切な接触パッド／金属キャップ設計と共に、開示されたダイオードが異なる電気的仕様（例えば、異なる静電容量）を必要とする様々な用途に対処することを可能にする。 It should be mentioned that the electrical performance (e.g., capacitance) of the TVS diode can be tuned by changing the passivation layer (e.g., material and thickness) and also by changing the type of Si substrate (e.g., selection of non-epi or low-doped material). These adjustments, together with appropriate contact pad/metal cap design, allow the disclosed diode to address various applications requiring different electrical specifications (e.g., different capacitance).

図３に示す実施形態では、更なる中間層４６が金属層４と接触パッド６との間に位置される。中間層４６は、金属層４と接触パッド６とを電気的及び機械的に接続する。中間層４６は、隣接する金属層４及び接触パッド６に強固に接合される。 In the embodiment shown in FIG. 3, a further intermediate layer 46 is positioned between the metal layer 4 and the contact pad 6. The intermediate layer 46 electrically and mechanically connects the metal layer 4 and the contact pad 6. The intermediate layer 46 is firmly bonded to the adjacent metal layer 4 and contact pad 6.

中間層４６によって、金属層４と接触パッド６との間の接続を改善及び強化することができる。 The intermediate layer 46 can improve and strengthen the connection between the metal layer 4 and the contact pad 6.

中間層４６は、導電性材料、例えば導電性金属を含む。 The intermediate layer 46 includes a conductive material, such as a conductive metal.

中間層４６の材料は、金属層４及び接触パッド６の材料と異なっていてもよい。 The material of the intermediate layer 46 may be different from the material of the metal layer 4 and the contact pad 6.

更に、図３の実施形態は、図２に示す実施形態と同様又は同一である。 Furthermore, the embodiment of FIG. 3 is similar or identical to the embodiment shown in FIG. 2.

１ ウェハ
２ ＴＶＳダイオードダイ
２Ａ ダイオードの第１の側面
２Ｂ ダイオードの第２の側面
３ 電気部品
４ 金属層
４６ 中間層
５ マスク層
６ 接触パッド
６Ａ 第１の接触パッド
６Ｂ 第２の接触パッド
７ 背面研削テープ
８ 転写テープ
９ フィルムフレームキャリア
１０ 熱剥離テープ
１１ 金属キャップ
２０ ベース本体
２１ パッシベーション層 1 Wafer 2 TVS diode die 2A First side of diode 2B Second side of diode 3 Electrical component 4 Metal layer 46 Intermediate layer 5 Mask layer 6 Contact pad 6A First contact pad 6B Second contact pad 7 Back grinding tape 8 Transfer tape 9 Film frame carrier 10 Thermal release tape 11 Metal cap 20 Base body 21 Passivation layer

Claims (15)

半導体ダイ（２）であって、半導体材料を含むベース本体（２０）と、前記ダイ（２）を電気的に接触させることができる接触パッド（６）が設けられた２つの接触領域（４）を有する表面と、前記接触パッド（６）に直接適用される２つの金属キャップ（１１）とを備える、半導体ダイ（２）。 A semiconductor die (2) comprising a base body (20) containing a semiconductor material, a surface having two contact areas (4) provided with contact pads (6) to which the die (2) can be electrically contacted, and two metal caps (11) applied directly to the contact pads (6). 前記接触領域（４）を前記接触パッド（６）と接続する２つの中間層（４６）を更に備える、請求項１に記載の半導体ダイ（２）。 The semiconductor die (2) of claim 1, further comprising two intermediate layers (46) connecting the contact areas (4) with the contact pads (6). 半導体ダイ（２）を製造する方法であって、
ダイ（２）を用意するステップであって、前記ダイ（２）が、半導体材料を含むベース本体（２０）と、前記ダイ（２）を電気的に接触させることができる接触パッド（６）が設けられた２つの接触領域（４）を有する表面とを備える、ステップと、電気的不動態化のためのパッシベーション層（２１）を前記ダイの前記表面に適用することによって、各接触パッド（６）への外部アクセスを可能にするパッシベーションのない領域をもたらすステップと、前記接触パッド（６）と直接接触する金属キャップ（１１）で前記ダイ（２）の前記表面の一部を金属化するステップと
を含む、方法。 A method for manufacturing a semiconductor die (2), comprising the steps of:
1. A method comprising the steps of: preparing a die (2), the die (2) having a base body (20) comprising a semiconductor material and a surface having two contact areas (4) provided with contact pads (6) by which the die (2) can be electrically contacted; applying a passivation layer (21) for electrical passivation to the surface of the die, thereby resulting in a passivation-free area allowing external access to each contact pad (6); and metallizing a part of the surface of the die (2) with a metal cap (11) in direct contact with the contact pads (6). 前記ステップが記載された順序で実行される、請求項３に記載の方法。 The method of claim 3, wherein the steps are performed in the order recited. 前記ダイ（２）を第１の側面で第１のメタライゼーションテープ（１０）に装填することと、少なくとも１つの接触パッド（６）を含む前記第１のメタライゼーションテープ（１０）によって覆われない前記ダイ（２）の連続領域を金属化することと、前記ダイ（２）を第２の側面で第２のメタライゼーションテープ（１０）に装填することと、少なくとも１つの接触パッド（６）を含む前記第２のメタライゼーションテープ（１０）によって覆われない前記ダイ（２）の連続領域を金属化することと
を含む、請求項４に記載の方法。 5. The method of claim 4, comprising: loading the die (2) on a first side into a first metallization tape (10); metallizing a continuous area of the die (2) not covered by the first metallization tape (10) including at least one contact pad (6); loading the die (2) on a second side into a second metallization tape (10); and metallizing a continuous area of the die (2) not covered by the second metallization tape (10) including at least one contact pad (6). 前記第１の金属化ステップの後に前記ダイ（２）の前記第２の側面の金属キャップ（１１）を硬化させることと、前記第２の金属化ステップの後に前記ダイ（２）の前記第１の側面の金属キャップ（１１）を硬化させることと
を更に含む、請求項５に記載の方法。 6. The method of claim 5, further comprising: hardening the metal cap (11) on the second side of the die (2) after the first metallization step; and hardening the metal cap (11) on the first side of the die (2) after the second metallization step. 前記第１の金属化ステップ及び任意選択的な第１の硬化ステップの後に前記ダイ（２）を前記第１のメタライゼーションテープ（１０）から解放することと、第２の金属化ステップ及び任意選択的な第２の硬化ステップの後に前記ダイ（２）を前記第２のメタライゼーションテープ（１０）から解放することと
を更に含む、請求項５又は６に記載の方法。 7. The method of claim 5 or 6, further comprising: releasing the die (2) from the first metallization tape (10) after the first metallization step and an optional first curing step; and releasing the die (2) from the second metallization tape (10) after a second metallization step and an optional second curing step. 前記ダイ（２）が前記金属キャップ（１１）を介して外部接触される、請求項３から７のいずれか一項に記載の方法。 The method according to any one of claims 3 to 7, wherein the die (2) is externally contacted via the metal cap (11). 前記金属キャップ（１１）が前記パッシベーション層（２１）に直接に適用される、請求項３から８のいずれか一項に記載の方法。 The method according to any one of claims 3 to 8, wherein the metal cap (11) is applied directly to the passivation layer (21). 前記金属キャップ（１１）が浸漬プロセスによって適用される、請求項３から９のいずれか一項に記載の方法。 The method according to any one of claims 3 to 9, wherein the metal cap (11) is applied by a dipping process. 前記金属キャップ（１１）は、２つ又は３つの金属化ステップによって適用される２つ又は３つの異なる積層を備える、請求項３から１０のいずれか一項に記載の方法。 The method according to any one of claims 3 to 10, wherein the metal cap (11) comprises two or three different laminations applied by two or three metallization steps. 前記金属キャップ（１１）は、前記接触パッド（６）の金属又は金属の混合物とは異なる金属又は金属の混合物を備える、請求項３から１１のいずれか一項に記載の方法。 The method according to any one of claims 3 to 11, wherein the metal cap (11) comprises a metal or a mixture of metals different from the metal or mixture of metals of the contact pad (6). 前記パッシベーション層（２１）が原子層堆積プロセスによって適用される、請求項３から１２のいずれか一項に記載の方法。 The method according to any one of claims 3 to 12, wherein the passivation layer (21) is applied by an atomic layer deposition process. 前記原子層堆積プロセスが８０℃未満の温度で実行される、請求項１３に記載の方法。 The method of claim 13, wherein the atomic layer deposition process is carried out at a temperature less than 80°C. 幾つかのダイ（２）がウェハ（１）レベルチップスケールパッケージプロセスによって並行して製造される、請求項３から１４のいずれか一項に記載の方法。 The method according to any one of claims 3 to 14, wherein several dies (2) are manufactured in parallel by a wafer (1) level chip scale packaging process.
JP2023563004A 2021-04-22 2022-03-08 METALIZED SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - Patent application Pending JP2024515633A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102021110276.6 2021-04-22
DE102021110276 2021-04-22
PCT/EP2022/055910 WO2022223195A1 (en) 2021-04-22 2022-03-08 Metallized semiconductor die and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2024515633A true JP2024515633A (en) 2024-04-10

Family

ID=81074267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023563004A Pending JP2024515633A (en) 2021-04-22 2022-03-08 METALIZED SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - Patent application

Country Status (5)

Country Link
US (1) US20240194623A1 (en)
EP (1) EP4327355A1 (en)
JP (1) JP2024515633A (en)
CN (1) CN117203752A (en)
WO (1) WO2022223195A1 (en)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2797996B1 (en) * 1999-08-25 2003-10-03 Gemplus Card Int METHOD FOR PROTECTING INTEGRATED CIRCUIT CHIPS BY INSULATING THIN FILM DEPOSITION
JP2002184645A (en) 2000-12-12 2002-06-28 Fdk Corp Surface-mounting type chip component
TW497126B (en) * 2001-05-03 2002-08-01 Comchip Technology Co Ltd Discrete circuit component and its manufacturing method
DE102005004160B4 (en) 2005-01-28 2010-12-16 Infineon Technologies Ag CSP semiconductor device, semiconductor circuitry, and method of fabricating the CSP semiconductor device
EP2390909A1 (en) 2010-05-24 2011-11-30 Jerry Hu Miniature packaging for discrete circuit components
JP2012004480A (en) 2010-06-21 2012-01-05 Tdk Corp Method for manufacturing electronic component and electronic component
DE202011002810U1 (en) 2011-02-16 2011-06-09 Inter Ikea Systems B.V. Mechanism for sliding door
US9082832B2 (en) * 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US8508035B2 (en) * 2011-12-02 2013-08-13 Nxp B.V. Circuit connector apparatus and method therefor
DE102011056515B4 (en) 2011-12-16 2023-12-07 Tdk Electronics Ag Electrical component and method for producing an electrical component
KR20180094345A (en) 2017-02-15 2018-08-23 주식회사 모다이노칩 Chip package

Also Published As

Publication number Publication date
WO2022223195A1 (en) 2022-10-27
EP4327355A1 (en) 2024-02-28
CN117203752A (en) 2023-12-08
US20240194623A1 (en) 2024-06-13

Similar Documents

Publication Publication Date Title
US20230207502A1 (en) Semiconductor device with redistribution layers formed utilizing dummy substrates
TWI602276B (en) Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different cte insulating layers
CN100524725C (en) Semiconductor device and manufacturing method of the same
TWI508198B (en) Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8728871B2 (en) Method for fabricating electronic device package
US20060046348A1 (en) Semiconductor chip packages and methods for fabricating the same
EP1734576A1 (en) Semiconductor device having through electrode and method of manufacturing the same
KR20090057894A (en) Semiconductor device and method of making integrated passive devices
TW201117686A (en) Semiconductor device and method of forming integrated passive device
US8378479B2 (en) Semiconductor device and method for fabricating semiconductor device
US9583413B2 (en) Semiconductor device
US7491572B2 (en) Method for fabricating an image sensor mounted by mass reflow
US7746213B2 (en) Device and method for manufacturing the same
US20040127011A1 (en) [method of assembling passive component]
JP2024515633A (en) METALIZED SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING SAME - Patent application
CN117374020A (en) Chip scale package
CN101188204B (en) Semiconductor device and manufacturing method therefor
JP5537119B2 (en) Lid, lid manufacturing method and electronic device manufacturing method
KR101457883B1 (en) Flip chip structure and method of manufacture
KR100948999B1 (en) Semiconductor package fabricating?method
EP2390909A1 (en) Miniature packaging for discrete circuit components
JP3406710B2 (en) Package for storing semiconductor elements
CN111710613A (en) Wafer-level chip packaging method
CN116865709A (en) Surface acoustic wave device
CN114975137A (en) Wafer level packaging structure and preparation method thereof

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231208

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20231208