JP2024101333A - Power Conversion Equipment - Google Patents

Abstract

[Problem] To provide a power conversion device in which the size of the capacitor is reduced. [Solution] An inverter circuit 100 includes a P bus bar connected to a high potential terminal P of a battery 200, an N bus bar connected to a low potential terminal N, and an M bus bar that is a midpoint M between the P bus bar and the N bus bar. Furthermore, the inverter circuit 100 includes a PM capacitor 30 connected to the P bus bar and the M bus bar, an MN capacitor 40 connected to the M bus bar and the N bus bar, and a PN capacitor 50 connected to the P bus bar and the N bus bar. [Selected Figure] Figure 1

Description

This disclosure relates to a power conversion device.

A conventional example of a multilevel inverter is a power conversion device disclosed in Patent Document 1. The power conversion device has two smoothing capacitors connected in series.

JP 2013-102627 A

The power conversion device is provided with two smoothing capacitors for the purposes of suppressing the allowable voltage fluctuation at the midpoint between the two smoothing capacitors and reducing the current ripple flowing out of the power conversion device. However, the power conversion device requires a large capacitor capacity to reduce the current ripple. This causes a problem in that the smoothing capacitor becomes large in size. In addition, further improvements are required for the power conversion device in the above respects and in other respects not mentioned.

One disclosed objective is to provide a power conversion device in which the size of the capacitor is reduced.

The power conversion device disclosed herein is
A power conversion device capable of dividing an input DC voltage into a plurality of values and outputting a plurality of voltage levels,
A high potential wiring (71) connected to the positive electrode of the power source;
A low potential wiring (72) connected to the negative electrode of the power supply;
At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring;
a first capacitor (30) connected to the high potential wiring and the midpoint wiring;
a second capacitor (40) connected to the midpoint wiring and the low potential wiring;
and at least one third capacitor (50) connected to the high potential wiring and the low potential wiring.

The power conversion device disclosed herein is provided with at least one third capacitor connected to the high potential wiring and the low potential wiring. This allows the power conversion device to reduce the total capacity of the first capacitor, the second capacitor, and the third capacitor. This allows the power conversion device to reduce the size of the first capacitor, the second capacitor, and the third capacitor.

The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference characters in parentheses in this section are illustrative of the corresponding relationships with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become clearer with reference to the detailed description that follows and the accompanying drawings.

1 is a circuit diagram showing a schematic configuration of an inverter circuit according to a first embodiment. FIG. 2 is a cross-sectional view showing a schematic configuration of an inverter circuit. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 . FIG. 3 is a plan view taken from the direction of the arrow IV in FIG. 2 . FIG. 2 is a perspective view showing the arrangement of a capacitor device. FIG. 11 is a perspective view showing the arrangement of a capacitor device in a second embodiment. FIG. 11 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a third embodiment. FIG. 13 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a fourth embodiment. FIG. 13 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a fifth embodiment. FIG. 13 is a cross-sectional view showing a schematic configuration of an inverter circuit according to a sixth embodiment.

Below, several embodiments for implementing the present disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in the preceding embodiment may be given the same reference numerals, and duplicated descriptions may be omitted. In each embodiment, when only a part of the configuration is described, the other parts of the configuration may be applied by referring to the other embodiment described previously.

First Embodiment
An inverter circuit 100 according to a first embodiment will be described with reference to Figs. 1 to 5. The inverter circuit 100 is configured to divide an input DC voltage into a plurality of values and to be capable of outputting a plurality of levels of voltage. The inverter circuit 100 is a so-called multilevel inverter. Whereas a two-level inverter can output voltages of +E, -E, 0, and two levels other than 0, assuming that the voltage of the battery 200 is E, a multilevel inverter can output voltages of three or more levels. In this embodiment, a three-level inverter circuit 100 is adopted as an example.

The inverter circuit 100 can be mounted on a moving object such as a vehicle or an aircraft. As shown in FIG. 1, the inverter circuit 100 is electrically connected to a battery 200 and a motor 300. The motor 300 is a three-phase motor equipped with a U-phase coil 301, a V-phase coil 302, and a W-phase coil 303. For example, a motor generator can be used as the motor 300. The inverter circuit 100 converts the DC power output by the battery 200 into three-phase AC power and supplies the three-phase AC power to the motor 300. The inverter circuit 100 corresponds to a power conversion device.

<Circuit configuration of inverter circuit 100>
The circuit configuration of an inverter circuit 100 will be described with reference to Fig. 1. The inverter circuit 100 includes switching elements 11 to 16, a U-phase middle section 21, a V-phase middle section 22, a W-phase middle section 23, and a capacitor device 60. Fig. 1 illustrates a PM capacitor 30, an MN capacitor 40, and a PN capacitor 50 included in the capacitor device 60.

Switching elements 11-16 can be MOSFETs, IGBTs, or the like. Switching elements 11-16 can also be made primarily of wide band gap semiconductors such as Si or SiC. Each gate electrode of switching elements 11-16 is connected to an electronic control device (not shown). Switching elements 11-16 are driven and controlled by the electronic control device.

The switching elements 11 to 16 include a U-phase upper arm element 11, a U-phase lower arm element 12, a V-phase upper arm element 13, a V-phase lower arm element 14, a W-phase upper arm element 15, and a W-phase lower arm element 16.

The U-phase upper arm element 11 and the U-phase lower arm element 12 are connected in series between the high potential side terminal (P) and the low potential side terminal (N) of the battery 200. The source terminal of the U-phase upper arm element 11 and the drain terminal of the U-phase lower arm element 12 are connected to the U-phase coil 301. The U-phase upper arm element 11 and the U-phase lower arm element 12 can be collectively referred to as the U-phase arm.

The V-phase upper arm element 13 and the V-phase lower arm element 14 are connected in series between the high potential terminal and the low potential terminal of the battery 200. The source terminal of the V-phase upper arm element 13 and the drain terminal of the V-phase lower arm element 14 are connected to the V-phase coil 302. The V-phase upper arm element 13 and the V-phase lower arm element 14 can be collectively referred to as the V-phase arm.

The W-phase upper arm element 15 and the W-phase lower arm element 16 are connected in series between the high potential terminal and the low potential terminal of the battery 200. The source terminal of the W-phase upper arm element 15 and the drain terminal of the W-phase lower arm element 16 are connected to the W-phase coil 303. The W-phase upper arm element 15 and the W-phase lower arm element 16 can be collectively referred to as the V-phase arm.

In this way, each arm is connected in series between the P bus bar 71 and the N bus bar 72, which will be described later. Note that with respect to the structure of the switching elements 11 to 16, the battery 200, which will be described later, corresponds to the power source. The high potential terminal corresponds to the positive electrode. The low potential terminal corresponds to the negative electrode.

The U-phase middle section 21, the V-phase middle section 22, and the W-phase middle section 23 are connected to the midpoint (neutral point) M between the high potential and the low potential and each arm. Each of the middle sections 21 to 23 includes two switching elements. The switching elements can be the same as the switching elements 11 to 16 described above. The switching elements have their gate electrodes connected to the electronic control device. The switching elements are driven and controlled by the electronic control device. The midpoint M can be considered to be a point of intermediate potential between the high potential and the low potential. The midpoint M is also a point between the PM capacitor 30 and the MN capacitor 40.

The U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b as switching elements. The drain terminal of the first U-phase middle element 21a is connected to the midpoint M, and the source terminal is connected to the source terminal of the second U-phase middle element 21b. The drain terminal of the second U-phase middle element 21b is connected to the source terminal of the U-phase upper arm element 11 and the drain terminal of the U-phase lower arm element 12.

The V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b as switching elements. The first V-phase middle element 22a has a drain terminal connected to the midpoint M and a source terminal connected to the source terminal of the second V-phase middle element 22b. The drain terminal of the second V-phase middle element 22b is connected to the source terminal of the V-phase upper arm element 13 and the drain terminal of the V-phase lower arm element 14.

The W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b as switching elements. The first W-phase middle element 23a has a drain terminal connected to the midpoint M and a source terminal connected to the source terminal of the second W-phase middle element 23b. The drain terminal of the second W-phase middle element 23b is connected to the source terminal of the W-phase upper arm element 15 and the drain terminal of the W-phase lower arm element 16. The structures of the U-phase middle section 21, V-phase middle section 22, and W-phase middle section 23 will be described later.

The capacitor device 60 includes a PM capacitor 30, an MN capacitor 40, and a PN capacitor 50 as smoothing capacitors. The PM capacitor 30 is connected to the high potential side terminal and the midpoint M. The MN capacitor 40 is connected to the midpoint M and the low potential side terminal. Thus, the PM capacitor 30 and the MN capacitor 40 are connected in series.

The PM capacitor 30 and the MN capacitor 40 are provided mainly for voltage stabilization and current ripple absorption. In other words, the PM capacitor 30 and the MN capacitor 40 are provided to suppress the allowable voltage fluctuation at the midpoint M and to reduce the current ripple that flows out of the inverter circuit 100. The PM capacitor 30 corresponds to the first capacitor. The MN capacitor 40 corresponds to the second capacitor.

The PN capacitor 50 is connected to the high potential terminal and the low potential terminal. Therefore, the PN capacitor 50 is connected in parallel to the PM capacitor 30 and the MN capacitor 40. The PN capacitor 50 is provided to absorb current ripple. In other words, the PN capacitor 50 is provided to reduce the current ripple that flows out of the inverter circuit 100. The PN capacitor 50 corresponds to the third capacitor.

In the inverter circuit 100, a small capacitance is required to suppress the allowable voltage fluctuation at the midpoint M, whereas a large capacitance is required to reduce the current ripple flowing out to the outside. Therefore, the inverter circuit 100 is provided with a PN capacitor 50. As described above, this PN capacitor 50 is connected in parallel with the PM capacitor 30 and the MN capacitor 40. Therefore, the inverter circuit 100 can reduce the total capacitance of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50. Therefore, the inverter circuit 100 can reduce the size of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50.

The present disclosure can also be applied to a diode clamp type (T type) inverter circuit 100. The present disclosure can also be used with an inverter circuit 100 with N levels (N=4) or more. In this case, the intermediate potential is N-2. The number of PN capacitors 50 is N-1.

<Structure of inverter circuit 100>
The structure of the inverter circuit 100 will be described with reference to Figures 2 to 5. In the inverter circuit 100, a capacitor device 60 and a structure in which the semiconductor devices 10, 20 and a cooler 90 are integrally assembled are arranged side by side. In the drawings, the arrangement direction of the capacitor device 60 and the structure is indicated by arrow AD. Note that in Figure 5, bus bars 71 to 73, insulating member 80, etc. are omitted. The same applies to Figure 6, which will be described later.

As shown in Figures 2 and 3, the inverter circuit 100 also includes bus bars 71 to 74 that connect the capacitors 30 to 50 to the semiconductor devices 10 and 20. The bus bars 71 to 74 are conductive members whose main component is copper or the like. The bus bars 71 to 74 are flat plate-shaped members.

The P bus bar 71 is connected to the high-potential terminal. The terminal connected to the high-potential terminal is connected to the P bus bar 71. The P bus bar 71 corresponds to the high-potential wiring.

The N bus bar 72 is connected to the low-potential terminal. The N bus bar 72 corresponds to low-potential wiring. The terminal connected to the low-potential terminal is connected to the N bus bar 72.

The M bus bar 73 constitutes the midpoint M. The M bus bar 73 has a potential between the P bus bar 71 and the N bus bar 72. The M bus bar 73 is connected to the PM capacitor 30 and the MN capacitor 40. The terminal connected to the midpoint M is connected to the M bus bar 73. The M bus bar 73 corresponds to the midpoint wiring.

The O bus bar 74 is an output terminal. The inverter circuit 100 has an O bus bar 74 connected to each of the U-phase coil 301, the V-phase coil 302, and the W-phase coil 303.

In this embodiment, as an example, an example is adopted in which an insulating member 80 is provided to electrically insulate the components from each other. The insulating member 80 is provided between the P bus bar 71 and the M bus bar 73, and between each bus bar 71, 73 and the PM capacitor 30. The insulating member 80 is also provided between the M bus bar 73 and the N bus bar 72, and between each bus bar 72, 73 and the MN capacitor 40. However, if electrical insulation is possible, there is no need to provide the insulating member 80.

The semiconductor devices 10 and 20 are, for example, covered with an electrically insulating sealing resin with two bare-chip-shaped switching elements connected to each other. As shown in Figures 2 and 4, the tips of the terminals 1 to 5 of the semiconductor devices 10 and 20 protrude from the sealing resin. The inverter circuit 100 includes a plurality of semiconductor devices 10 and a plurality of semiconductor devices 20. The semiconductor devices 10 and 20 are arranged side by side and assembled to a cooler 90. Note that the cooler 90 has been omitted from Figure 4 to simplify the drawing.

The inverter circuit 100 includes three semiconductor devices 10 that constitute each arm. The semiconductor device 10 of the U-phase arm includes a U-phase upper arm element 11 and a U-phase lower arm element 12. The semiconductor device 10 of the V-phase arm includes a V-phase upper arm element 13 and a V-phase lower arm element 14. The semiconductor device 10 of the W-phase arm includes a W-phase upper arm element 15 and a W-phase lower arm element 16. The semiconductor device 10 also includes a P terminal 1, an N terminal 2, an O terminal 3, and a signal terminal 5. The semiconductor device 10 can also be called an arm device.

The inverter circuit 100 includes three semiconductor devices 20 constituting each of the middle sections 21 to 23. The semiconductor device 20 in the U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b. The semiconductor device 20 in the V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b. The semiconductor device 20 in the W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b. The semiconductor device 20 also includes an O terminal 3, an M terminal 4, and a signal terminal 5. The semiconductor device 20 can also be called a middle device.

As shown in FIG. 4, P terminal 1 is connected to P bus bar 71. N terminal 2 is connected to N bus bar 72. O terminal 3 is connected to O bus bar 74. M terminal 4 is connected to M bus bar 73. As shown in FIG. 2, signal terminal 5 is connected to wiring board 110. Note that wiring board 110 is a board in which conductive wiring is provided on an insulating base material such as resin. Wiring board 110 is connected to an electronic control device.

The cooler 90 is configured to circulate a refrigerant such as water to cool each of the semiconductor devices 10 and 20. The cooler 90 sandwiches each of the semiconductor devices 10 and 20 between the areas through which the refrigerant flows.

As a result, the bus bars 71 to 74 are arranged such that their connection portions with the terminals 1 to 4 are close to the cooler 90. As described above, the bus bars 71 to 74 are also connected to the terminals 1 to 4 of the semiconductor devices 10 and 20, which are cooled by the cooler 90. As a result, the bus bars 71 to 74 are cooled by the cooler 90 together with the semiconductor devices 10 and 20. It can also be said that one end of the bus bars 71 to 73 is connected to the structure, and the other end is connected to the capacitor device 60.

As shown in Figures 2 and 3, the capacitor device 60 includes the capacitors 30-50, a capacitor case 61, and a sealing resin part 63. The capacitor case 61 houses the capacitors 30-50, and is a case with an opening 62 in one part. The capacitor case 61 is provided with the sealing resin part 63 while housing the capacitors 30-50. In other words, the capacitor case 61 has the capacitors 30-50 and the sealing resin part 63 in the housing space. The capacitors 30-50 are sealed with the sealing resin part 63.

In addition, a portion of the P bus bar 71, N bus bar 72, and M bus bar 73 are arranged inside the capacitor case 61 to connect to each of the capacitors 30 to 50. The portions of the P bus bar 71, N bus bar 72, and M bus bar 73 arranged inside the capacitor case 61 are sealed with a sealing resin portion 63. In addition, as shown in FIG. 3, the P bus bar 71, N bus bar 72, and M bus bar 73 protrude from the opening 62.

In this way, the capacitor device 60 has three capacitors 30 to 50 held together. The capacitor device 60 can also be called a capacitor structure. Furthermore, each of the capacitors 30 to 50 may be made up of a single capacitor element, or may be made up of multiple capacitor elements.

As shown in FIG. 2, the PM capacitor 30 has a first PM terminal 31 and a second PM terminal 32. The first PM terminal 31 is connected to the P bus bar 71. The second PM terminal 32 is connected to the M bus bar 73.

The MN capacitor 40 has a first MN terminal 41 and a second MN terminal 42. The first MN terminal 41 is connected to the M bus bar 73. The second MN terminal 42 is connected to the N bus bar 72.

The PN capacitor 50 has a first PN terminal 51 and a second PN terminal 52. The first PN terminal 51 is connected to the P bus bar 71. The second PN terminal 52 is connected to the N bus bar 72.

As shown in FIG. 2, the PM capacitor 30 and the MN capacitor 40 are arranged closer to the cooler 90 than the PN capacitor 50. In this embodiment, as an example, they are arranged along the arrangement direction AD in the following order: cooler 90, PM capacitor 30, MN capacitor 40, and PN capacitor 50. For this reason, the PM capacitor 30 and MN capacitor 40 are more easily cooled by the cooler 90 than the PN capacitor 50. It can be said that the inverter circuit 100 has a stronger cooling power for the PM capacitor 30 and the MN capacitor 40 than for the PN capacitor 50.

In addition, the length of the P bus bar 71 from the connection point with the structure to the connection point with the PM condenser 30 is shorter than the length from the connection point with the structure to the connection point with the PN condenser 50. Therefore, the PM condenser 30 is more easily cooled by the P bus bar 71, which is cooled by the cooler 90, than the PN condenser 50.

On the other hand, the length of the N bus bar 72 from the connection point with the structure to the connection point with the MN capacitor 40 is shorter than the length from the connection point with the structure to the connection point with the PN capacitor 50. Therefore, the MN capacitor 40 is more easily cooled by the N bus bar 72 cooled by the cooler 90 than the PN capacitor 50.

However, the ripple current caused by heat generation is larger in the PM capacitor 30 and the MN capacitor 40 than in the PN capacitor 50. Therefore, in this disclosure, the PM capacitor 30 and the MN capacitor 40 are arranged closer to the cooler 90 than the PN capacitor 50. Therefore, the inverter circuit 100 can suppress the heat of the PM capacitor 30 and the MN capacitor 40. Therefore, the inverter circuit 100 can increase the allowable current of the PM capacitor 30 and the MN capacitor 40. In other words, the inverter circuit 100 can increase the allowable current more than a configuration in which the PN capacitor 50 is closer to the cooler 90 than the PM capacitor 30 and the MN capacitor 40. Note that the positional relationship between the cooler 90 and each of the capacitors 30 to 50 described above can be applied to other embodiments.

The thermal conductivity of the P bus bar 71 and the N bus bar 72 may be higher at the portions connected to the PM capacitor 30 and the MN capacitor 40 than at the portions connected to the PN capacitor 50. For example, the portions connected to the PN capacitor 50 are made primarily of copper. On the other hand, the portions connected to the PM capacitor 30 and the MN capacitor 40 are made primarily of silver. This also allows the inverter circuit 100 to increase the allowable current of the PM capacitor 30 and the MN capacitor 40.

Furthermore, as shown in Figures 2 and 5, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction intersecting the alignment direction AD. In this embodiment, as an example, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction perpendicular to the alignment direction AD.

In more detail, the PM capacitor 30 and the MN capacitor 40 are stacked so that the second PM terminal 32 of the PM capacitor 30 faces the first MN terminal 41 of the MN capacitor 40. A part of the M bus bar 73 is disposed between the PM capacitor 30 and the MN capacitor 40. Therefore, the second PM terminal 32 and the first MN terminal 41 are connected to the same M bus bar 73.

For this reason, the inverter circuit 100 can be made smaller in size along the arrangement direction AD than a configuration in which the PM capacitor 30 and the MN capacitor 40 are arranged along the arrangement direction AD. It can also be said that the inverter circuit 100 can be made smaller in size in a direction perpendicular to the stacking direction of the PM capacitor 30 and the MN capacitor 40. The PN capacitor 50 is arranged in the arrangement direction AD relative to the PM capacitor 30 and the MN capacitor 40. It can also be said that the PM capacitor 30 and the MN capacitor 40 are stacked in the thickness direction of both capacitors 30, 40. It can also be said that the PM capacitor 30 and the MN capacitor 40 are simply stacked.

In this embodiment, as an example, capacitors 30 to 50 arranged as described above are used. However, the present disclosure is not limited to this.

Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Below, the second to sixth embodiments will be described as other forms of the present disclosure.

Second Embodiment
An inverter circuit 100 according to the second embodiment will be described with reference to Fig. 6. In this embodiment, differences from the first embodiment will be mainly described. In this embodiment, the positional relationship between the PM capacitor 30 and the MN capacitor 40 is different from that in the first embodiment.

The PM capacitor 30 and the MN capacitor 40 are arranged in parallel. The PM capacitor 30 and the MN capacitor 40 are arranged such that the first PM terminal 31 and the first MN terminal 41 are on the same imaginary plane. The PM capacitor 30 and the MN capacitor 40 are arranged such that the second PM terminal 32 and the second MN terminal 42 are on another imaginary plane.

Therefore, the inverter circuit 100 can reduce the size of the PM capacitor 30 and the MN capacitor 40 in the direction perpendicular to the capacitor arrangement direction, compared to a configuration in which both capacitors 30, 40 are stacked. Also, like the first embodiment, the inverter circuit 100 can reduce the size of each of the capacitors 30 to 50. Note that the PN capacitor 50 is arranged in parallel with both the PM capacitor 30 and the MN capacitor 40. The first PN terminal 51 is arranged on the same imaginary plane as the first PM terminal 31 and the first MN terminal 41. The second PN terminal 52 is arranged on the same imaginary plane as the second PM terminal 32 and the second MN terminal 42.

Third Embodiment
The inverter circuit 100 of the third embodiment will be described with reference to FIG. 7. In this embodiment, differences from the first embodiment will be mainly described. In this embodiment, the positional relationship between the PM capacitor 30 and the MN capacitor 40 is different from that of the first embodiment. The PM capacitor 30 and the MN capacitor 40 are arranged to be shifted in the arrangement direction AD. As in the first embodiment, the inverter circuit 100 can reduce the size of each of the capacitors 30 to 50.

(Fourth embodiment)
An inverter circuit 100 according to the fourth embodiment will be described with reference to Fig. 8. In this embodiment, differences from the second embodiment will be mainly described. In this embodiment, the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40 is different from that of the second embodiment.

The PN capacitor 50 is arranged in parallel with the PM capacitor 30 and the MN capacitor 40. In other words, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 are arranged in a straight line.

As a result, the inverter circuit 100 can be made smaller in size in the direction perpendicular to the capacitor arrangement direction of the capacitors 30 to 50 than a configuration in which the capacitors 30 to 50 are arranged in a stacked manner. Also, as in the first embodiment, the inverter circuit 100 can make each of the capacitors 30 to 50 smaller in size.

Fifth Embodiment
An inverter circuit 100 according to the fifth embodiment will be described with reference to Fig. 9. In this embodiment, differences from the first embodiment will be mainly described. In this embodiment, the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40 is different from that of the first embodiment.

The PN capacitor 50 is arranged in a stacked manner together with the PM capacitor 30 and the MN capacitor 40. The capacitors 30 to 50 are arranged so that their terminals do not face each other. The first PN terminal 51 is arranged parallel to the same imaginary plane as the first PM terminal 31 and the first MN terminal 41. The second PN terminal 52 is arranged parallel to the same imaginary plane as the second PM terminal 32 and the second MN terminal 42. The inverter circuit 100 can reduce the size of the capacitors 30 to 50 in the direction perpendicular to the capacitor arrangement direction, compared to a configuration in which the capacitors 30 to 50 are arranged in parallel. The inverter circuit 100 can also reduce the size of the capacitors 30 to 50, as in the first embodiment.

Sixth Embodiment
An inverter circuit 100 according to the sixth embodiment will be described with reference to Fig. 10. In this embodiment, differences from the first embodiment will be mainly described. In this embodiment, the configurations of the P bus bar 71 and the N bus bar 72 are different from those of the first embodiment.

The P bus bar 71 includes a PM bus bar portion 71m connected to the PM capacitor 30, and a PN bus bar portion 71p connected to the PN capacitor 50. The N bus bar 72 includes an MN bus bar portion 72m connected to the MN capacitor 40, and a PN bus bar portion 72p connected to the PN capacitor 50. The PM bus bar portion 71m has a larger cross-sectional area than the PN bus bar portion 71p. The MN bus bar portion 72m has a larger cross-sectional area than the PN bus bar portion 72p.

This also allows the inverter circuit 100 to increase the allowable current of the PM capacitor 30 and the MN capacitor 40. Also, like the first embodiment, the inverter circuit 100 can reduce the size of each of the capacitors 30 to 50.

Although the present disclosure has been described with reference to an embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, while various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more, or less are also within the scope and concept of the present disclosure.

100... inverter circuit, 1... P terminal, 2... N terminal, 3... O terminal, 4... M terminal, 5... signal terminal, 10, 20... semiconductor device, 11-16... switching elements, 11... U-phase upper arm element, 12... U-phase lower arm element, 13... V-phase upper arm element, 14... V-phase lower arm element, 15... W-phase upper arm element, 16... W-phase lower arm element, 21... U-phase middle section, 22... V-phase middle section, 23... W-phase middle section, 21a... first U-phase middle element, 21b... second U-phase middle element, 22a... first V-phase middle element, 22b... second V-phase middle element, 23a... first W-phase middle element, 23b... second W-phase middle element, 30... PM capacitor, 31...first PM terminal, 32...second PM terminal, 40...MN capacitor, 41...first MN terminal, 42...second MN terminal, 50...PN capacitor, 51...first PN terminal, 52...second PN terminal, 60...capacitor device, 61...capacitor case, 62...opening, 63...sealing resin part, 71...P bus bar, 71m...PM bus bar part, 71p...PN bus bar part, 72...N bus bar, 72m...MN bus bar part, 72p...PN bus bar part, 73...M bus bar, 74...O bus bar, 80...insulating member, 90...cooler, 110...wiring board, 200...battery, 300...motor, 301...U-phase coil, 302...V-phase coil, 303...W-phase coil

Claims (9)

A power conversion device capable of dividing an input DC voltage into a plurality of values and outputting a plurality of voltage levels,
A high potential wiring (71) connected to the positive electrode of the power source;
A low potential wiring (72) connected to the negative electrode of the power source;
At least one midpoint wiring (73) having a potential between the high potential wiring and the low potential wiring;
a first capacitor (30) connected to the high potential wiring and the midpoint wiring;
a second capacitor (40) connected to the midpoint wiring and the low potential wiring;
and at least one third capacitor (50) connected to the high potential wiring and the low potential wiring. a plurality of semiconductor devices (10, 20) including switching elements connected to the high potential wiring, the low potential wiring, and the midpoint wiring,
A cooler (90) for cooling the semiconductor device,
The power conversion device according to claim 1 , wherein the first capacitor and the second capacitor are disposed closer to the cooler than the third capacitor. The power conversion device according to claim 1 or 2, wherein the cross-sectional areas of the high-potential wiring and the low-potential wiring connected to the first capacitor and the second capacitor are larger than the cross-sectional areas of the parts connected to the third capacitor. The power conversion device according to claim 1 or 2, wherein the thermal conductivity of the high-potential wiring and the low-potential wiring is higher at the portions connected to the first capacitor and the second capacitor than at the portions connected to the third capacitor. the first capacitor, the second capacitor, and the third capacitor are integrally held to form a capacitor device,
The power conversion device according to claim 2 , wherein the capacitor device is arranged alongside the cooler. The power conversion device according to claim 5, wherein the first capacitor and the second capacitor are arranged in a stacked configuration. The power conversion device according to claim 6, wherein the third capacitor is stacked together with the first capacitor and the second capacitor. The power conversion device according to claim 5, wherein the first capacitor and the second capacitor are arranged in parallel. The power conversion device according to claim 8, wherein the third capacitor is arranged in parallel with the first capacitor and the second capacitor.

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